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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Single Crystal Semiconductor Layer On Insulating Substrate (soi)

Single Crystal Semiconductor Layer On Insulating Substrate (soi)

Single Crystal Semiconductor Layer On Insulating Substrate (soi) patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

04/17/14 - 20140103435 - Vertical source/drain junctions for a finfet including a plurality of fins
Fin-defining mask structures are formed over a semiconductor material layer. A semiconductor material portion is formed by patterning the semiconductor material layer, and a disposable gate structure is formed over the fin-defining mask structures. After formation of a disposable template layer, the disposable gate structure is removed. A plurality of...

04/17/14 - 20140103436 - Extremely thin semiconductor-on-insulator with back gate contact
A structure is provided in which the back gate regions are physically separated from one another as opposed to using reversed biased pn junction diodes. In the present disclosure, the back gate regions can be formed first through a buried dielectric material of an extremely thin semiconductor-on-insulator (ETSOI) substrate. After...

04/17/14 - 20140103437 - Random doping fluctuation resistant finfet
An improved fin field-effect transistor (FinFET) is built on a compound fin, which has a doped core and lightly doped epitaxial channel region between that core and the gate dielectric. The improved structure reduces FinFET random doping fluctuations when doping is used to control threshold voltage. Further, the transistor design...

04/17/14 - 20140103438 - Multi-gate semiconductor devices and methods of forming the same
A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also...

04/10/14 - 20140097493 - Cells including at least one fin field effect transistor and semiconductor integrated circuits including the same
A semiconductor integrated circuit (IC) may comprise at least one cell comprising at least one fin field-effect transistor (FET). The at least one cell may comprise a plurality of fins that extend in a first direction and are arranged in parallel to each other in a second direction that is...

04/03/14 - 20140091390 - Protection layer for halftone process of third metal
A thin-film transistor having a protection layer for a planarization layer. The protection layer prevents reduction of the planarization layer during an ashing process, thereby preventing the formation of a steeply tapered via hole through the planarization layer. In this manner, the via hole may be coated with a conductive...

04/03/14 - 20140091391 - Field-effect-transistor with self-aligned diffusion contact
Embodiments of the present invention provide an array of fin-type transistors formed on top of an oxide layer. At least a first and a second of the fin-type transistors have their respective source and drain contacts being formed inside the oxide layer, with one of the contacts of the first...

03/27/14 - 20140084370 - Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates
Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional germanium-containing body is disposed on a semiconductor release layer disposed on the insulating structure. The three-dimensional germanium-containing...

03/27/14 - 20140084371 - Multi-gate field effect transistor devices
A field effect transistor device includes a substrate, a substrate insulator layer arranged on the substrate, a semiconductor fin arranged on the substrate insulator layer, a source region arranged on a portion of the substrate insulator layer, a drain region arranged on a portion of the substrate insulator layer, a...

03/20/14 - 20140077296 - Method and structure for finfet with finely controlled device width
A structure and method for fabricating finFETs of varying effective device widths is disclosed. Groups of fins are shortened by a predetermined amount to achieve an effective device width that is equivalent to a real (non-integer) number of full-sized fins. The bottom of each group of fins is coplanar, while...

03/20/14 - 20140077297 - Thin film transistor and method of fabricating the same
Provided is a thin film transistor. The thin film transistor according to an embodiment of the present invention may include a source electrode and a drain electrode buried in a first flexible substrate, a semiconductor layer disposed on the first flexible substrate to be positioned between the source electrode and...

03/20/14 - 20140077298 - Thin film transistor array substrate and display device
A thin film transistor, an array substrate including the thin film transistor and a display device. The thin film transistor includes: a gate electrode (100), a gate insulating layer (200), an active layer (300) and a source/drain layer (400) that are successively stacked. The source/drain layer (400) comprises a source...

03/20/14 - 20140077299 - Strained semiconductor device and method of making the same
In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall...

03/13/14 - 20140070316 - Replacement source/drain for 3d cmos transistors
A method of forming a semiconductor structure may include forming at least one fin and forming, over a first portion of the at least one fin structure, a gate. Gate spacers may be formed on the sidewalls of the gate, whereby the forming of the spacers creates recessed regions adjacent...

03/13/14 - 20140070317 - Method for manufacturing a suspended membrane and dual-gate mos transistor
A method for manufacturing a suspended membrane in a single-crystal semiconductor substrate, including the steps of: forming in the substrate an insulating ring delimiting an active area, removing material from the active area, successively forming in the active area a first and a second layers, the second layer being a...

03/13/14 - 20140070318 - Reducing resistance in source and drain regions of finfets
A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections...

03/06/14 - 20140061792 - Field effect transistor devices with recessed gates
A field effect transistor device includes a bulk semiconductor substrate, a fin arranged on the bulk semiconductor substrate, the fin including a source region, a drain region, and a channel region, a first shallow trench isolation (STI) region arranged on a portion of the bulk semiconductor substrate adjacent to the...

03/06/14 - 20140061793 - Sublithographic width finfet employing solid phase epitaxy
A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different...

03/06/14 - 20140061794 - Finfet with self-aligned punchthrough stopper
A finFET with self-aligned punchthrough stopper and methods of manufacture are disclosed. The method includes forming spacers on sidewalls of a gate structure and fin structures of a finFET device. The method further includes forming a punchthrough stopper on exposed sidewalls of the fin structures, below the spacers. The method...

03/06/14 - 20140061795 - Thin film transistor including improved semiconductor interface
A transistor includes a substrate; a gate including a first electrically conductive layer stack on the substrate; and a first inorganic thin film dielectric layer on the substrate with the first inorganic thin film dielectric layer having a first pattern. A second inorganic thin film dielectric layer has a second...

03/06/14 - 20140061796 - Techniques for metal gate workfunction engineering to enable multiple threshold voltage finfet devices
Techniques are provided for gate work function engineering in FIN FET devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a FIN FET device is provided. The FIN FET device includes a SOI wafer having an oxide layer and...

03/06/14 - 20140061797 - Thin film transistor array substrate, method of manufacturing the same, and display device
Embodiments of the present invention disclose a thin film transistor array substrate, a method of manufacturing the same, and display device. A method of manufacturing a thin film transistor array substrate, comprises: forming a resin layer on a substrate formed with a thin film transistor array, patterning the resin layer...

03/06/14 - 20140061798 - Microelectronic device with isolation trenches extending under an active area
and in which, in said part of the thickness of the second semiconductor layer, at least one portion of dielectric material of the isolation trench is positioned under the active area by forming two side walls, two other side walls of the isolation trench being not arranged under the active...

03/06/14 - 20140061799 - Silicon-on-insulator transistor with self-aligned borderless source/drain contacts
A method is provided for fabricating an integrated circuit that includes multiple transistors. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work...

03/06/14 - 20140061800 - Electrical isolation structures for ultra-thin semiconductor-on-insulator devices
After formation of raised source and drain regions, a conformal dielectric material liner is deposited within recessed regions formed by removal of shallow trench isolation structures and underlying portions of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate. A dielectric material that is different from the material of the...

02/27/14 - 20140054698 - Electronic device including shallow trench isolation (sti) regions with bottom nitride liner and upper oxide liner and related methods
An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one STI region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall...

02/27/14 - 20140054699 - Electronic device including shallow trench isolation (sti) regions with bottom oxide liner and upper nitride liner and related methods
An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region...

02/27/14 - 20140054700 - Using fast anneal to form uniform ni(pt)si(ge) contacts on sige layer
Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX and at least one active area formed in the wafer; a gate stack...

02/27/14 - 20140054701 - Method of manufacturing transistor, transistor, array substrate and display device
Embodiments of the present invention provide a method for manufacturing a transistor, a transistor, an array substrate and a display device. The method comprises: forming a first source/drain metal layer on a substrate; forming an insulating layer above the first source/drain metal layer; forming a gate metal layer on the...

02/27/14 - 20140054702 - Tft, mask for manufacturing the tft, array substrate and display device
Embodiments of the invention relate to a TFT, a mask for manufacturing the TFT, an array substrate and a display device. A channel of the TFT is formed by using a single slit mask. The channel of the TFT has a bent portion and extension portions provided on both sides...

02/27/14 - 20140054703 - Array substrate and manufacturing method thereof
Embodiments of the invention provide an array substrate comprising a plurality of pixel units, each of the pixel units including a first display electrode, a second display electrode and an insulating portion, wherein, the insulating portion comprises a plurality of first via holes; the first display electrode is disposed at...

02/27/14 - 20140054704 - Semiconductor device including an active region and two layers having different stress characteristics
An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active...

02/20/14 - 20140048881 - Method of manufacturing a body-contacted soi finfet
A semiconductor structure including a body-contacted finFET device and methods form manufacturing the same. The method may include forming one or more semiconductor fins on a SOI substrate, forming a semiconductive body contact region connected to the bottom of the fin(s) in the buried insulator region, forming a sacrificial gate...

02/20/14 - 20140048882 - Techniques for gate workfunction engineering to reduce short channel effects in planar cmos devices
In one aspect, a CMOS device is provided. The CMOS device includes a SOI wafer having a SOI layer over a BOX; one or more active areas formed in the SOI layer in which one or more FET devices are formed, each of the FET devices having an interfacial oxide...

02/20/14 - 20140048883 - Thin-film transistor and method of manufacturing the same
The organic thin-film transistor according to the present invention includes: a gate electrode line on a substrate in a first region: a first signal line layer in a second region; a gate insulating film covering the gate electrode line and the first signal line layer; bank layers on the gate...

02/13/14 - 20140042539 - Self-aligned thin film transistor with doping barrier and method of manufacturing the same
Disclosed are a self-aligned thin film transistor controlling a diffusion length of a doping material using a doping barrier in a thin film transistor having a self-aligned structure and a method of manufacturing the same. The self-aligned thin film transistor with a doping barrier includes: an active layer formed on...

02/13/14 - 20140042540 - Array substrate, method for fabricating the same and display device
Disclosed are an array substrate, a method for fabricating the same and a display device. The array substrate comprises: a substrate, a gate electrode, a gate insulating layer as well as an active layer, and a source/drain metal layer formed on the substrate, the source/drain metal layer is configured for...

02/13/14 - 20140042541 - Creating anisotropically diffused junctions in field effect transistor devices
A method of forming a transistor device includes implanting a diffusion inhibiting species in a semiconductor-on-insulator substrate comprising a bulk substrate, a buried insulator layer, and a semiconductor-on-insulator layer, the semiconductor-on-insulator substrate having one or more gate structures formed thereon such that the diffusion inhibiting species is disposed in portions...

02/13/14 - 20140042542 - Mosfet with recessed channel film and abrupt junctions
MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and...

02/13/14 - 20140042543 - Mosfet with recessed channel film and abrupt junctions
MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and...

02/06/14 - 20140035037 - Embedded silicon germanium n-type filed effect transistor for reduced floating body effect
A semiconductor device includes a gate stack formed on an active region in a p-type field effect transistor (pFET) portion of a silicon-on-insulator (SOI) substrate. The SOI substrate includes a n-type field effect transistor (nFET) portion. A gate spacer is formed over the gate stack. A source region and a...

01/30/14 - 20140027851 - Body contacts for fet in soi sram array
Contact with a floating body of an FET in SOI may be formed in a portion of one of the two diffusions of the FET, wherein the portion of the diffusion (such as N−, for an NFET) which is “sacrificed” for making the contact is a portion of the diffusion...

01/30/14 - 20140027852 - Semiconductor device and method for manufacturing the same
A semiconductor device in which defects in characteristics due to electrostatic discharge is reduced and a method for manufacturing the semiconductor device are provided. The semiconductor device has at least one of these structures: (1) a structure in which a first and second insulating films are in direct contact with...

01/23/14 - 20140021547 - Integrated circuit including transistor structure on depleted silicon-on-insulator, related method and design structure
An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first semiconductor layer disposed on the substrate; a shallow trench isolation (STI) extending through the first semiconductor layer to within a portion of the substrate, the STI substantially separating a...

01/23/14 - 20140021548 - Semiconductor-on-insulator (soi) structure with selectively placed sub-insulator layer void(s) and method of forming the soi structure
Disclosed is a semiconductor-on-insulator (SOI) structure (e.g., an SOI field effect transistor (FET)) and method of forming the SOI structure so as to have sub-insulator layer void(s) selectively placed so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling...

01/16/14 - 20140015050 - Semiconductor device and manufacturing method thereof
In a semiconductor device, a logic MOSFET and a switch MOSFET are formed in a high-resistance substrate. The logic MOSFET includes an epitaxial layer formed on the high-resistance substrate and a well layer formed on the epitaxial layer. The switch MOSFET includes a LOCOS oxide film formed on the high-resistance...

01/16/14 - 20140015051 - Method of replacing silicon with metal in integrated circuit chip fabrication
A method of replacing semiconductor material with metal, Replacement Metal Gate Field Effect Transistors (RMG FETs) and Contacts (RMCs), and Integrated Circuit (IC) chips including the FETs and/or RMCs. A patterned semiconductor layer, e.g., silicon, is formed on a dielectric layer, e.g., a layered gate dielectric. A field dielectric layer...

01/09/14 - 20140008726 - Semiconductor structure and method of fabricating the same
A semiconductor structure fabricating method includes the following steps. Firstly, a silicon substrate is provided. The silicon substrate has a first surface and a second surface. In addition, a first semiconductor structure is formed on the first surface of the silicon substrate. Then, the second surface of the silicon substrate...

01/09/14 - 20140008727 - Method for doping semiconductor structures and the semiconductor device thereof
A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor...

01/02/14 - 20140001554 - Semiconductor device with epitaxial source/drain facetting provided at the gate edge
A method of forming a semiconductor structure includes providing an active layer and forming adjacent gate structures on the active layer. The gate structures each have sidewalls such that first spacers are formed on the sidewalls. A raised region is epitaxially grown on the active layer between the adjacent gate...

01/02/14 - 20140001555 - Undercut insulating regions for silicon-on-insulator device
A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation...