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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Single Crystal Semiconductor Layer On Insulating Substrate (soi) Single Crystal Semiconductor Layer On Insulating Substrate (soi)Single Crystal Semiconductor Layer On Insulating Substrate (soi) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/24/08 - 20080017924 - Semiconductor device and method of manufacturing the same A semiconductor device having an SOI structure including a semiconductor substrate, a buried insulating layer and an SOI layer, including first and second semiconductor regions of a predetermined conductivity type provided in an element formation region of said SOI layer, and a partial insulating film provided in an upper layer ... 01/17/08 - 20080012076 - Display device, method for manufacturing thereof, and television device The invention provides a display device and a method for manufacturing thereof by increasing a material efficiently as well as simplifying steps. Also, the invention provides a technique for forming a pattern such as a wiring, that is used for forming a display device, to have a predetermined shape with ... 01/17/08 - 20080012074 - Low temperature sol-gel silicates as dielectrics or planarization layers for thin film transistors Traditionally, sol-gel silicates have been reported as being high temperature processable at 400 C to give reasonably dense films that showed good leakage current densities (<5×10−8 A/cm2). Recently we have discovered that we are able to prepare films from particular combinations of sol-gel silicate precursors that cure at 135° C. ... 01/10/08 - 20080006877 - Method of forming a solution processed device Embodiments of methods, apparatuses, devices, and/or systems for forming a solution processed device are described. ... 01/03/08 - 20080001225 - Microelectronic structure by selective deposition A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the ... 12/27/07 - 20070296032 - Artificial dielectrics using nanostructures Artificial dielectrics using nanostructures, such as nanowires, are disclosed. In embodiments, artificial dielectrics using other nanostructures, such as nanorods, nanotubes or nanoribbons and the like are disclosed. The artificial dielectric includes a dielectric material with a plurality of nanowires (or other nanostructures) embedded within the dielectric material. Very high dielectric ... 12/06/07 - 20070278578 - Memory cell array, method of producing the same, and semiconductor memory device using the same A memory cell array includes isolated semiconductor regions formed on a supporting insulating substrate, memory cells formed in the respective semiconductor regions, and insulating regions formed so as to insulate the memory cells. Each memory cell formed in a semiconductor region includes a source region, a drain region, a front ... 12/06/07 - 20070278577 - Semiconductor device and manufacturing method of the same To reduce the adverse affect that characteristics of end portions of a channel forming region of a semiconductor film have on characteristics of a transistor. A gate electrode is formed over a channel forming region of a semiconductor film over a substrate, with a gate insulating film interposed therebetween. The ... 12/06/07 - 20070278575 - Transistor and fabrication process Process for fabricating a transistor, in which an electron-sensitive resist layer lying between at least two semiconductor fingers is formed and said resist lying between at least two wires is converted into a dielectric. For example, in one embodiment of the present disclosure an integrated circuit includes a transistor having ... 11/22/07 - 20070267699 - Transistor including a deposited channel region having a doped portion A transistor having a gate electrode, a source electrode, a drain electrode, a dielectric material and a channel region disposed between the source electrode and drain electrode. The channel region includes a portion doped with an impurity to change the fixed charge density within the portion relative to a remainder ... 11/22/07 - 20070267698 - Dual wired integrated circuit chips A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side ... 11/22/07 - 20070267696 - Mobile transforming plug A mobile transforming plug includes an insulating main body, a shell cover, a linking element and a linker. At the front side of the insulating main body, a connecting part is formed. A carrying part is formed at the rear side of the insulating main body. There is a connection ... 11/15/07 - 20070262379 - Metal structure of glass substrate and formation thereof Aluminum gate electrode parasitic resistance and capacitance delay suffers performance, and even makes the signal loss to high-resolution and small-size requests for thin film transistor liquid crystal display. An important technology employed in manufacturing thin film transistor is to convert surface of glass substrate into a silicon nitride layer, and ... 11/15/07 - 20070262378 - Technique for stable processing of thin/fragile substrates A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second ... 11/08/07 - 20070257313 - Semiconductor memory device including an soi substrate A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain ... 11/08/07 - 20070257312 - Semiconductor-on-insulator (soi) substrates and semiconductor devices using void spaces An SOI substrate is fabricated by providing a substrate having a sacrificial layer thereon, an active semiconductor layer on the sacrificial layer remote from the substrate and a supporting layer that extends along at least two sides of the active semiconductor layer and the sacrificial layer and onto the substrate, ... 11/08/07 - 20070257311 - Semiconductor device and method for manufacturing the same The present invention provides a method for manufacturing massively and efficiently a minute device which can receive or send data in contact, preferably, out of contact by forming an integrated circuit which is formed by a thin film over a large glass substrate and by peeling the integrated circuit from ... 11/08/07 - 20070257310 - Body-tied mosfet device with strained active area A body-tied MOSFET device and method of fabrication are presented. In the method of fabrication, oxygen diffuses and reacts down a first axis of a pFET or nFET. This results in a partial oxidation of a buried-oxide/silicon island interface. The partial oxidation produces a thickness variation in the silicon island ... 11/01/07 - 20070252210 - Semiconductor element, semiconductor device and methods for manufacturing thereof The present invention provides a method of manufacturing a semiconductor element having a miniaturized structure and a semiconductor device in which the semiconductor element having a miniaturized structure is integrated highly, by overcoming reduction of the yield caused by alignment accuracy, accuracy of a processing technique by reduced projection exposure, ... 11/01/07 - 20070252206 - Semiconductor thin film and method of manufacturing the same and semiconductor device and method of manufacturing the same A thin film semiconductor transistor structure has a substrate with a dielectric surface, and an active layer made of a semiconductor thin film exhibiting a crystallinity as equivalent to the single-crystalline. To fabricate the transistor, the semiconductor thin film is formed on the substrate, which film includes a mixture of ... 10/25/07 - 20070246774 - Semiconductor device with substantial driving current and decreased junction leakage current The semiconductor device includes an active region, a stepped recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The stepped recess channel region is formed in the active region. ... 10/18/07 - 20070241399 - Semiconductor device and method of fabricating the same In a semiconductor device including a multi-gate MIS transistor having a channel on a plurality of surfaces, a gate electrode is formed on a gate insulating film on side surfaces of an island-like semiconductor layer formed along a given direction on an insulating film, and source/drain electrodes are formed in ... 10/18/07 - 20070241398 - Error detection and correction in semiconductor structures A semiconductor structure and a method for operating the same. The semiconductor structure includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is on top of and bonded to the second semiconductor chip. The first and second semiconductor chips include a first and a second ... 10/11/07 - 20070235804 - Soi lateral semiconductor device and method of manufacturing the same The SOI lateral semiconductor device includes a semiconductor region of a first conductivity type, a buried oxide film layer in the semiconductor region, a thin active layer on the buried oxide film layer, an anode region in the thin active layer, and a drain layer contacting the buried oxide film ... 10/04/07 - 20070228469 - Thin-film transistor formed on insulating substrate There is provided a thin-film transistor that is formed on an insulating substrate, is capable of a high-speed operation, has small non-uniformity among devices, is hardly susceptible to device destruction due to high voltage, and is free from the effect of a parasitic transistor that forms at an edge part ... 10/04/07 - 20070228466 - Pixel structure, thin film transistor array substrate and liquid crystal display panel A pixel structure, suitable being driven by a scan line and a data line on a substrate, is provided. The pixel structure includes a thin film transistor (TFT) and a pixel electrode. Wherein, the TFT includes a gate, a first and a second dielectric layer, a semiconductor layer, a source, ... 10/04/07 - 20070228465 - Improved soi substrate and soi device, and method for forming the same An improved semiconductor-on-insulator (SOI) substrate is provided, which has a substantially planar upper surface and comprises at least first and second patterned buried insulator layers. Specifically, the first patterned buried insulator layer has a first thickness and is located in the SOI substrate at a first depth from the substantially ... 09/27/07 - 20070221991 - Semiconductor device with increased channel area and decreased leakage current The semiconductor device includes an active region, a recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess channel region is formed in the active region. The vertical ... 09/27/07 - 20070221990 - Grounding front-end-of-line structures on a soi substrate Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including ... 09/20/07 - 20070215945 - Light control device and display Provided is a light control device including: a thin film transistor; and a light control element including an electrode electrically connected to the thin film transistor, in which a semiconductor region of the thin film transistor and an pixel electrode are composed of the same semiconductor layer, and the same ... 09/20/07 - 20070215941 - Semiconductor-on-insulator substrate comprising a buried diamond-like carbon layer and method for making same The substrate successively comprises a base, a diamond-like carbon layer, a dielectric layer and a semi-conducting material layers which is designed to constitute microelectronic elements. A nucleation layer is preferably disposed between the base and the diamond-like carbon layer. The dielectric material is chosen such that the upper level of ... 09/13/07 - 20070210382 - Semiconductor device and method of manufacturing the same Provided is a semiconductor device formed to an SOI substrate including a MOS transistor in which a parasitic MOS transistor is suppressed. The semiconductor device formed on the SOI substrate by employing a LOCOS process is structured such that a part of a a polysilicon layer to becomes a gate ... 09/13/07 - 20070210381 - Electronic device and a process for forming the electronic device An electronic device can have an insulating layer lying between a first semiconductor layer and a base layer. A second semiconductor layer, having a different composition and stress as compared to the first semiconductor layer, can overlie at least a portion of the first semiconductor layer. In one embodiment, a ... 09/13/07 - 20070210380 - Body connection structure for soi mos transistor A body connection structure for a SOI MOS transistor is described, including a first and a second control transistors. The first control transistor includes a gate electrically connecting with the gate of the SOI MOS transistor, a first S/D region electrically connecting with the first S/D region of the SOI ... 09/06/07 - 20070205463 - Semiconductor-on-insulator silicon wafer A method of fabricating a semiconductor-on-insulator semiconductor wafer is described that includes providing first and second semiconductor substrates. A first insulating layer is formed on the first substrate with a first predetermined stress and a second insulating layer is formed on the second substrate with a second predetermined stress different ... 08/30/07 - 20070200177 - Semiconductor laser device and semiconductor laser device manufacturing method A semiconductor laser device comprising: an active layer, a semiconductor layer formed on the active layer and having a wurtzite structure, wherein a principal surface of the active layer is substantially perpendicular to a (0001) surface of the semiconductor layer, a current path portion in the semiconductor layer extends along ... 08/30/07 - 20070200175 - Functional device and method of manufacturing it A functional device which is composed of a nanometer-sized functional structure, which can reduce connection resistance in connecting the functional structure to an external electrode, and which includes a wiring section capable of minimizing constraints given to structural designs of various functional structures, and a method of manufacturing it are ... 08/30/07 - 20070200174 - Soi substrate, mask blank for charged particle beam exposure, and mask for charged particle beam exposure The invention provides an SOI substrate 10 comprising on one major surface of a silicon single crystal 13 a silicon thin-film layer 11 via a buried silicon oxide film 12, characterized in that a substrate warp preventive layer 14 is provided on another major surface of the silicon single crystal ... 08/30/07 - 20070200173 - Embedded substrate interconnect for underside contact to source and drain regions A semiconductor topography (10) is provided which includes a semiconductor-on-insulator (SOI) substrate having a conductive line (16) arranged within an insulating layer (22) of the SOI substrate. A method for forming an SOI substrate with such a configuration includes forming a first conductive line (16) within an insulating layer (22) ... 08/30/07 - 20070200172 - Thin film power mos transistor, apparatus, and method A thin film power transistor includes a plurality of first doped regions over a substrate and a second doped region forming a body. At least a portion of the body is disposed between the plurality of first doped regions. The thin film power transistor also includes a gate over the ... 08/23/07 - 20070194379 - Amorphous oxide and thin film transistor The present invention relates to an amorphous oxide and a thin film transistor using the amorphous oxide. In particular, the present invention provides an amorphous oxide having an electron carrier concentration less than 1018/cm3, and a thin film transistor using such an amorphous oxide. In a thin film transistor having ... 08/23/07 - 20070194378 - Eeprom memory cell for high temperatures An electrically erasable programmable read-only memory (EEPROM) memory cell is produced using a silicon on insulator (SOI) technology, which is suitable for use at high temperatures. An EEPROM cell is formed from a memory transistor comprising a floating gate and a high-voltage select transistor. The select transistor comprises a freely ... 08/16/07 - 20070187760 - Thin film transistor including low resistance conductive thin films and manufacturing method thereof A thin film transistor includes a substrate, and a pair of source/drain electrodes (i.e., a source electrode and a drain electrode) formed on the substrate and defining a gap therebetween. A pair of low resistance conductive thin films are provided such that each coats at least a part of one ... 08/16/07 - 20070187758 - Sb-mosfet (schottky barrier metal-oxide-semiconductor field effect transistor) with low barrier height and fabricating method thereof Provided is a high-performance n-type Schottky barrier tunneling transistor with low Schottky barrier for electrons due to a Schottky junction formed on a Si (111) surface created through anisotropic etching. The Schottky barrier tunneling transistor includes: a silicon on insulator (SOI) substrate; a source and a drain formed on the ... 08/09/07 - 20070181946 - Method and apparatus for forming a semiconductor-on-insulator (soi) body-contacted device A method for making a semiconductor device includes patterning a semiconductor layer, overlying an insulator layer, to create a first active region and a second active region, wherein the first active region is of a different height from the second active region, and wherein at least a portion of the ... 08/09/07 - 20070181945 - Semiconductor device and manufacturing method thereof An island-like interlayer insulating film is formed selectively in a region where a source interconnection and a gate interconnection intersect. For example, by use of ink jet method, a solution containing an insulating material is dropped on a region where the gate interconnection and the source interconnection intersect or a ... 08/02/07 - 20070176237 - Semiconductor device and manufacturing method thereof A semiconductor device comprises a support layer made of semiconductor, a diffusion layer formed by implanting impurities in a surface layer of the support layer, a buried insulating layer provided on the diffusion layer, an island-like active layer provided on the buried insulating layer, a channel region formed in the ... 08/02/07 - 20070176234 - Semiconductor device The present invention is to provide a semiconductor device that achieves high mechanical strength without reducing the circuit scale and that can prevent the data from being forged and altered illegally while suppressing the cost. The present invention discloses a semiconductor device typified by an ID chip that is formed ... 07/26/07 - 20070170507 - Structure and method for manufacturing planar strained si/sige substrate with multiple orientations and different stress levels The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; forming a first concentration of lattice modifying material atop the first orientation ... 07/26/07 - 20070170505 - Semiconductor device and manufacturing method thereof To provide a wireless identification semiconductor device provided with a display function, which is capable of effectively utilizing electric power supplied by an electromagnetic wave. The following are included: an antenna; a power source generating circuit electrically connected to the antenna; an IC chip circuit and a display element electrically ... 07/26/07 - 20070170502 - Semiconductor device and method for manufacturing the same The present invention provides a high-quality semiconductor device in which deterioration in transistor characteristics and an increase in interface layer due to a gate insulating film are suppressed, and a method for manufacturing the same. In the present invention, an interface layer, a diffusion suppressing layer and a high dielectric ... 07/19/07 - 20070164361 - Micro-mechanically strained semiconductor film A semiconductor structure embodiment comprises a semiconductor membrane with local strained areas. The membrane with local strained areas is formed by a process including performing a local oxidation of silicon (LOCOS) process in a substrate and removing resulting oxide to form a recess in the substrate, and bonding a semiconductor ... 07/19/07 - 20070164360 - Semiconductor device and method of fabricating the same A semiconductor device has a supporting substrate applied with a predetermined potential, an insulating layer formed on the supporting substrate, a semiconductor layer formed on the insulating layer, a FDSOI transistor formed on the semiconductor layer and including a source region, a drain region, and a channel region, the channel ... 07/19/07 - 20070164359 - Area-efficient gated diode structure and method of forming same An area-efficient gated diode includes a semiconductor layer of a first conductivity type, an active region of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, and at least one trench electrode extending substantially vertically through the active region and at least ... 07/19/07 - 20070164358 - Structure and method to form semiconductor-on-pores (sop) for high device performance and low manufacturing cost A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein ... 07/19/07 - 20070164357 - Structure and method for mosfet gate electrode landing pad A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is ... 07/19/07 - 20070164356 - Strained semiconductor-on-insulator (ssoi) by a simox method A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that ... 07/12/07 - 20070158745 - Semiconductor device and manufacturing method thereof When a metal layer 11 is provided over a substrate, an oxide layer 12 is provided in contact with the metal layer 11, a layer to be peeled 13 is formed, and the metal layer 11 is irradiated with a laser beam to perform oxidization and form a metal oxide ... 07/12/07 - 20070158743 - Thin silicon single diffusion field effect transistor for enhanced drive performance with stress film liners The present invention provides a semiconducting device structure including a thin SOI region, wherein the SOI device is formed with an optional single thin diffusion, i.e., offset, spacer and a single diffusion implant. The device silicon thickness is thin enough to permit the diffusion implants to abut the buried insulator ... 07/12/07 - 20070158742 - Mos transistor and manufacturing method thereof There are provided a MOS transistor and a manufacturing method thereof. The MOS transistor includes a substrate on which an insulating layer is formed, a gate embedded in the insulating layer, wherein the top surface of the gate is exposed, a gate oxide layer formed on the insulating layer and ... 06/28/07 - 20070145482 - Thin film transistor and manufacturing method thereof, and liquid crystal display device having thin film transistor and manufacturing method thereof A liquid crystal display device includes a substrate, a gate line and a data line intersected with each other to define a pixel region on the substrate, a thin film transistor having a nanowire channel layer in an intersection region of the gate line and the data line, and a ... 06/28/07 - 20070145481 - Silicon-on-insulator chip having multiple crystal orientations A silicon-on-insulator device having multiple crystal orientations is disclosed. In one embodiment, the silicon-on-insulator device includes a substrate layer, an insulating layer disposed on the substrate layer, a first silicon layer, and a strained silicon layer. The first silicon layer has a first crystal orientation and is disposed on a ... 06/28/07 - 20070145480 - Thin film transistor, electrode thereof and method of fabricating the same A method of forming an electrode of a semiconductor device is provided. A material layer comprising an organo-metallic compound is first formed on a substrate. Thereafter, an electrode is formed by irradiating the material layer through utilizing the heating property of laser. Next, the material layer is patterned by utilizing ... 06/21/07 - 20070138557 - Semiconductor device A transistor region is a region where a plurality of MOS transistors, including an MOS transistor, are formed, and a dummy region is a region lying under a spiral inductor. In the dummy region, a plurality of dummy active layers are disposed in the main surface of an SOI substrate ... 06/21/07 - 20070138556 - Self-aligned planar double-gate process by self-aligned oxidation A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the ... 06/21/07 - 20070138555 - One transistor soi non-volatile random access memory cell Various semiconductor structure embodiments include a substrate, a buried insulator over at least a portion of the substrate, a body region over the buried insulator, first and second source/drain regions to provide a channel region in the body region, a gate insulator over the channel region, and a gate over ... 06/21/07 - 20070138554 - Full depletion soi-mos transistor A method of manufacturing a full depletion SOI-MOS transistor including a substrate, a buried oxide layer, a thin silicon layer, an isolation layer, a gate insulation layer, a gate electrode and a polysilicon layer. The buried oxide layer is formed on a main surface of the substrate. The thin silicon ... 06/21/07 - 20070138553 - Method of manufacturing semiconductor substrate and semiconductor device A method of manufacturing a semiconductor substrate comprises: forming a first mono crystalline semiconductor layer in a portion having a mono crystalline area exposed on an active surface side of a mono crystalline semiconductor base material, the first mono crystalline semiconductor layer being made of a mono crystalline material having ... 06/14/07 - 20070132026 - Method for manufacturing semiconductor substrate, method for manufacturing semiconductor device, and semiconductor device A method for manufacturing a semiconductor substrate includes forming a first semiconductor layer on a semiconductor base; forming a second semiconductor layer having a lower etching selection ratio than the first semiconductor layer on the first semiconductor layer; removing a part of the second semiconductor layer and a part of ... 06/14/07 - 20070132025 - Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device A method for manufacturing a semiconductor substrate comprises: forming a silicon on insulator (SOI) area and an element isolation film on a semiconductor base; forming a first semiconductor layer on the semiconductor base in the SOI structure area; forming a second semiconductor layer having an etching selection ratio smaller than ... 06/14/07 - 20070132024 - Thin film transistor array panel and method of manufacturing the same The present invention provides a thin film transistor array panel which includes a substrate, gate lines formed on the substrate, polycrystalline semiconductors formed on the gate lines, data lines formed on the polycrystalline semiconductors and including first electrodes, second electrodes formed on the polycrystalline semiconductors and facing the first electrodes, ... 06/14/07 - 20070132023 - Organic thin film transistor, method of manufacturing the same, and organic light emitting display device having the same Provided is an organic thin film transistor that can prevents damage to source and drain electrodes when patterning an organic semiconductor layer, and a method of manufacturing an organic light emitting display device having the organic thin film transistor. The organic thin film transistor includes a source electrode and a ... 06/14/07 - 20070132022 - Semiconductor device and method of manufacturing the same First and second preliminary epitaxial layers are grown from single-crystalline seeds in openings in an insulation layer until the first and second epitaxial layers are connected to each other. While the first and second preliminary epitaxial layers are being grown, a connection structure of a material having an amorphous state ... 06/07/07 - 20070126060 - Sram cell with improved layout designs A 6T SRAM cell includes a first inverter having a first pull-up transistor and a first pull-down transistor serially coupled between a supply source and a complementary supply source, and a second inverter cross-coupled with the first inverter having a second pull-up transistor and a second pull-down transistor serially coupled ... 05/31/07 - 20070120189 - Crystalline semiconductor thin film, method of fabricating the same, semiconductor device, and method of fabricating the same There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. An amorphous semiconductor thin film is irradiated with ultraviolet light or infrared light, to obtain a crystalline semiconductor thin film (102). Then, the crystalline semiconductor thin film (102) is ... 05/31/07 - 20070120188 - Light-emitting device and electronic apparatus A light-emitting device includes a drive transistor that controls a current to be supplied to a light-emitting element from a power supply line, an electrical continuity portion that electrically connects the drive transistor with the light-emitting element, an initializing transistor that is turned ON to diode-connect the drive transistor, and ... 05/31/07 - 20070120187 - Lateral soi semiconductor device This invention is generally concerned with semiconductor-on-insulator devices, particularly for high voltage applications. A lateral semiconductor-on-insulator device is described, comprising: a semiconductor substrate; an insulating layer on said semiconductor substrate; and a lateral semiconductor device on said insulator; said lateral semiconductor device having: a first region of a first conductivity ... 05/24/07 - 20070114609 - Semiconductor substrate and method of manufacturing the same A method of manufacturing a semiconductor substrate can effectively prevent a chipping phenomenon and the production of debris from occurring in part of the insulation layer and the semiconductor by removing a outer peripheral portion of the semiconductor substrate so as to make the outer peripheral extremity of the insulation ... 05/24/07 - 20070114608 - Lateral thin-film soi device having a field plate with isolated metallic regions In a lateral thin-film Silicon-On-Insulator (SOI) device, a field plate is provided to extend substantially over a lateral drift region to protect the device from package and surface charge effects. In particular, the field plate comprises a layer of plural metallic regions which are isolated laterally from one another by ... 05/17/07 - 20070108523 - Semiconductor device and fabrication method for the same In a semiconductor device including a monocrystalline thin film transistor 16a that has been formed on a monocrystalline Si wafer 100 and then is transferred to a insulating substrate 2, LOCOS oxidization is performed with respect to the element-isolation region of the monocrystalline Si wafer 100 so as to create ... 05/17/07 - 20070108522 - Soi substrate and method of manufacturing the same The SOI substrate includes a supporting substrate, an insulating layer (first insulating layer), another insulating layer (second insulating layer), and a silicon layer (silicon active layer). On a surface of the supporting substrate, which is the surface on the side of the silicon layer, the first insulating layer is provided. ... 05/17/07 - 20070108521 - Flexible semiconductor device and identification label Provided is a flexible device (100) having an integrated circuit (5) and an antenna (6) which is incorporated or directly coupled to the interconnect structure of the integrated circuit (5). The interconnect structure extends outside of the active area. An electrically insulating or dielectric layer (4) is present as support ... 05/10/07 - 20070102762 - Semiconductor device, and semiconductor package and circuit device using the same A first semiconductor element and a second semiconductor element each have an electrode forming surface with an electrode pad thereon. The first semiconductor element and the second semiconductor element are stacked to expose each electrode pad and bonded while facing the electrode forming surfaces each other. The electrode pads of ... 05/10/07 - 20070102761 - Semiconductor device and method of fabricating the same A semiconductor device includes a semiconductor substrate, a channel region formed above the semiconductor substrate, a first gate electrode formed above the channel region via a first gate insulating film, a second gate electrode formed below the channel region via a second gate insulating film to face the first gate ... 05/10/07 - 20070102760 - Inhibiting radiation hardness of integrated circuits A system and method for inhibiting radiation hardness of Silicon on Insulator (SOI) integrated circuits is described. An electrical connection is used to connect a substrate below a buried oxide layer to the topside above the buried oxide layer. A bias is then applied to the substrate. The bias may ... 05/03/07 - 20070096211 - Method of evaluating semiconductor device The present invention provides a semiconductor device having an active region bent at right angles, wherein an interval between patterns for the active region and a gate is set larger than an arc radius of a curved portion (portion where a line is brought to arcuate form) formed inside the ... 05/03/07 - 20070096210 - Semiconductor device and method of forming the same An insulated gate semiconductor device comprising an insulator substrate having provided thereon a source and a drain region; a channel region being incorporated between said source and said drain regions, said channel region comprising a polycrystalline, a single crystal, or a semi-amorphous semiconductor material; and a region provided under said ... 05/03/07 - 20070096209 - Image displaying device and method for manufacturing same A technique for improving the manufacturing yield of an image displaying device is disclosed. A fabrication method of the image displaying device includes the steps of forming on an insulative substrate a plurality of island-like semiconductor layers, forming a gate insulating film on the island-like semiconductor layers, defining more than ... 05/03/07 - 20070096208 - Manufacturing method for flat panel display A dummy glass substrate supporting a plastic insulation substrate for a display apparatus wherein the dummy glass substrate includes a stress relaxation portion having grooves that reduce thermal deformation of the plastic insulation substrate. ... 05/03/07 - 20070096207 - Semiconductor device and method for manufacturing the same A semiconductor device includes at least one thin film transistor including a semiconductor layer that has a crystalline region including a channel region, a source region and a drain region, a gate insulating film disposed at least on the channel region, the source region and the drain region of the ... 05/03/07 - 20070096206 - Gate electrode stress control for finfet performance enhancement A finFET and its method for fabrication include a gate electrode formed over a channel region of a semiconductor fin. The semiconductor fin has a crystallographic orientation and an axially specific piezoresistance coefficient. The gate electrode is formed with an intrinsic stress determined to influence, and preferably optimize, charge carrier ... 04/26/07 - 20070090458 - Semiconductor device having first and second separation trenches A semiconductor device includes: a SOI substrate having a SOI layer, a buried oxide layer and a support substrate; multiple first separation trenches on the SOI layer; multiple MOS transistors, each of which is surrounded with one first separation trench; a second separation trench on the SOI layer including n-ply ... 04/26/07 - 20070090457 - Thin film transistor substrate for display unit A thin film transistor (TFT) substrate comprises: a plastic insulation substrate; a first silicon nitride layer with a first refractive index, formed one surface of the plastic insulation substrate; and a TFT comprising a second silicon nitride layer formed with a second refractive index smaller than the first refractive index ... 04/26/07 - 20070090456 - Soi device and method for fabricating the same A semiconductor-on-insulator (SOI) device is described, including a substrate, a first insulating layer and a second insulating layer on the substrate, a semiconductor layer covering the first and the second insulating layers, a gate dielectric layer and a gate on the semiconductor layer, and two doped regions as source/drain regions ... 04/19/07 - 20070085138 - Semiconductor device and manufacturing method thereof The invention relates to a semiconductor device including a plurality of thin film transistors provided on a base member having a curved surface. The surface may be bent in either a convex shape or a concave shape. All channel length directions of the plurality of thin film transistors may also ... 04/05/07 - 20070075369 - Thin film transistor and method of fabricating the same A thin film transistor and a method of fabricating the same capable of reducing stress of a substrate caused by a metal layer of the drain and source electrodes, the thin film transistor including a substrate; a semiconductor layer disposed on the substrate and including source, drain and channel regions; ... 04/05/07 - 20070075368 - Cmos inverter cell A CMOS inverter cell having a small horizontal length which is reduced by substituting metal lines for supplying data signals to gates with a connection pattern which is mounted in one end of a supply voltage area of the CMOS inverter cell and is made of the same material as ... 04/05/07 - 20070075367 - Soi semiconductor component with increased dielectric strength An SOI semi-conductor element has field electrodes and/or field zones which are arranged between a first and a second semi-conductor zone. Electric coupling is possible between the field electrodes and the field zones. ... 04/05/07 - 20070075366 - Semiconductor memory device and method for manufacturing the same According to the present invention, there is provided a semiconductor memory device having: a semiconductor layer of a first conductivity type formed above a semiconductor substrate via an embedded insulation film, a gate electrode formed above the semiconductor layer via a gate insulation film, a floating body region of a ... 04/05/07 - 20070075365 - Thin-film transistor and method of making the same A thin-film transistor includes a substrate having a substantially outwardly protruding support structure formed thereon such that a portion adjacent to the structure is exposed. The support structure has opposed sidewalls sloped at an angle relative to the substrate surface. A stack is established over the portion and over a ... 03/29/07 - 20070069292 - Semiconductor device having ldmos transistor and method for manufacturing the same A semiconductor device includes: a semiconductor substrate having a first semiconductor layer, an insulation layer and a second semiconductor layer, which are stacked in this order; a LDMOS transistor disposed on the first semiconductor layer; and a region having a dielectric constant, which is lower than that of the first ... 03/29/07 - 20070069291 - Method and apparatus improving gate oxide reliability by controlling accumulated charge A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in ... 03/22/07 - 20070063283 - Thin film transistor, liquid crystal display using thin film transistor, and method of manufacturing thin film transistor A semiconductor film, which is located over a gate electrode for forming a channel region between a source electrode and a drain electrode, has a width greater than a width of the source electrode and a width of the drain electrode located over the gate electrode. Irregularities are formed in ... 03/22/07 - 20070063282 - Soi-like structures in a bulk semiconductor substrate Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the ... 03/22/07 - 20070063281 - Semiconductor device and manufacturing method thereof, soi substrate and display device using the same, and manufacturing method of the soi substrate A polycrystalline Si thin film and a single crystal Si thin film are formed on an SiO2 film deposited on an insulating substrate. A polycrystalline Si layer is grown by thermally crystallizing an amorphous Si thin film so as to form the polycrystalline Si thin film. A single crystal Si ... 03/22/07 - 20070063280 - Thin film transistor array substrate A thin film transistor array substrate having a display area and a non-display area is provided. Pixel units, scan lines and data lines are disposed within the display area, and the scan line and data line are electrically connected to the corresponding pixel units. The non-display region has first chip ... 03/22/07 - 20070063279 - Insulation layer for silicon-on-insulator wafer A method of forming a silicon-on-insulator wafer begins by providing a silicon wafer having a first surface. An ion implantation process is then used to implant oxygen within the silicon wafer to form an oxygen layer that is buried within the silicon wafer, thereby forming a silicon device layer that ... 03/22/07 - 20070063278 - Highly manufacturable sram cells in substrates with hybrid crystal orientation The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially ... 03/22/07 - 20070063277 - Multiple low and high k gate oxides on single gate for lower miller capacitance and improved drive current The present invention provides a semiconductor structure having at least one CMOS device in which the Miller capacitances, i.e., overlap capacitances, are reduced and the drive current is improved. The inventive structure includes a semiconductor substrate having at least one overlaying gate conductor, each of the at least one overlaying ... 03/22/07 - 20070063276 - Dense chevron finfet and method of manufacturing same A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal ... 03/15/07 - 20070057326 - Semiconductor device and manufacturing method of the same A semiconductor device comprises: a channel region of a transistor formed in a predetermined region of silicon layer formed on insulation film; a gate electrode formed on the channel region via gate insulation film; and source/drain regions formed in the silicon layer thicker than said channel region located out of ... 03/15/07 - 20070057325 - Semiconductor finfet structures with encapsulated gate electrodes and methods for forming such semiconductor finfet structures Semiconductor structures in which the gate electrode of a FinFET is masked from the process introducing dopant into the fin body of the FinFET to form source/drain regions and methods of fabricating such semiconductor structures. The gate doping, and hence the work function of the gate electrode, is advantageously isolated ... 03/15/07 - 20070057324 - Strained semiconductor device and method of making the same In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall ... 03/15/07 - 20070057323 - Silicon-on-insulator (soi) read only memory (rom) array and method of making a soi rom A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper surface ... 03/08/07 - 20070052026 - Semiconductor device and method of manufacturing the same A semiconductor device is disclosed, which comprises a semiconductor substrate, source/drain regions formed in the semiconductor substrate, a gate insulating film formed on a channel region between the source/drain regions, a gate electrode formed on the gate insulating film, and a sidewall insulating film formed on a sidewall surface of ... 03/08/07 - 20070052025 - Oxide semiconductor thin film transistor and method of manufacturing the same Provided is a thin film transistor comprising a channel layer comprised of an oxide semiconductor containing In, M, Zn, and O, M including at least one selected from the group consisting of Ga, Al, and Fe. The channel layer is covered with a protective film. ... 03/08/07 - 20070052024 - Thin film transistor having a nano semiconductor sheet and method of manufacturing the same Provided are a nano semiconductor sheet, a thin film transistor (TFT) using the nano semiconductor sheet, and a flat panel display using nano semiconductor sheet. The nano semiconductor sheet has excellent characteristics, can be manufactured at room temperature, and has good flexibility. The nano semiconductor sheet includes: a first film ... 03/08/07 - 20070052023 - Thin film transistor and method of fabricating the same A thin film transistor and a method of fabricating the same are disclosed. The method includes: sequentially depositing an amorphous silicon layer, a capping layer, and a metal catalyst layer; annealing the entire layer to crystallize the amorphous silicon layer into a polysilicon layer; removing the capping layer; and, when ... 03/08/07 - 20070052022 - Thin film transistor, method of fabricating the same, and a display device including the thin film transistor A thin film transistor (TFT), a method of fabricating the same, and a display device including the TFT, are provided. In the TFT, a channel region is connected to a gate electrode so that the influence of a substrate bias is reduced or eliminated. Thus, the threshold voltage of the ... 03/08/07 - 20070052021 - Transistor, and display device, electronic device, and semiconductor device using the same It is an object of an invention disclosed in the present specification to provide a transistor having low contact resistance. In the transistor, a semiconductor film including an impurity element imparting P-type or N-type conductivity, an insulating film formed thereover, and an electrode or a wiring that is electrically connected ... 03/08/07 - 20070052020 - Thin film transistor and method of manufacturing the same A Thin Film Transistor comprises a gate electrode formed on a substrate; a gate insulation layer covering the gate electrode; an amorphous silicon (a-Si) region disposed on the gate insulation layer and above the gate electrode; a doped a-Si region formed on the a-Si region; the source and drain metal ... 03/08/07 - 20070052019 - Transistor device wiwth metallic electrodes and a method for use in forming such a device A transistor device having a metallic source electrode, a metallic drain electrode, a metallic gate electrode and a channel in a deposited semiconductor material, the transistor device comprising: a first layer comprising the metallic gate electrode, a first metal portion of the metallic source electrode and a first metal portion ... 03/01/07 - 20070045740 - Thin film transistor, method of fabricating the same, and a display device including the thin film transistor A thin film transistor (TFT), a method of fabricating the same, and a display device including the TFT, are provided. The method includes forming an edge region that is doped with impurities of a conductivity type opposite to a conductivity type of impurities doped into source and drain regions. The ... 03/01/07 - 20070045739 - Method for manufacturing semiconductor substrate and method for manufacturing semiconductor apparatus and photomask A method for manufacturing a semiconductor substrate, includes: forming a first semiconductor layer on a semiconductor base material; forming a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having an etching selectivity larger than that of the first semiconductor layer; forming, at the second semiconductor layer ... 03/01/07 - 20070045738 - Method for the manufacture of a strained silicon-on-insulator structure The present invention is directed to a strained silicon on insulator (SSOI) structure having improved surface characteristics, such as reduced roughness, low concentration of LPDs, and lower contamination, and a method for making such a structure. ... 03/01/07 - 20070045737 - Semiconductor device and method for manufacturing the same A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions including ... 03/01/07 - 20070045736 - Finfet and method for manufacturing the same A gate electrode is arranged in a direction parallel or perpendicular to a specified crystal orientation of a substrate. A first transistor of a first conductivity type has a first active region, which is arranged in a direction perpendicular to the gate electrode. A second transistor of a second conductivity ... 03/01/07 - 20070045735 - Finfet structure with contacts A FinFET, which by its nature has both elevated source/drains and an elevated channel that are portions of an elevated semiconductor portion that has parallel fins and one source/drain on one side of the fins and another source/drain on the other side of the fins, has all of the source/drain ... 03/01/07 - 20070045734 - Thin film transistor and fabrication method thereof A thin film transistor is provided, including a substrate, a gate, a first dielectric layer, a channel layer, a source/drain and a second dielectric layer. The gate is disposed on the substrate, and the gate and the substrate are covered with the first dielectric layer. The channel layer is at ... 03/01/07 - 20070045733 - Programmable random logic arrays using pn isolation Disclosed are a programmable, random logic device array, and a method of forming such a device. The device comprises a substrate, and a semiconductor layer above the substrate. That semiconductor layer, in turn, includes a first region of a first semiconductor type, an array of spaced apart second regions of ... 03/01/07 - 20070045732 - Integrated circuit having a transistor level top side wafer contact and a method of manufacture therefor The present invention provides an integrated circuit and a method of manufacture therefor. The integrated circuit (100), in one embodiment without limitation, includes a dielectric layer (120) located over a wafer substrate (110), and a semiconductor substrate (130) located over the dielectric layer (120), the semiconductor substrate (130) having one ... 03/01/07 - 20070045731 - Flash memory device having resistivity measurement pattern and method of forming the same A flash memory device has a resistivity measurement pattern and method of forming the same. A trench is formed in an isolation film in a Self-Aligned Floating Gate (SAFG) scheme. The trench is buried to form a resistivity measurement floating gate. This allows the resistivity of the floating gate to ... 02/22/07 - 20070040218 - Hybrid-orientation technology buried n-well design A semiconductor structure is provided that includes a hybrid orientated substrate having at least two coplanar surfaces of different surface crystal orientations, wherein one of the coplanar surfaces has bulk-like semiconductor properties and the other coplanar surface has semiconductor-on-insulator (SOI) properties. In accordance with the present invention, the substrate includes ... 02/15/07 - 20070034954 - Thin film conductor and method of fabrication A thin film conductor having improved adhesion and superior conductivity, a method for fabricating the same, a thin film transistor (TFT) plate including the thin film conductor, and a method for fabricating the TFT plate are provided. The thin film conductor includes an adhesive layer containing an oxidation-reactive metal or ... 02/15/07 - 20070034953 - Semiconductor device and method of fabricating same A semiconductor device includes: a semiconductor substrate; a first transistor including a first gate electrode including a first metallic silicide layer, the first gate electrode being formed on the semiconductor substrate through a first gate insulating film, a first gate sidewall insulating film formed on a side face of the ... 02/15/07 - 20070034952 - Method of manufacturing semiconductor device having impurity region under isolation region In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming ... 02/15/07 - 20070034951 - Schotiky barrier tunnel transistor and method of manufacturing the same Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The ... 02/15/07 - 20070034950 - Semiconductor wafer and method of fabricating the same Disclosed is a semiconductor wafer and method of fabricating the same. The semiconductor wafer is comprised of a semiconductor layer formed on an insulation layer on a base substrate. The semiconductor layer includes a surface region organized in a first crystallographic orientation, and another surface region organized in a second ... 02/08/07 - 20070029614 - Semiconductor device with thin-film transistors and method of fabricating the same A semiconductor device with a TFT includes a substrate, an island-shaped semiconductor film serving as an active layer of the TFT on or over the substrate, a pair of source/drain regions formed in the semiconductor film, and a channel region formed between the pair of source/drain regions in the semiconductor ... 02/08/07 - 20070029613 - Electro-optical device, electronic apparatus, and method of manufacturing electro-optical device An electro-optical device includes: an electro-optical device substrate; step portions having a concave shape that are formed on a predetermined insulating film of the electro-optical device substrate; side wall portions each of which is formed on a side surface of the concave step portion between the surface of the insulating ... 02/08/07 - 20070029612 - Scalable high performance carbon nanotube field effect transistor A structure and fabrication process for a carbon nanotube field effect transistor is disclosed herein. The structure employs an asymmetric gate which is closer to the source and farther from the drain, which helps to minimize “off current” drain leakage when the drain is biased and the gate is otherwise ... 02/08/07 - 20070029611 - Integrated circuit having a top side wafer contact and a method of manufacture therefor The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the ... 02/01/07 - 20070023837 - Thin film transistor substrate and method of making the same The present invention relates to a thin film transistor substrate comprising: an insulating substrate; a source electrode and a drain electrode which are formed on the insulating substrate and separated from each other and have a channel area therebetween; a wall exposing at least portions of the source electrode and ... 02/01/07 - 20070023836 - Semiconductor device The present invention provides an MOSFET having a semiconductor substrate, an insulating layer provided on the semiconductor substrate, and an SOI layer provided on the insulating layer. A source region and a drain region are provided in the SOI layer. A non-doped region is provided at a position interposed between ... 02/01/07 - 20070023835 - Asymmetry thin-film transistor An asymmetry thin-film transistor includes a substrate, a semiconductor layer positioned on the substrate, and a gate positioned on the substrate. The semiconductor layer has a channel region, a single lightly doped region and a first heavily doped region positioned at a side of the channel region, and a second ... 02/01/07 - 20070023834 - Method of measuring a surface voltage of an insulating layer In a method of measuring a surface voltage of an insulating layer, the number of times that surface voltages are measured in a depletion region increases so that precise data about the depletion region may be obtained. The number of times that the surface voltages are measured in an accumulation ... 02/01/07 - 20070023833 - Method for reading a memory cell having an electrically floating body transistor, and memory cell and array implementing same An integrated circuit device (for example, logic or discrete memory device) including a memory cell including an electrically floating body transistor, wherein the electrically floating body transistor includes a source region, a drain region, a body region disposed between the source region and the drain region, wherein the body region ... 01/25/07 - 20070018247 - Method and apparatus for use in improving linearity of mosfet's using an accumulated charge sink A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, ... 01/25/07 - 20070018246 - Semiconductor device and semiconductor device manufacturing method A semiconductor device includes a back gate electrode composed of a first single-crystal semiconductor layer formed on a first insulating layer, a second insulating layer formed on the first single-crystal semiconductor layer, a second single-crystal semiconductor layer formed on the second insulating layer and having a film thickness smaller than ... 01/18/07 - 20070013002 - Field effect transistor with a heterostructure and associated production method A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1-x), where the proportion x ... 01/18/07 - 20070013001 - Epitaxial imprinting The present invention provides an epitaxial imprinting process for fabricating a hybrid substrate that includes a bottom semiconductor layer; a continuous buried insulating layer present atop said bottom semiconductor layer; and a top semiconductor layer present on said continuous buried insulating layer, wherein said top semiconductor layer includes separate planar ... 01/11/07 - 20070007596 - Method to manufacture silicon quantum islands and single-electron devices The present invention provides a method of manufacturing a single-electron transistor device (100). The method includes forming a thinned region (110) in a silicon substrate (105), the thinned region (110) offset by a non-selected region (115). The method also includes forming at least one quantum island (145) from the thinned ... 01/11/07 - 20070007595 - Semiconductor device with effective heat-radiation The semiconductor device has a silicon layer (SOI layer) (12) formed through a silicon oxide film (11) on a support substrate (10). A transistor (T1) is formed in the SOI layer (12). The wiring (17a) is connected with a source of the transistor (T1) through a contact plug (15a). A ... 01/11/07 - 20070007594 - Semiconductor device and method of manufacturing the same According to the present invention, there is provided a semiconductor device manufacturing method comprising: depositing a semiconductor layer and mask material in order over a semiconductor substrate on an insulating film; patterning the semiconductor layer and mask material to form a semiconductor layer in a predetermined region; removing a surface ... 01/04/07 - 20070001228 - Semiconductor device and method of manufacturing the same In a conventional method of crystallization using a laser beam, variance (or dispersion) in a TFT characteristic becomes large, which causes various functions of a semiconductor device comprising TFTs as components of its electronic circuit to be restrained. A first shape of semiconductor region having on its one side a ... 01/04/07 - 20070001227 - Manufacturing processing for an isolated transistor with strained channel Transistor type semiconducting device comprising: a substrate, an insulating layer comprising sidewalls formed on each part of the source zone and the drain zone, drain, channel and source zones, the channel zone being formed on the insulating layer and being strained by the drain and the source zones, between the ... 01/04/07 - 20070001226 - Semiconductor device The present invention provides a semiconductor device in which a first conductive layer included in a stack having a transistor and a second conductive layer over a substrate are electrically connected. The semiconductor device provides a s conductive layer for electrically connecting the first conductive layer included in the stack ... 01/04/07 - 20070001225 - Semiconductor device and manufacturing method of the same To provide a manufacturing method in which LDD regions with different widths are formed in a self-aligned manner, and the respective widths are precisely controlled in accordance with each circuit. By using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function formed of ... 01/04/07 - 20070001224 - Minute structure, micromachine, organic transistor, electric appliance, and manufacturing method thereof A micromachine is generally formed using a semiconductor substrate such as a silicon wafer. One of the objects of the present invention is to realize further reduction in cost by integrating a minute structure and a semiconductor element controlling the minute structure over one insulating surface in one step. A ... 01/04/07 - 20070001223 - Ultrathin-body schottky contact mosfet An ultra thin SOI MOSFET device structure and method of fabrication is presented. The device has a terminal composed of silicide, which terminal is forming a Schottky contact with the channel. A plurality of impurities are segregated on the silicide/channel interface, and these segregated impurities determine the resistance of the ... 01/04/07 - 20070001222 - Single transistor memory cell with reduced recombination rates A semiconductor fabrication method includes forming a semiconductor structure including source/drain regions disposed on either side of a channel body wherein the source/drain regions include a first semiconductor material and wherein the channel body includes a migration barrier of a second semiconductor material. A gate dielectric overlies the semiconductor structure ... 12/28/06 - 20060289934 - Semiconductor device, liquid crystal display panel, electronic device, and method of manufacturing semiconductor device In a plurality of transistors in which the thresholds that are required in the circuit design are equal, a transistor having an initial threshold at a lower limit within an acceptable range of the required threshold is arranged at a circuit position where an absolute value of a threshold voltage ... 12/21/06 - 20060284253 - Organic thin film transistor and method of manufacturing the same An organic thin film transistor (OTFT) includes a substrate, a gate electrode formed on the transparent substrate, a gate insulation film formed on the gate electrode, a source electrode and a drain electrode formed spaced apart from each other on the gate insulation film, a device insulation film formed over ... 12/21/06 - 20060284252 - Process for holding strain in an island etched in a strained thin layer and structure obtained by implementation of this process The invention relates to structures useful for the manufacture of electronic components, which comprise a substrate, a strain holding layer, and a layer of a strained semiconducting material. These structures are particularly useful where islands are later formed in the strained semiconducting material because the strain holding layer limits relaxation ... 12/21/06 - 20060284251 - Coplanar silicon-on-insulator (soi) regions of different crystal orientations and methods of making the same In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI ... 12/21/06 - 20060284250 - Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions ... 12/14/06 - 20060278927 - Body biasing structure of soi A body biasing structure of devices connected in series on an SOI substrate is provided. According to some embodiments, the shallow junction of common source/drain regions enables all devices to bias by only one body contact on an SOI substrate like a conventional bulk MOSFET, and the floating body effect ... 12/14/06 - 20060278926 - Capacitorless dram on bulk silicon A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A ... 12/07/06 - 20060273394 - Semiconductor device and method of manufacturing same A semiconductor device which achieves reductions in malfunctions and operating characteristic variations by reducing the gain of a parasitic bipolar transistor, and a method of manufacturing the same are provided. A silicon oxide film (6) is formed partially on the upper surface of a silicon layer (3). A gate electrode ... 12/07/06 - 20060273393 - Structure and method of making field effect transistor having multiple conduction states A field effect transistor (“FET”) is provided has a semiconductor region including a channel region, a source region and a drain region and a gate conductor overlying the channel region. Such FET has a first threshold voltage having a first magnitude and a second threshold voltage having a second magnitude ... 11/30/06 - 20060267097 - Method for forming a mos transistor and structure thereof A method for forming a MOS transistor having LDD structure by a simple and a few number of processes and a structure thereof are described. In accordance with the present invention, a low concentration of an impurity region can be formed in a semiconductor film part between an end of ... 11/30/06 - 20060267096 - Method of designing semiconductor device, semiconductor device and recording medium A semiconductor device including a transistor having an SOI structure the operating speed of which is not affected is provided. A MOS transistor having the SOI structure is formed which satisfies R·C·f<1 where C is a gate capacitance (F), R is a body resistance (Ω), f is a clock operating ... 11/30/06 - 20060267095 - Semiconductor device A semiconductor device capable of reducing deterioration of electron mobility while suppressing depletion of gate electrodes is provided. This semiconductor device includes a metal-containing layer so formed that at least either a first gate electrode or a second gate electrode partially covers a corresponding first or second gate insulating film ... 11/30/06 - 20060267094 - Organic thin film transistor, method of fabricating the same, and flat panel display having the organic thin film transistor An organic thin film transistor that prevents the surface of an organic semiconductor layer from being damaged and reduces turn-off current, a method of fabricating the same, and an organic light-emitting device incorporating the organic thin film transistor. The organic thin film transistor includes a substrate, source and drain electrodes ... 11/30/06 - 20060267093 - Floating-body dynamic random access memory and method of fabrication in tri-gate technology A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A ... 11/23/06 - 20060261409 - Si nanowire substrate, method of manufacturing the same, and method of manufacturing thin film transistor using the same A silicon nanowire substrate having a structure in which a silicon nanowire film having a fine line-width is formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the silicon nanowire substrate includes preparing ... 11/16/06 - 20060255409 - Anomaly notification control in disk array In a storage device incorporating a plurality of kinds of disk drives with different interfaces, the controller performs sparing on a disk drive, whose errors that occur during accesses exceed a predetermined number, by swapping it with a spare disk drive that is prepared beforehand. ... 11/16/06 - 20060255408 - Semiconductor device and method for manufacturing the same There is provided a semiconductor device in which the characteristic variations of a transistor and the degradation of a gate oxide layer are reduced during a WP process and a method for manufacturing the same. The semiconductor device includes a semiconductor chip having an SOI transistor. The SOI transistor includes ... 11/16/06 - 20060255407 - Semiconductor device and manufacturing method of the same In a peripheral insulating film in a peripheral region, concave parts are provided. At least one of the concave parts is made to have an opening as a contact hole with an Al wiring layer, and a plurality of contact holes may be provided. Accordingly, frictions between the Al wiring ... 11/16/06 - 20060255406 - Semiconductor device An object of the present invention is to provide a semiconductor device which enables to reduce the device area, while securing the breakdown voltage between the drain and the source of each MOS transistor for the semiconductor device including plural MOS transistors, which are arrayed adjacently each other, with different ... 11/16/06 - 20060255405 - Fully-depleted soi mosfet device and process for fabricating the same The present invention proposes a nano-scale high-performance SOI MOSFET device and a process for manufacturing the same. The device is characterized by comprising: a metal oxide semiconductor, formed on the SOI substrate; a silicide layer (05), wherein a gate consists of a single full silicide gate (10), a high-K dielectric ... 11/09/06 - 20060249790 - Method for fabricating sige-on-insulator (sgoi) and ge-on-inulator (goi) substrates A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the ... 11/09/06 - 20060249789 - Inter-digitated silicon photodiode based optical receiver on soi A photodiode includes SOI substrate and a plurality of interdigitated electrodes comprising of different doped regions. A silicon device region is defined in the SOI substrate having a thickness between 0.5 and 5 microns. ... 11/02/06 - 20060244066 - Contacts to semiconductor fin devices A method for forming a contact to a semiconductor fin which can be carried out by first providing a semiconductor fin that has a top surface, two sidewall surfaces and at least one end surface; forming an etch stop layer overlying the fin; forming a passivation layer overlying the etch ... 11/02/06 - 20060244065 - Semiconductor device and manufacturing method thereof A semiconductor device includes a substrate having first and second regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in the second region and having an upper surface higher than an upper surface of the first insulating film, ... 11/02/06 - 20060244064 - Semiconductor device for limiting leakage current Formed on an insulator (9) are an N− type semiconductor layer (10) having a partial isolator formed on its surface and a P− type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P+ type semiconductor layers are provided on the semiconductor layer (10) ... 11/02/06 - 20060244063 - Thin film transistor and manufacturing method thereof The present invention provides a thin film transistor in which a substantial length of a channel is shortened to miniaturize a semiconductor device and a manufacturing method thereof. In addition, the present invention provides a semiconductor device which realizes high-speed operation and high-performance of the semiconductor device and a manufacturing ... 11/02/06 - 20060244062 - Silicon-on-insulator based radiation detection device and method Structures and a method for detecting ionizing radiation using silicon-on-insulator (SOI) technology are disclosed. In one embodiment, the invention includes a substrate having a buried insulator layer formed over the substrate and an active layer formed over the buried insulator layer. Active layer may be fully depleted. A transistor is ... 11/02/06 - 20060244061 - Integrated circuit (ic) with high-q on-chip discrete capacitors A semiconductor structure that may be a discrete capacitor, a Silicon On Insulator (SOI) Integrated Circuit (IC) including circuits with discrete such capacitors and/or decoupled by such discrete capacitors and an on-chip decoupling capacitor (decap). One capacitor plate may be a well (N-well or P-well) in a silicon bulk layer ... 10/26/06 - 20060237790 - Structure and method for manufacturing planar soi substrate with multiple orientations The present invention provides a method of forming a substantially planar SOI substrate having multiple crystallographic orientations including the steps of providing a multiple orientation surface atop a single orientation layer, the multiple orientation surface comprising a first device region contacting and having a same crystal orientation as the single ... 10/26/06 - 20060237789 - Thin film transistor (tft) and flat panel display including the tft A Thin Film Transistor (TFT) that can reduce leakage current and can prevent crosstalk between adjacent TFTs includes: a substrate; a gate electrode disposed on the substrate; a source electrode and a drain electrode separated from each other and insulated from the gate electrode; and a semiconductor layer which is ... 10/26/06 - 20060237788 - Semiconductor device and its fabrication method A semiconductor device has a semiconductor substrate, a first MOSFET which has a first gate insulating film made of a high dielectric material formed above the semiconductor substrate and a first gate electrode formed above the first gate insulating film, an insulating film which is formed directly on sidewalls of ... 10/19/06 - 20060231894 - Transistor A transistor comprises: an insulating layer; a semiconductor layer provided on a major surface of the insulating layer; a gate insulating layer provided on the base region; and a gate electrode provided on the gate insulating layer. The semiconductor layer has a source portion having a plurality of source regions ... 10/19/06 - 20060231893 - Hybrid crystal orientation cmos structure for adaptive well biasing and for power and performance enhancement The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device ... 10/19/06 - 20060231892 - Enhanced silicon-on-insulator (soi) transistors and methods of making enhanced soi transistors Enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. A selective epitaxial growth is utilized in the source/drain regions ... 10/19/06 - 20060231891 - Soi sram products with reduced floating body effect and the method thereof A memory device is formed on a semiconductor-on-insulator (SOI) structure, the SOI structure including a substrate, an insulating layer on the substrate, and a semiconductor film on the insulating layer. The memory device includes a memory array in a memory region of the SOI structure, a plurality of first substrate ... 10/12/06 - 20060226486 - Semiconductor device The present invention provides a semiconductor device which has a substrate formed as a rigid body, stress relaxation layers formed by filling in concave portions defined in a first main surface of the substrate, and a device forming layer which covers part of the first main surface and is formed ... 10/12/06 - 20060226485 - Semiconductor device A semiconductor element is configured to prevent deterioration thereof due to an electrical charge occurring at a top surface/bottom surface of a support substrate during a plasma process in manufacturing a semiconductor device using an SOI substrate. The semiconductor device includes a MOS transistor formed on an SOI layer of ... 10/12/06 - 20060226484 - Thin film transistor A thin film transistor (TFT) is disclosed, and the thin film transistor comprises: a substrate, a gate electrode, a first adhesion layer, a gate insulting layer, a semiconductor layer, and a source electrode and a drain electrode. The gate electrode is formed on the substrate, and the gate electrode is ... 10/12/06 - 20060226483 - Method of fabricating strained channel devices A process for forming both tensile and compressive strained silicon layers to accommodate channel regions of MOSFET or CMOS devices has been developed. After formation of shallow trench isolation structures as well as application of high temperature oxidation and activation procedures, the fabrication sequences used to obtain the strained silicon ... 10/12/06 - 20060226482 - Methods of fabricating silicon nitride regions in silicon carbide and resulting structures A method is disclosed for fabricating a silicon nitride regions in silicon carbide. The method includes the steps of implanting a sufficient dose and energy of nitrogen ions into a silicon carbide substrate maintained at a temperature above about 350° C. to produce an as-implanted layer of a silicon nitride ... 10/12/06 - 20060226481 - Simplified vertical array device dram/edram integration: method and structure The present invention provides a semiconductor structure that includes an active wordline located above a semiconductor memory device and a passive wordline located adjacent to said active wordline and above an active area of a substrate. In accordance with the present invention, the passive wordline is separated from the active ... 10/12/06 - 20060226480 - Method for fabricating oxygen-implanted silicon on insulation type semiconductor and semiconductor formed therefrom The invention relates generally to a method for fabricating oxygen-implanted semiconductors, and more particularly to a method for fabricating oxygen-implanted silicon-on-insulation (“SOI”) type semiconductors by cutting-up regions into device-sized pieces prior to the SOI-oxidation process. The process sequence to make SOI is modified so that the implant dose may be ... 10/05/06 - 20060220133 - Doping of semiconductor fin devices A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. ... 10/05/06 - 20060220132 - Semiconductor substrate, semiconductor device, method of manufacturing semiconductor substrate, and method of manufacturing semiconductor device A method of manufacturing a semiconductor device, includes: forming an insulating layer on a single crystal semiconductor substrate; forming a non-crystalline semiconductor layer on the insulating layer; forming an insulating film on the non-crystalline semiconductor layer; forming an opening section for exposing a part of a surface of the single ... 10/05/06 - 20060220131 - Fin-type channel transistor and method of manufacturing the same It is possible to reliably implant an impurity into an impurity forming region, and to form a self-aligned silicides on the entire portion of the source and drain regions. There are provided: a first semiconductor layer of a first conductivity type in a substantially a rectangular solid shape formed on ... 10/05/06 - 20060220130 - High breakdown voltage semiconductor device and fabrication method of the same A high breakdown voltage semiconductor device is formed using an SOI substrate comprising a support substrate, an insulating film, and an active layer. The high breakdown voltage semiconductor device comprises an N-type well region and a P-type drain offset region formed on the active layer, a P-type source region formed ... 10/05/06 - 20060220129 - Hybrid fully soi-type multilayer structure The invention relates to a silicon-on-insulator-type multilayer structure that includes a support layer, at least two working layers having different crystalline orientations, and an insulating layer extending over at least a portion of the support layer. This insulating layer extends over the whole surface of the support layer so as ... 10/05/06 - 20060220128 - Semiconductor substrate, semiconductor device, method for manufacturing semiconductor substrate and method for manucfacturing semiconductor device A semiconductor substrate comprising a semiconductor base, a dielectric layer formed in at least a part of an area on the semiconductor base, and a single crystal semiconductor layers having mutually different film thicknesses, disposed on the dielectric layer and formed by epitaxial growth. ... 10/05/06 - 20060220127 - Method for producing a tensioned layer on a substrate, and a layer structure The invention relates to a method for producing a tensioned layer on a substrate involving the following steps: producing a defect area in a layer adjacent to the layer to be tensioned, and; relaxing at least one layer adjacent to the layer to be tensioned. Additional layers can be epitaxially ... 10/05/06 - 20060220126 - Method of manufacturing an electronic arrangement The device of the invention comprises a thin film transistor of an organic semiconductor material. This semiconductor material is patterned by applying first a protective layer and thereafter a photoresist. As a result hereof, the transistor of the invention (A) shows a very low leakage current and a low threshold ... 09/28/06 - 20060214231 - Nonplanar device with thinned lower body portion and method of fabrication A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top ... 09/28/06 - 20060214230 - Sos wafer and manufacturing method thereof The present invention provides an SOS wafer comprising a non-transparent polysilicon layer provided on a back surface of a sapphire substrate, a silicon nitride layer which protects the polysilicon layer, and a stress relaxing film which cancels stress produced in the silicon nitride layer, wherein the silicon nitride layer and ... 09/28/06 - 20060214229 - Semiconductor device and image display apparatus A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor including a source region, a drain region, a channel region having a predetermined channel length, an LDD region and GOLD region having an impurity ... 09/28/06 - 20060214228 - Semiconductor device and boost circuit A semiconductor device includes a transistor that is used for a charge pump circuit, being configured with a fully depleted silicon-on-insulator transistor. ... 09/28/06 - 20060214227 - Semiconductor memory device and method of manufacturing semiconductor memory device A semiconductor memory device includes an insulation layer provided on a semiconductor substrate; a semiconductor layer provided on the insulation layer; a source layer of a first conductivity type formed in the semiconductor layer; a drain layer of the first conductivity type formed in the semiconductor layer; a body region ... 09/28/06 - 20060214226 - Method for forming an soi structure with improved carrier mobility and esd protection A semiconductor device and method for forming the same including improved electrostatic discharge protection for advanced semiconductor devices, the semiconductor device including providing semiconductor substrate having a pre-selected surface orientation and crystal direction; an insulator layer overlying the semiconductor substrate; a first semiconductor active region overlying the insulator layer having ... 09/28/06 - 20060214225 - High performance field effect transistors on soi substrate with stress-inducing material as buried insulator and methods The present invention provides a semiconductor structure that includes a high performance field effect transistor (FET) on a semiconductor-on-insulator (SOI) in which the insulator thereof is a stress-inducing material of a preselected geometry. Such a structure achieves performance enhancement from uniaxial stress, and the stress in the channel is not ... 09/28/06 - 20060214224 - Semiconductor device and process for producing the same A semiconductor device comprising a substrate of SiC provided with an insulating film through plasma treatment. Rare gas is incorporated in the insulating film. Preferably, at least one of krypton (Kr), argon (Ar) and xenon (Xe) is used as the rare gas. A combination of oxygen gas and krypton (Kr) ... 09/14/06 - 20060202269 - Wireless chip and electronic appliance having the same The present invention provides a wireless chip having high mechanical strength. Moreover, the present invention also provides a wireless chip which can prevent an electric wave from being blocked. In a wireless chip of the present invention, a layer having a thin film transistor formed over an insulating substrate is ... 09/14/06 - 20060202268 - Soi semiconductor device and method of manufacturing thereof An SOI semiconductor device has a substrate, an insulation film, a silicon film, a gate insulation film, a gate electrode, a pair of first diffusion regions, a first region, and a second diffusion region. The insulation film is formed on the substrate. The silicon film is formed on the insulation ... 09/07/06 - 20060197156 - Power semiconductor and method of fabrication This invention is generally concerned with power semiconductors such as power MOS transistors, insulated gate by bipolar transistors (IGBTs), high voltage diodes and the like, and methods for their fabrication. A power semiconductor, the semiconductor comprising: a power device, said power device having first and second electrical contact regions and ... 09/07/06 - 20060197155 - Nonvolatile memory and manufacturing method thereof Memory elements, switching elements, and peripheral circuits to constitute a nonvolatile memory are integrally formed on a substrate by using TFTs. Since semiconductor active layers of memory element TFTs are thinner than those of other TFTs, impact ionization easily occurs in channel regions of the memory element TFTs. This enables ... 09/07/06 - 20060197154 - Semiconductor component and method of manufacture A semiconductor component having analog and logic circuit elements manufactured from an SOI substrate and a method for manufacturing the semiconductor component. An SOI substrate has a support wafer coupled to an active wafer through an insulating material. Openings are formed in the active wafer, extend through the insulating material, ... 08/24/06 - 20060186476 - Method of manufacturing thin film transistor On a glass substrate an insulating protective layer comprising SiO2 film is formed, and an active layer comprising a p-Si film is formed thereon. Further, a first gat insulating film comprising an SiN film which serves as a lower layer and a second gate insulating film comprising an SiN film ... 08/24/06 - 20060186475 - Thin film transistor having high mobility and high on-current and method for manufacturing the same An image input apparatus includes an insulating substrate; polycrystalline silicon islands formed on said insulating substrate; pixels each including thin film transistors and a photodiode formed above said thin film transistors, each of the thin film transistors have a source region, a channel region and a drain region foamed in ... 08/24/06 - 20060186474 - Semiconductor device and method of manufacturing the same It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source region (51), a drain ... 08/24/06 - 20060186473 - Method of forming an implantable electronic device chip level hermetic and biocompatible electronics package using soi wafers The invention is directed to a hermetically packaged and implantable integrated circuit for electronics that is made my producing streets in silicon-on-insulator chips that are subsequently coated with a selected electrically insulating thin film prior to completing the dicing process to yield an individual chip. A thin-layered circuit may transmit ... 08/24/06 - 20060186472 - Semiconductor apparatus and complimentary mis logic circuit A configuration is adopted comprising an NchMOS transistor 1 equipped with an insulating isolation layer 4 providing insulation and isolation using an SOI structure, and a capacitor formed using an insulating film, with a silicon substrate B being made thin and substrate capacitance being reduced. The NchMOS transistor 1 is ... 08/17/06 - 20060180862 - Semiconductor device, driver circuit and manufacturing method of semiconductor device The present invention provides a semiconductor technology capable of suppressing an increase in threshold voltage of a transistor and, also, improving a withstand voltage between a source region and a drain region. Source and drain regions of a p channel type MOS transistor are formed in an n− type semiconductor ... 08/17/06 - 20060180861 - Semiconductor device and method for manufacturing semiconductor device In a semiconductor device, a gate electrode, an impurity diffused region, a body potential fixing region, a first insulator, and a dummy gate electrode are provided on top of an SOI substrate consisting of an underlying silicon substrate, a buried insulator, and a semiconductor layer. The impurity diffused region is ... 08/17/06 - 20060180860 - Image sensor An image sensor including an image sensing device layer, a silicon-on-insulator (SOI) layer, an optical device array and a substrate is provided. The SOI layer has a first surface and a second surface. The image sensing device layer is formed on the first surface of the SOI layer. The optical ... 08/17/06 - 20060180859 - Metal gate carbon nanotube transistor A top metal gate carbon nanotube transistor may be provided which has acceptable electrical characteristics. The transistor may be formed over a structure including a semiconductor substrate made of an epitaxial layer and covered with an insulating layer. The carbon nanotubes may be deposited thereover, source and drains defined, and ... 08/10/06 - 20060175661 - Soi mosfet device with reduced polysilicon loading on active area Silicon-on-insulator (SOI) devices with reduced polysilicon loading on an active area uses at least one dielectric layer resistant to silicidation to separate at least one body contact region from source/drain regions, thus reducing gate capacitance and improving device performance. The SOI devices may be used in full depletion type transistors ... 08/10/06 - 20060175660 - Vertical body-contacted soi transistor A vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region ... 08/10/06 - 20060175659 - A cmos structure for body ties in ultra-thin soi (utsoi) substrates The present invention provides a semiconducting structure including a substrate having an UTSOI region and a bulk-Si region, wherein the UTSOI region and the bulk-Si region have a same crystallographic orientation; an isolation region separating the UTSOI region from the bulk-Si region; and at least one first device located in ... 08/03/06 - 20060170051 - Semiconductor circuit constructions The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor substrate. The first semiconductor substrate has a semiconductive material projection extending therefrom, and the second semiconductor substrate has ... 08/03/06 - 20060170050 - Fully depleted silicon-on-insulator cmos logic A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the body region of partially depleted memory cells. This causes the body region to be fully depleted without the adverse floating body effects. ... 08/03/06 - 20060170049 - Mosfet In various aspects, a MOSFET may include an active region of a first conductivity type provided on an insulating layer, the active region having a first portion and a second portion, the first portion being thicker than the second portion; a base region of the first conductivity type provided on ... 08/03/06 - 20060170048 - Thin film transistor array substrate and fabrication method thereof A thin film transistor array substrate is disclosed. A gate electrode is disposed overlying a substrate. A gate dielectric layer covers the substrate and the gate electrode. A semiconductor layer is disposed overlying the gate dielectric layer, wherein the semiconductor layer comprises a channel. A source electrode electrically connects a ... 08/03/06 - 20060170047 - Semiconductor device and method of manufacturing the same A semiconductor device according to an embodiment of the present invention comprises a semiconductor substrate; and a plurality of MOSFETs which are formed on the semiconductor substrate, are the same conductivity type, and have gate insulating films of the same insulating material, with each gate insulating film having any one ... 08/03/06 - 20060170046 - Semiconductor device and manufacturing method thereof A method for manufacturing a semiconductor device, including the steps of: forming a shielding film 38 on a first insulating film 37; sequentially forming a second insulating film 39 and an amorphous semiconductor film 40 on the shielding film 38; melting the amorphous semiconductor film 40 at least in portions ... 08/03/06 - 20060170045 - Semiconductor method and device with mixed orientation substrate A semiconductor device includes a semiconductor body having semiconductor material of a first crystal orientation. A first transistor is formed in the semiconductor material of the first crystal orientation. An insulating layer overlies portions of the semiconductor body and a semiconductor layer overlies the insulating layer. The semiconductor layer has ... 08/03/06 - 20060170044 - One-transistor random access memory technology integrated with silicon-on-insulator process An one-transistor random access memory device integrated on a silicon-on-insulator (SOI) substrate has a capacitor structure buried in at least part of a capacitor trench in the SOI substrate, and a gate structure formed on the SOI substrate. A top electrode the capacitor structure is formed simultaneously with and of ... 07/27/06 - 20060163655 - Semiconductor device An exemplary embodiment includes a semiconductor device. The semiconductor device can include a channel including one or more compounds of the formula AxBxOx, wherein each A is selected from the group of Cu, Ag, Sb, each B is selected from the group of Cu, Ag, Sb, Zn, Cd, Ga, In, ... 07/27/06 - 20060163654 - Silicon-on-insulator device A Silicon on Insulator (SOI) device is disclosed wherein an extension of P-type doping (303) is implanted between the buried oxide layer of the device and the SOI layer. The extension is of a size and shape to permit the source (309) to be biased at a voltage significantly less ... 07/20/06 - 20060157787 - Thin film transistor having double-layered gate electrode and method of manufacturing the thin film transistor A thin film transistor (TFT) that can prevent damage to a silicon layer under a gate electrode in an annealing process by using a first gate electrode having high thermal resistance and a second gate electrode having high reflectance and a method of manufacturing the TFT are provided. The method ... 07/20/06 - 20060157786 - Semiconductor device and manufacturing method thereof A semiconductor device of the present invention includes: an SOI substrate that is a semiconductor wafer on which a semiconductor active layer is formed via a laminated insulating film; an insulating film which is arranged in a device isolation region surrounding an element forming region of the SOI substrate, and ... 07/20/06 - 20060157785 - Semiconductor storage device According to the present invention, there is provided a semiconductor storage device having a memory cell, comprising: a buried electrode formed on a semiconductor substrate; a semiconductor layer formed on said buried electrode via a buried insulating film; a surface electrode formed on said semiconductor layer via an insulating film; ... 07/20/06 - 20060157784 - Mos field effect transistor and manufacture method therefor A method of manufacturing an MOS field effect transistor, which achieves a faster operation and lower power consumption by using a thin film SOI structure, is provided. The method of manufacturing an MOS field effect transistor to be formed on a semiconductor substrate having a channel layer on a buried ... 07/20/06 - 20060157783 - Semiconductor device having trench isolation for differential stress and method therefor A semiconductor device has trenches for defining active regions. After a thin diffusion barrier is deposited in the trenches, some of the trenches are selectively etched to leave different areas in the trench. One of the areas has the diffusion barrier completely removed so that the underlying layer is exposed. ... 07/13/06 - 20060151835 - Semiconductor device and method of fabricating same There are disclosed TFTs having improved reliability. An interlayer dielectric film forming the TFTs is made of a silicon nitride film. Other interlayer dielectric films are also made of silicon nitride. The stresses inside the silicon nitride films forming these interlayer dielectric films are set between −5×109 and 5×109 dyn/cm2. ... 07/13/06 - 20060151834 - High mobility plane finfet with equal drive strength An integrated circuit structure has a buried oxide (BOX) layer above a substrate, and a first-type fin-type field effect transistor (FinFET) and a second-type FinFET above the BOX layer. The second region of the BOX layer includes a seed opening to the substrate. The top of the first-type FinFET and ... 07/13/06 - 20060151833 - Transistor structure having stressed regions of opposite types underlying channel and source/drain regions An integrated circuit and method of fabrication are provided in which the integrated circuit includes a field effect transistor (FET) having a channel region and source and drain regions adjacent to the channel region. A first stressed region having a first type of stress is provided to underlie the channel ... 07/06/06 - 20060145255 - Thin film transistor substrate Disclosed are a thin film transistor substrate of an LCD device and a method of manufacturing the same. The thin film transistor substrate includes a nickel-silicide layer formed on an insulating layer pattern including silicon and a metal layer formed on the nickel-silicide layer. Nickel is coated on the insulating ... 06/29/06 - 20060138542 - Semiconductor on insulator substrate and devices formed therefrom A semiconductor on insulator (SOI) device is comprised of a layer of a dielectric material having a perovskite lattice, such as a rare earth scandate. The dielectric material is selected to have an effective lattice constant that enables growth of semiconductor material having a diamond lattice directly on the dielectric. ... 06/29/06 - 20060138541 - Semiconductor device and method of manufacturing same A high-speed, low-power-consumption semiconductor device has a thin-film Si layer with a source/drain formed therein. The thin-film Si layer is curved from a region directly below a gate electrode toward a region near the source/drain. The curved thin-film Si layer develops strains in a channel region disposed directly below the ... 06/29/06 - 20060138540 - Semiconductor wafer having a semiconductor layer and an electrically insulating layer beneath it, and process for producing it The invention relates to a semiconductor wafer, which, at its surface comprises a semiconductor surface layer with a thickness in the range from 3 nm to 200 nm having no hole defects, and which comprises an adjoining electrically insulating layer beneath the semiconductor surface layer. ... 06/29/06 - 20060138539 - Process for treating a semiconductor wafer with a gaseous medium, and semiconductor wafer treated by this process A process for treating a semiconductor wafer with a gaseous medium containing hydrogen fluoride and at least one oxidizing agent which oxidizes the surface of the semiconductor wafer, involves flowing the gaseous medium onto the surface of the semiconductor wafer at a relative velocity in the range from 40 mm/s ... 06/22/06 - 20060131651 - Semiconductor substrate and its fabrication method To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate. ... 06/22/06 - 20060131650 - Bipolar reading technique for a memory cell having an electrically floating body transistor A technique of sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one embodiment, the present inventions are directed to a ... 06/22/06 - 20060131649 - Semiconductor wafer with an epitaxially deposited layer, and process for producing the semiconductor wafer A semiconductor wafer is formed of a substrate wafer of single crystal silicon doped with dopant atoms of the n type or p type, with a front surface and a back surface, contains a layer deposited epitaxially on the front surface of the substrate wafer. The substrate wafer additionally includes ... 06/22/06 - 20060131648 - Ultra thin film soi mosfet having recessed source/drain structure and method of fabricating the same There are provided an ultra thin film silicon on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) having a recessed source/drain structure, and a method of fabricating the same. The ultra thin film SOI MOS transistor includes a semiconductor substrate; a buried insulating layer disposed on the semiconductor substrate, ... 06/15/06 - 20060125011 - Memory with split gate devices and method of fabrication A DRAM fabricated on an SOI substrate employing single body devices as memory cells without relying on a field through the insulative layer of the SOI is described. Floating body devices are defined by orthogonally disposed lines with both a front gate and back gate for each body being formed ... 06/15/06 - 20060125010 - Methods of forming transistor constructions The invention includes a non-volatile memory cell comprising a field effect transistor construction having a body region within a crystalline material. The body region includes a charge trapping region. The memory cell can be TFT-SOI based, and can be supported by a substrate selected from a diverse assortment of materials. ... 06/15/06 - 20060125009 - Thin film transistors including indolocarbazoles A thin film transistor composed of a semiconductor layer including an optionally substituted indolocarbazole. ... 06/15/06 - 20060125008 - Dual stressed soi substrates The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a ... 06/08/06 - 20060118873 - Semiconductor device and manufacturing method thereof A semiconductor device includes a substrate having first to fourth regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in the second region and having an upper surface higher than an upper surface of the first insulating film, ... 06/08/06 - 20060118872 - Semiconductor device and method of manufacturing the same A semiconductor device includes: a semiconductor layer portion provided on an insulating layer, the semiconductor layer portion becoming an element formation region; a gate insulating layer provided on the semiconductor layer portion; a gate electrode provided on the gate insulating layer; and an impurity region provided in the semiconductor layer ... 06/08/06 - 20060118871 - Semiconductor device, semiconductor memory device, and method of manufacturing semiconductor device A semiconductor device includes a first semiconductor layer that is formed on a first insulating layer; a second insulating layer that is formed on the first semiconductor layer; a second semiconductor layer that is formed on the second insulating layer; a first gate electrode that is formed on the second ... 06/08/06 - 20060118870 - Structure of strained silicon on insulator and method of manufacturing the same Provided is a strained SOI structure and a method of manufacturing the strained SOI structure. The strained SOI structure includes an insulating substrate, a SiO2 layer formed on the insulating substrate, and a strained silicon layer formed on the SiO2 layer. ... 06/08/06 - 20060118869 - Thin-film transistors and processes for forming the same A TFT includes a substrate and a first semiconductor layer overlying the substrate. A portion of the first semiconductor layer is a channel region of the TFT. The TFT also includes spaced-apart first and second source/drain structures overlying the first semiconductor layer. From a plan view of the TFT, the ... 06/08/06 - 20060118868 - A semiconductor substrate comprising a support substrate which comprises a gettering site A semiconductor substrate includes a support substrate 1 has gettering sites 10 for gettering impurity metal, an embedded insulating film 2 which is provided on the support substrate 1 and contains oxides of an element whose single bond energy to oxygen is higher than that to silicon, and a semiconductor ... 06/08/06 - 20060118867 - Semiconductor component with stress-carrying semiconductor layer and corresponding production method The invention relates to a semiconductor component with stress-absorbing semiconductor layer (SA) and an associated fabrication method, a crystalline stress generator layer (SG) for generating a mechanical stress being formed on a carrier material (1). An insulating stress transmission layer (2), which transmits the mechanical stress which has been generated ... 06/01/06 - 20060113598 - Device and method for fabricating double-sided soi wafer scale package with optical through via connections A semiconductor package includes an SOI wafer having a first side including an integrated circuit system, and a second side, opposite the first side, forming at least one cavity. At least one chip or component is placed in the cavity. An optical through via is formed through a buried oxide ... 06/01/06 - 20060113597 - Semiconductor device and manufacturing method thereof In a semiconductor device, typically an active matrix display device, the structure of TFTs arranged in the respective circuits are made suitable in accordance with the function of the circuit, and along with improving the operating characteristics and the reliability of the semiconductor device, the manufacturing cost is reduced and ... 06/01/06 - 20060113596 - Single crystal substrate and method of fabricating the same A high quality single crystal substrate and a method of fabricating the same are provided. The method of fabricating a single crystal substrate includes: forming an insulator on a substrate; forming a window in the insulator, the window exposing a portion of the substrate; forming an epitaxial growth silicon or ... 06/01/06 - 20060113595 - Rectangular substrate dividing apparatus A rectangular substrate dividing apparatus, which can divide a rectangular substrate in a smaller space, accommodate devices, formed as individual pieces by the division, into device cases, and pick up the devices reliably and efficiently from a protective tape affixed to the back of the rectangular substrate, is provided. This ... 06/01/06 - 20060113594 - Soi wafer and production method therefor An SOI wafer in which a base wafer and a bond wafer respectively consisting of silicon single crystal are bonded via an oxide film, and then the bond wafer is thinned to form a silicon active layer, wherein the base wafer is formed of silicon single crystal grown by Czochralski ... 05/25/06 - 20060108636 - Amorphous oxide and field effect transistor A novel amorphous oxide applicable, for example, to an active layer of a TFT is provided. The amorphous oxide comprises microcrystals. ... 05/18/06 - 20060102954 - Organic thin film transistor array panel and manufacturing method thereof A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on a substrate; forming a gate insulating layer on the gate line; depositing an ITO layer at a temperature of about 20-35° C.; etching the ITO layer to form a data ... 05/11/06 - 20060097318 - Transistor with silicon and carbon layer in the channel region A transistor and method of manufacturing thereof having stressed material layers formed in the channel to increase the speed and improve performance of the transistor. A layer of silicon and carbon is epitaxially grown in the channel region. A thin semiconductor material may be formed over the layer of silicon ... 05/11/06 - 20060097317 - Semiconductor substrate and process for producing it A semiconductor substrate useful as a donor wafer is a single-crystal silicon wafer having a relaxed, single-crystal layer containing silicon and germanium on its surface, the germanium content at the surface of the layer being in the range from 10% by weight to 100% by weight, and a layer of ... 05/11/06 - 20060097316 - Semiconductor structure and method for integrating soi devices and bulk devices This invention discloses a method and a semiconductor structure for integrating at least one bulk device and at least one silicon-on-insulator (SOI) device. The semiconductor structure includes a first substrate having an SOI area and a bulk area, on which the bulk device is formed; an insulation layer formed on ... 05/04/06 - 20060091462 - Memory cell having an electrically floating body transistor and programming technique therefor A semiconductor memory cell comprising an electrically floating body transistor including a source region, a drain region, a body region disposed between the source region and the drain region, wherein the body region is electrically floating, and a gate disposed over the body region and separated therefrom by a gate ... 05/04/06 - 20060091461 - Transistor structure with dual trench for optimized stress effect and method therefor A method for forming a portion of a semiconductor device structure comprises providing a semiconductor-on-insulator substrate having a semiconductor active layer, an insulation layer, and a semiconductor substrate. A first isolation trench is formed within the semiconductor active layer and a stressor material is deposited on a bottom of the ... 05/04/06 - 20060091460 - Semiconductor devices and methods of making In one method of forming a semiconductor device, a first electrode is formed electrically coupled with a semiconductor material. After the first electrode is formed, an insulator is formed over the semiconductor material adjoining the first electrode and extending a selected distance from the first electrode. After the insulator is ... 04/27/06 - 20060086981 - Power converter The power converter for solving the above-described problem has a module section and a drive section for operating the module section. The drive section has a drive circuit. The drive circuit is provided so as to correspond to the first semiconductor element which is one of the semiconductor elements comprising ... 04/27/06 - 20060086980 - Semiconductor device, sram and manufacturing method of semiconductor device A semiconductor device according to the present invention is provided with an SOI substrate, an active region, a first insulating film (complete separation insulating film), a second insulating film (partial separation insulating film), and a contact portion. Here, the active region is formed within the surface of the SOI layer. ... 04/27/06 - 20060086979 - Metal wiring, method of manufacturing the same, tft substrate having the same, method of manufacturing tft substrate and display device having the same A TFT substrate includes a transparent substrate, a scan line, a data line, a switching device and a pixel electrode. The scan line is formed on the transparent substrate. The data line is formed on the transparent substrate such that the data line is electrically insulated from the scan line. ... 04/27/06 - 20060086978 - Thin film transistor, electro-optical device and electronic apparatus A thin film transistor includes a semiconductor layer formed over a substrate, and an electrode member formed over the substrate by a liquid phase method. The electrode member includes a base layer composed of a metal material and an outer surface layer deposited on at least one surface of the ... 04/27/06 - 20060086977 - Nonplanar device with thinned lower body portion and method of fabrication A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top ... 04/27/06 - 20060086976 - Method of forming a component having dielectric sub-layers Embodiments of methods, apparatuses, devices, and/or systems for forming a component having dielectric sub-layers are described. ... 04/20/06 - 20060081932 - Semiconductor channel on insulator structure A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose ... 04/20/06 - 20060081931 - Semiconductor device and method of manufacturing the same The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second electrode being in contact with the first gate electrode and a gate ... 04/20/06 - 20060081930 - Semiconductor device, manufacturing method thereof, and memory circuit The present invention provides a semiconductor device capable of suppressing a body floating effect, and a manufacturing method thereof. A semiconductor device having an SOI structure includes a silicon substrate, a buried insulating layer formed on the silicon substrate, and a semiconductor layer formed on the buried insulating layer. The ... 04/20/06 - 20060081929 - Silicon-on-insulator substrate, fabricating method thereof, and method for fabricating floating structure using the same A silicon-on-insulator (SOI) substrate including laminated layers of a substrate, an oxide layer, and a silicon layer in order. The oxide layer has an electrifying hole fluidly connected with the substrate and the electrifying hole is filled with a part of the silicon layer. A method for fabricating the floating ... 04/20/06 - 20060081928 - Isolation spacer for thin soi devices A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa. ... 04/13/06 - 20060076623 - High mobility plane cmos soi Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. First-type transistors (e.g., NFETs) are formed on first portions of the substrate having a first type of crystalline orientation, and second-type transistors (e.g., PFETs) are formed on second portions of the substrate ... 04/13/06 - 20060076622 - Semiconductor device and method of manufacturing semiconductor device A semiconductor device including an NMOS region and a PMOS region in the same substrate, wherein the semiconductor device includes a strained Si layer which is provided on the substrate in the NMOS region and in which the surface has a plane orientation different from that of the substrate, and ... 04/06/06 - 20060071274 - Method and structure for bonded silicon-on-insulator wafer A bonded SOI wafer and a method for forming a bonded SOI wafer are provided. According to the disclosed method, a first semiconductor wafer is provided, having a first dielectric layer disposed at an outer surface of the first wafer and a plurality of dielectric filled trenches extending from the ... 03/30/06 - 20060065929 - Nitride based semiconductor device and method for manufacturing the same Provided is a nitride-based semiconductor device in which a SAW filter and a HFET are integrated on a single substrate, as well as a method for manufacturing the same. The nitride-based semiconductor device comprises a semi-insulating GaN layer formed on a substrate, a plurality of electrodes for a SAW filter ... 03/23/06 - 20060060922 - Wafer and method of producing a substrate by transfer of a layer that includes foreign species A method of producing a substrate that has a transfer crystalline layer transferred from a donor wafer onto a support. The transfer layer can include one or more foreign species to modify its properties. In the preferred embodiment an atomic species is implanted into a zone of the donor wafer ... 03/23/06 - 20060060921 - Semiconductor substrate, semiconductor device, method of manufacturing semiconductor substrate, and method of manufacturing semiconductor device A semiconductor substrate includes a first semiconductor layer that is formed on a semiconductor base substrate, a second semiconductor layer that is formed on the first semiconductor layer and that has an etching selection ratio smaller than that of the first semiconductor layer, a cavity portion that is formed below ... 03/23/06 - 20060060920 - Poly-silicon-germanium gate stack and method for forming the same A CMOS gate stack that increases the inversion capacitance compared to a conventional CMOS gate stack has been described. Using a poly-SiGe gate, instead of the conventional poly-Si gate near the gate dielectric layer, increases the amount of implanted dopant that can be activated. This increase overcomes the polysilicon depletion ... 03/23/06 - 20060060919 - Low temperature polysilicon thin film transistor and method of fabricating lightly doped drain thereof A method of fabricating a lightly doped drain region of a low temperature polysilicon thin film transistor is provided. First, a polysilicon layer is formed over a substrate, and then a gate insulation layer is formed over the polysilicon layer. A gate buffer layer and a gate are formed over ... 03/23/06 - 20060060918 - Buried biasing wells in fets A structure of a semiconductor device and method for fabricating the same is disclosed. The semiconductor structure comprises first and second source/drain regions; a channel region disposed between the first and second source/drain regions; a buried well region in physical contact with the channel region; and a buried barrier region ... 03/16/06 - 20060054973 - Method of making cavities in a semiconductor wafer The invention provides a method of making a semiconductor structure that includes a surface layer of silicon, a buried insulating layer, and a substrate. The method includes implanting atoms through at least a portion of the insulating layer; and etching the insulating layer in at least a portion of the ... 03/16/06 - 20060054972 - Component and method for producing the same A method and device are for anchoring fixed structural elements and, e.g., for anchoring electrodes for components, e.g., SOI wafer components, whose component structure is formed in a silicon layer on top of a substrate used as support. The fixed element may be mechanically connected to the substrate via at ... 03/09/06 - 20060049461 - Thin-film transistor with vertical channel region A vertical thin-film transistor (V-TFT) is provided along with a method for forming the V-TFT. The method comprises: providing a substrate made from a material such as Si, quartz, glass, or plastic; conformally depositing an insulating layer overlying the substrate; forming a gate, having sidewalls and a thickness, overlying a ... 03/09/06 - 20060049460 - Cmos logic gate fabricated on hybrid crystal orientations and method of forming thereof In preferred embodiments of the present invention, a method of forming CMOS devices using SOI and hybrid substrate orientations is described. In accordance with a preferred embodiment, a substrate may have multiple crystal orientations. One logic gate in the substrate may comprise at least one N-FET on one crystal orientation ... 03/02/06 - 20060043485 - Method for fabricating semiconductor device and semiconductor device A method for fabricating a semiconductor device according to the present invention is a method for fabricating a semiconductor device including a substrate layer including a plurality of first regions each having an active region and a plurality of second regions each being provided between adjacent ones of the first ... 03/02/06 - 20060043484 - Self-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk mosfets and for shallow junctions A method (and resulting structure) for fabricating a silicide for a semiconductor device, includes depositing a metal or an alloy thereof on a silicon substrate, reacting the metal or the alloy to form a first silicide phase, etching any unreacted metal, depositing a silicon cap layer over the first silicide ... 03/02/06 - 20060043483 - Bonding of substrates In one embodiment, a method comprises placing a first and a second substrate into a reaction chamber, the first substrate being made of an indium antimonide material and having a first surface and the second substrate being made of a silicon or a silicon dioxide material and having a second ... 02/23/06 - 20060038228 - High strain glass/glass-ceramic containing semiconductor-on-insulator structures The present invention relates to semiconductor-on-insulator structures having strained semiconductor layers. According to one embodiment of the invention, a semiconductor-on-insulator structure has a first layer including a semiconductor material, attached to a second layer including a glass or glass-ceramic, with the strain point of the glass or glass-ceramic equal to ... 02/23/06 - 20060038227 - Strained semiconductor-on-insulator structures and methods for making strained semiconductor-on-insulator structures The present invention relates to semiconductor-on-insulator structures having strained semiconductor layers. According to one embodiment of the invention, a semiconductor-on-insulator structure has a first layer including a semiconductor material, attached to a second layer including a glass or glass-ceramic, with the CTEs of the semiconductor and glass or glass-ceramic selected ... 02/16/06 - 20060033160 - Conductive layer for biaxially oriented semiconductor film growth A conductive layer for biaxially oriented semiconductor film growth and a thin film semiconductor structure such as, for example, a photodetector, a photovoltaic cell, or a light emitting diode (LED) that includes a crystallographically oriented semiconducting film disposed on the conductive layer. The thin film semiconductor structure includes: a substrate; ... 02/09/06 - 20060027867 - Sub-lithographics opening for back contact or back gate A low resistance buried back contact for SOI devices. A trench is etched in an insulating layer at minimum lithographic dimension, and sidewalls are deposited in the trench to decrease its width to sublithographic dimension. Conducting material is deposited in the trench, which serves as a low-resistance contact to the ... 02/02/06 - 20060022269 - Semiconductor substrate, semiconductor device, method for manufacturing semiconductor substrate and method for manufacturing semiconductor device A semiconductor substrate comprising: a semiconductor base; dielectric layers of mutually different film thicknesses formed on the semiconductor base; and semiconductor layers of mutually different film thicknesses formed on the dielectric layers. ... 02/02/06 - 20060022268 - Semiconductor devices including stress inducing layers A semiconductor device may include a substrate and a fin shaped semiconductor region on the substrate. The fin shaped semiconductor region may include a channel region and first and second junction regions on opposite sides of the channel region. A gate electrode may be provided on the channel region of ... 02/02/06 - 20060022267 - Semiconductor device and method of manufacturing the semiconductor device In a method of manufacturing a semiconductor device to improve structural stability of a semiconductor device in a silicidation process, a substrate is provided to have an active region defined by an isolation layer. An etching mask is formed on the active region and the isolation layer to have a ... 02/02/06 - 20060022266 - Manufacturable recessed strained rsd structure and process for advanced cmos A manufacturable way to recess silicon that employs an end point detection method for the recess etch and allows tight tolerances on the recess is described for fabricating a strained raised source/drain layer. The method includes forming a monolayer comprising oxygen and carbon on a surface of a doped semiconductor ... 01/26/06 - 20060017106 - Tft, electronic device having the tft, and flat display device having the tft The invention provides an improved thin film transistor (TFT) that can be formed at room temperature and has an improved contact resistance between an active layer and source and drain electrodes, and further provides a flat display device using such a TFT. The TFT includes an active layer including at ... 01/26/06 - 20060017105 - Semiconductor device and method of fabricating the same A gate electrode has an end extended over a part of a LOCOS oxide film, and a source electrode has an end extended further than the end of the gate electrode over a part of the LOCOS oxide film. An insulating film covering the gate electrode and the LOCOS oxide ... 01/19/06 - 20060011982 - Micro-mechanically strained semiconductor film One aspect of the present subject matter relates to a method for forming strained semiconductor film. In various embodiments, a single crystalline semiconductor film is formed on a substrate surface, and a recess is created beneath the film. A portion of the film is influenced into the void and strained. ... 01/19/06 - 20060011981 - High frequency mos transistor, method of forming the same, and method of manufacturing a semiconductor device including the same In a high frequency LDMOS transistor, a gate structure is formed on a substrate. A drain, doped with first type impurities at a first concentration, is formed on the substrate spaced apart from the gate structure. A buffer well, doped with the first type impurities at a second concentration lower ... 01/19/06 - 20060011980 - Electronic device, thin film transistor structure and flat panel display having the same The present invention provides an electronic device having more than two conductive layers that cross but not in contact with each other. At least one of the conductive layers comprises a width change part, a width of which changes in a length direction of at least one of the conductive ... 01/19/06 - 20060011979 - Substrate for semiconductor device, method of manufacturing substrate for semiconductor device, substrate for electro-optical device, electro-optical device, and electronic apparatus A substrate for a semiconductor device includes a substrate, a thin film transistor that is provided on the substrate, a wiring line that is provided above the thin film transistor, an interlayer insulating film that electrically isolates the wiring line from at least a semiconductor layer of the thin film ... 01/19/06 - 20060011978 - Semiconductor constructions and integrated circuits The invention includes a TFT-based logic circuit construction. Such construction includes a pair of first transistor devices, and a pair of second transistor devices over the first transistor devices. The first transistor devices have first active regions extending into a first semiconductive material, and the second transistor devices have second ... 01/19/06 - 20060011977 - Semiconductor device and method of fabricating the same According to the present invention, there is provided a semiconductor device comprising: a semiconductor layer formed on a semiconductor substrate via an insulating film and having a projecting shape; a gate electrode formed, via a gate insulating film, on a pair of side surfaces of four side surfaces of said ... 01/12/06 - 20060006467 - Transistor structure and circuit suitable for input/output protection of liquid crystal display device A TFT structure and a circuit configuration, which are suitable, for example, for input/output protection of a liquid crystal display device, are provided. According to an embodiment of the invention, there is provided a TFT that includes a source region, a channel region and a drain region, which are formed ... 01/12/06 - 20060006466 - Semiconductor device and method of manufacturing the same A semiconductor device comprises a support substrate, an insulation film provided on the support substrate, a rectangular silicon island provided on the insulation film, the rectangular silicon island having first side surfaces mutually opposed in a first direction and second side surfaces mutually opposed in a second direction perpendicular to ... 01/12/06 - 20060006465 - Thin film transistor and method of fabricating the same A thin film transistor and method of fabricating the same are provided. The thin film transistor is characterized in that low angle grain boundaries formed in a channel layer in a semiconductor layer pattern is tilted −15 to 15° with respect to a current flowing direction. The method includes: forming ... 01/12/06 - 20060006464 - Method and system for providing a thin film with a controlled crystal orientation using pulsed laser induced melting and nucleation-initiated crystallization Method and system for generating a metal thin film with a uniform crystalline orientation and a controlled crystalline microstructure are provided. For example, a metal layer is irradicated with a pulsed laser to completely melt the film throughout its entire thickness. The metal layer can then resolidify to form grains ... 01/12/06 - 20060006463 - Nanowire device with (111) vertical sidewalls and method of fabrication A nano-scale device and method of fabrication provide a nanowire having (111) vertical sidewalls. The nano-scale device includes a semiconductor-on-insulator substrate polished in a [110] direction, the nanowire, and an electrical contact at opposite ends of the nanowire. The method includes wet etching a semiconductor layer of the semiconductor-on-insulator substrate ... 01/05/06 - 20060001094 - Semiconductor on insulator structure An apparatus and a method for forming the apparatus include a semiconductor layer on an insulating substrate, where the substrate is a different material than the semiconductor layer, and has a coefficient of thermal expansion substantially equal to that of the semiconductor layer. The semiconductor layer can also be formed ... 01/05/06 - 20060001093 - Silicon-on insulator (soi) substrate having dual surface crystallographic orientations and method of forming same A method is provided of forming a silicon-on-insulator (SOI) substrate having at least two exposed surface crystal orientations. The method begins by providing an SOI substrate having a first silicon layer with a surface having a first crystal orientation located on a first buried oxide layer. The buried oxide layer ... 01/05/06 - 20060001092 - Thin film transistor (tft) and flat panel display including tft A Thin Film Transistor (TFT) includes: an active layer including a channel region, a source region, and a drain region; a gate electrode insulated from the active layer and adapted to supply a signal to the channel region; and a source electrode and a drain electrode, insulated from the gate ... 01/05/06 - 20060001091 - Thin film transistor (tft) and flat panel display including the tft and their methods of manufacture A Thin Film Transistor (TFT) reduces interconnection resistance of source/drain electrodes, prevents contamination from an active layer, reduces contact resistance between a pixel electrode and the source/drain electrodes, smoothly supplies hydrogen to the active layer and has high mobility, on-current characteristics, and threshold voltage characteristics The TFT includes an active ... 01/05/06 - 20060001090 - Soi substrate and method for manufacturing the same The SOI substrate 1 has a supporting substrate 10, an insulating layer 20 formed on the supporting substrate 10 and a silicon layer 30 formed on the insulating layer 20. A through electrode 40 is provided in a device formation region A1 of the SOI substrate 1. The through electrode ... 01/05/06 - 20060001089 - Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present ... 01/05/06 - 20060001088 - Strained si mosfet on tensile-strained sige-on-insulator (sgoi) A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate comprising a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer ... 12/29/05 - 20050285197 - Thin film transistor and method of fabricating the same A thin film transistor including a substrate having first and second regions, a semiconductor layer pattern formed in the first region and the second region, and a first gate insulating layer pattern formed on a channel region of the semiconductor layer pattern of the first region. A second gate insulating ... 12/29/05 - 20050285196 - Thin film transistor of liquid crystal display device and fabrication method thereof A thin film transistor serving as a switching device provided in respective pixels of an active matrix-type liquid crystal display, the thin film transistor including a source electrode overlapping the gate electrode, a first semiconductor layer and contacting one of the two parts of a second impurity semiconductor layer, and ... 12/29/05 - 20050285195 - Thin film transistor array substrate and fabricating method thereof A thin film transistor array substrate and a fabricating method thereof are disclosed. The thin film transistor array substrate protects a thin film transistor without a protective film and accordingly reduces the manufacturing cost. In the thin film transistor array substrate, a gate electrode is connected to a gate line. ... 12/29/05 - 20050285194 - Semiconductor-on-insulating (soi) field effect transistors with body contacts and methods of forming same Semiconductor-on-insulator (SOI) field effect transistors include a semiconductor substrate and a first semiconductor active region on a first portion of a surface of the substrate. A first electrically insulating layer is provided. This first electrically insulating layer extends on a second portion of the surface of the substrate and also ... 12/29/05 - 20050285193 - Semiconductor device and method of manufacturing same A semiconductor device and related method of manufacture are disclosed. The semiconductor device comprises a gate electrode formed on a semiconductor substrate, an active region containing spaces formed below the gate electrode, a channel region formed between the gate electrode and the spaces, and source and drain regions formed on ... 12/29/05 - 20050285192 - Structures and methods for manufacturing p-type mosfet withgraded embedded silicon-germanium source-drain and/or extension P-type MOSFETs (PMOSFETs) are formed by encapsulating the gate with an insulator and depositing a germanium containing layer outside the sidewalls, then diffusing the germanium into the silicon-on-insulator layer or bulk silicon by annealing or by oxidizing to form graded embedded silicon-germanium source-drain and/or Extension (geSiGe-SDE). For SOI devices, the ... 12/22/05 - 20050280090 - Method of fabricating a finfet A FinFET structure and method of forming a FinFET device. The method includes: (a) providing a semiconductor substrate, (b) forming a dielectric layer on a top surface of the substrate; (c) forming a silicon fin on a top surface of the dielectric layer; (d) forming a protective layer on at ... 12/22/05 - 20050280089 - Nrom flash memory devices on ultrathin silicon An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on ... 12/22/05 - 20050280088 - Backside body contact A back side body contact for a transistor that extends through an opening in an insulating layer located adjacent to the backside of the body. The backside contact is coupled to an interconnect on the backside. In some examples, the interconnect is coupled to an interconnect located with respect the ... 12/15/05 - 20050275024 - Soi chip with recess-resistant buried insulator and method of manufacturing the same A semiconductor-on-insulator structure includes a substrate and a buried insulator stack overlying the substrate. The buried insulator stack includes a first dielectric layer and a recess-resistant layer overlying the first dielectric layer. A second dielectric layer can overlie the recess-resistant layer. A semiconductor layer overlying the buried insulator stack. Active ... 12/15/05 - 20050275023 - Semiconductor device and method of manufacturing same A semiconductor device and a manufacturing method thereof are obtained which can restrain increase of the parasitic capacitance generated between contact plugs of source/drain regions and a gate electrode while reducing the area of the source/drain regions. A channel region is formed under a gate electrode 1. A pair of ... 12/15/05 - 20050275022 - Depletion-merged fet design in bulk silicon Field effect transistors having reduced reverse body effects and reduced parasitic junction capacitance and a method of manufacture. The FET's comprise source/drain region pairs formed in said bulk silicon, each pair separated by a channel region. The depletion region associated with each of the source/drain regions of a pair are ... 12/15/05 - 20050275021 - Semiconductor device A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions (11) are formed after a silicon layer (3) has been thinned through formation of recesses (14). Therefore n-type impurities are ... 12/15/05 - 20050275020 - Method of forming active device on substrate and the substrate There are provided the steps of forming, on a substrate 10, a semiconductor layer 12 to be a base of a device, forming each of electrodes 14 to be a source electrode and a drain electrode on a surface of the semiconductor layer 12 provided on the substrate, covering a ... 12/15/05 - 20050275019 - Thin film transistor and method of fabricating the same A thin film transistor and method of fabricating the same are provided. The thin film transistor includes: a metal catalyst layer formed on a substrate, and a first capping layer and a second capping layer pattern sequentially formed on the metal catalyst layer. The method includes: forming a first capping ... 12/15/05 - 20050275018 - Semiconductor device with multiple semiconductor layers A semiconductor device structure uses two semiconductor layers to separately optimize N and P channel transistor carrier mobility. The conduction characteristic for determining this is a combination of material type of the semiconductor, crystal plane, orientation, and strain. Hole mobility is improved in P channel transistors when the conduction characteristic ... 12/15/05 - 20050275017 - Separately strained n-channel and p-channel transistors An integrated circuit with a first plurality of transistors formed on a first wafer and second plurality of transistors formed on a second wafer. At least a substantial majority of the transistor of the first transistor are of a first conductivity type and at least a substantial majority of the ... 12/08/05 - 20050269638 - Liquid crystal display device and fabricating method thereof A base thin film transistor (TFT) substrate includes a substrate, array areas on the substrate; at least one dummy area on the substrate and between the array areas; an insulating film on the substrate; at least one aperture through the insulating film and arranged within the at least one dummy ... 12/08/05 - 20050269637 - Semiconductor device A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below ... 12/08/05 - 20050269636 - Insulated gate field-effect transistor and its manufacturing method, and imaging device and its manufacturing method An insulated gate field effect transistor, a solid-state image pickup device using the same, and manufacturing methods thereof that suppress occurrence of a shutter step and suppress occurrence of punch-through and injection. An insulated gate field effect transistor (30) having a gate electrode (32) on a semiconductor substrate (11) with ... 12/01/05 - 20050263821 - Multiple-gate mos transistor and a method of manufacturing the same Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is implemented in an elevated structure by using a ... 11/24/05 - 20050258488 - Serially connected thin film transistors and fabrication methods thereof Serially connected thin film transistor (TFT) structure include an active layer shared by an N-type TFT region and a P-type TFT region. A contact hole is formed in an N/P junction between the N-type TFT region and the P-type TFT region and conductive carriers within an N-doped region at one ... 11/24/05 - 20050258487 - Tft, method of manufacturing the tft, flat panel display having the tft, and method of manufacturing the flat panel display A thin film transistor (TFT) including a semiconductor film that may be simply patterned, a method of manufacturing the TFT, a flat panel display (FPD) including the TFT, and a method of manufacturing the FPD. The TFT includes a gate electrode, source and drain electrodes electrically insulated from the gate ... 11/24/05 - 20050258486 - Thin film transistor substrate and fabrication method thereof The present invention provides a TFT substrate that includes a plurality of TFTs each of which have a gate, a source and a drain. The plurality of the TFTs may be formed by first and second active regions formed on the substrate that each have a source region that corresponds ... 11/24/05 - 20050258485 - Silicon on insulator device and method of manufacturing the same An isolated semiconductor device and method for producing the isolated semiconductor device in which the device includes a silicon-on-insulator (SOI) device formed on a substrate. A dielectric film is formed on the insulator and covers the SOI device. The dielectric film may be a single film or a multilayer film. ... 11/17/05 - 20050253197 - Semiconductor device and method of manufacturing the same A semiconductor device comprises; a MOS transistor formed on a semiconductor layer of an SOI substrate in which the semiconductor layer is formed on a semiconductor substrate with intervention of a buried insulating film, and a contact portion for applying to the semiconductor substrate different bias voltages in an operating ... 11/17/05 - 20050253196 - Semiconductor device and manufacturing method thereof A semiconductor device comprises a support layer made of semiconductor, a diffusion layer formed by implanting impurities in a surface layer of the support layer, a buried insulating layer provided on the diffusion layer, an island-like active layer provided on the buried insulating layer, a channel region formed in the ... 11/17/05 - 20050253195 - Semiconductor device and image display device A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor including a source region, a drain region, a channel region having a predetermined channel length, a GOLD region and an LDD region having an ... 11/17/05 - 20050253194 - Soi-like structure in a bulk semiconductor substrate and method of forming same Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the ... 11/17/05 - 20050253193 - Method of fabricating a necked finfet device A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has ... 11/10/05 - 20050247978 - Solution-processed thin film transistor One exemplary embodiment of the present disclosure includes a solution-processed thin film transistor having a number of a number of conductive solution-processed thin film contacts, semiconductor solution-processed thin film active regions, and dielectric solution-processed thin film isolations formed in a sequence and organization to form a solution-processed thin film structure. ... 11/10/05 - 20050247977 - Semiconductor device and method for fabricating the same A MIS-type semiconductor device includes a p-type semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and n-type diffused source and drain layers formed in regions of the semiconductor substrate located below both sides of the gate electrode. Insides ... 11/03/05 - 20050242397 - Semiconductor device and method for manufacturing partial soi substrates There is closed a semiconductor device which comprises a semiconductor substrate including an SOI region where a first insulating film is buried, and a non-SOI region, the semiconductor substrate being provided with a boundary region formed between the SOI region and the non-SOI region and having a second insulating film ... 11/03/05 - 20050242396 - Soi structure having a sige layer interposed between the silicon and the insulator A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over ... 11/03/05 - 20050242395 - Finfet transistor device on soi and method of fabrication A FinFET transistor on SOI device and method of fabrication is provided. At least two FinFET fins each having an upper poly-silicate glass portion and a lower silicon portion are formed using spacer patterning technology. Each fin is formed on a sacrificial SiN mask layer having a sacrificial support structure. ... 11/03/05 - 20050242394 - Pattern formation substrate and method of pattern formation A pattern formation substrate comprising a substrate having thereon a hydrophobic region exhibiting repellency to liquid drops and a hydrophilic line exhibiting affinity with liquid drops. The hydrophilic line has such a surface treatment that upon landing of a liquid drop thereon, the liquid drop moves in the arrowed direction. ... 10/27/05 - 20050236671 - Multi-planar layout vertical thin-film transistor inverter A vertical thin-film transistor (V-TFT) inverter circuit and a method for forming a multi-planar layout TFT inverter circuit have been provided. The method comprising: forming a P-channel TFT with a gate, a first source/drain (S/D) region in a first horizontal plane, and a second S/D region in a second horizontal ... 10/27/05 - 20050236670 - Soi single crystalline chip structure An SOI single crystalline chip structure includes an active device layer for having at least one SOI device placed thereon, a buried oxide layer under the active device layer, a metal layer under the buried oxide layer, and a silicon substrate under the metal layer. At least one through hole ... 10/27/05 - 20050236669 - Dual-thickness active device layer soi chip structure A dual-thickness active device layer SOI chip structure is provided. The SOI chip structure has an active device layer, at least one oxide region located at a predetermined position of the active device layer and with a first predetermined depth, at least one trench surrounding the oxide region and having ... 10/27/05 - 20050236668 - Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon and soi cmos devices by gate stress engineering with sige and/or si:c Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer ... 10/20/05 - 20050230754 - Preventive treatment method for a multilayer semiconductor wafer A preventive treatment method for a multilayer semiconductor wafer is described. The semiconductor wafer includes a supporting substrate, at least one intermediate layer and a surface layer in which an intermediate layer has an exposed lateral edge and the wafer is to be subjected to a subsequent treatment. The method ... 10/20/05 - 20050230753 - Ltps tft substrate and manufacturing process thereof An LTPS TFT substrate includes an insulated substrate and a poly-silicon film formed on the insulated substrate. The poly-silicon film includes a driving circuit area and a display area. The driving circuit area includes a plurality of driving circuits. The display area includes a plurality of pixel units. The driving ... 10/20/05 - 20050230752 - Semiconductor device and manufacturing method thereof In the case of providing an LDD region for a TFT, it is necessary to form separately an insulating film to be a mask or to contrive the shape of a gate electrode layer in order to have the concentration difference in impurities injected in a semiconductor film; therefore, the ... 10/20/05 - 20050230751 - Semiconductor device A semiconductor device includes a substrate having an active layer, an element region provided in the active layer, a P-type semiconductor region provided in the element region, and first and second N-type semiconductor regions provided in the element region, located on the sides of the P-type semiconductor region, respectively and ... 10/13/05 - 20050224881 - Methods of making semiconductor-on-insulator thin film transistor constructions The invention includes SOI thin film transistor constructions, memory devices, computer systems, and methods of forming various structures, devices and systems. The structures typically comprise a thin crystalline layer of silicon/germanium formed over a wide range of suitable substrates. The crystalline properties of the silicon/germanium can be controlled during formation ... 10/13/05 - 20050224880 - Multi-gate mos transistor and method of manufacturing the same Provided are a multi-gate MOS transistor and a method of manufacturing the same. Two silicon fins are vertically stacked on a silicon on insulator (SOI) substrate, and four side surfaces of an upper silicon fin and three side surfaces of a lower silicon fin are used as a channel. Therefore, ... 10/13/05 - 20050224879 - Semiconductor on insulator substrate and devices formed therefrom A semiconductor on insulator (SOI) device is comprised of a layer of a dielectric material having a perovskite lattice, such as a rare earth scandate. The dielectric material is selected to have an effective lattice constant that enables growth of semiconductor material having a diamond lattice directly on the dielectric. ... 10/13/05 - 20050224878 - Memory with split gate devices and method of fabrication A DRAM fabricated on an SOI substrate employing single body devices as memory cells without relying on a field through the insulative layer of the SOI is described. Floating body devices are defined by orthogonally disposed lines with both a front gate and back gate for each body being formed ... 10/13/05 - 20050224877 - Connection structure for soi devices A semiconductor contact connection structure and the method for forming the same are disclosed. The connection structure has a first semiconductor device formed on an insulator substrate. A non-conducting gate interconnect layer is formed on the insulator substrate for connecting to a gate of a second semiconductor device, and a ... 10/13/05 - 20050224876 - [structure of ltps-tft and method of fabricating channel layer thereof] A LTPS-TFT structure comprising a cap layer, a polysilicon film and a gate is provided. The cap layer is disposed over the substrate with a gap between the two. The polysilicon film is disposed over the cap layer and is divided into a channel region and a source/drain region on ... 10/13/05 - 20050224875 - High mobility plane cmos soi Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. First-type transistors (e.g., NFETs) are formed on first portions of the substrate having a first type of crystalline orientation, and second-type transistors (e.g., PFETs) are formed on second portions of the substrate ... 10/06/05 - 20050218452 - Display device A display device according to the present invention includes: a planarization layer for insulating between a gate electrode etc. and a data wiring, a drain electrode, or the like of the transistor; and a barrier layer that is formed on an upper surface or lower surface of the planarization layer ... 10/06/05 - 20050218451 - Semiconductor device incorporating semiconductor constructing body and method of fabricating the same A semiconductor device includes metal foil to which a ground potential is applied, at a semiconductor constructing body provided on the metal foil and having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate. An insulating layer is provided around the semiconductor constructing body ... 10/06/05 - 20050218450 - Thin-film field-effect transistors and making method In a thin-film field-effect transistor having a MIS structure, the insulator layer is formed of cyanoethylated dihydroxypropyl pullulan. The TFT is prepared by applying a cyanoethylated dihydroxypropyl pullulan solution onto a gate electrode in the form of a metal layer, drying the applied solution to form an insulator layer, and ... 09/29/05 - 20050212047 - Thin film transistor substrate and manufacturing method thereof A thin film transistor substrate includes a transparent insulating substrate, a first thin film transistor that is formed on the transparent insulating substrate, and a second thin film transistor that is formed on the transparent insulating substrate. The second thin film transistor has a characteristic that differs from that of ... 09/29/05 - 20050212046 - Light emitting device and method of manufacturing the same To provide a light emitting device capable of promoting an efficiency of taking out light to outside and achieving highly reliable bright image display by lower power consumption, in a light emitting device including a plurality of pixels and including a transistor and a pixel electrode electrically connected to the ... 09/29/05 - 20050212045 - Photo-detecting device A photo-detecting device that enables a solid-state image sensor to meet the requirement of higher quality imaging including: a first silicon substrate 120 having p- and n-type regions; a first SOI substrate 130 in which a second silicon substrate 132 having p- and n-type regions is formed on a first ... 09/29/05 - 20050212044 - Inspection method and inspection apparatus There is established an easier inspection method with which it is not required to set up probes on wires. Also, there is provided an inspection apparatus using this inspection method. With the inspection apparatus or inspection method, primary coils of an inspection substrate and secondary coils of a device substrate ... 09/22/05 - 20050205936 - Semiconductor device incorporating a defect controlled strained channel structure and method of making the same A semiconductor device includes a single crystal substrate and a dielectric layer overlying the substrate. The dielectric layer includes at least one opening having a first portion and an overlying second portion. The first portion has a depth and width, such that an aspect ratio of the depth to width ... 09/22/05 - 20050205935 - Manufacturing method for soi semiconductor device, and soi semiconductor device A manufacturing method for an SOI semiconductor device includes creating transistors and an element isolation region on a semiconductor layer in an SOI substrate. The method also includes covering the transistors and the element isolation region with a first insulation film. The method also includes creating a first opening section ... 09/22/05 - 20050205934 - Strained germanium-on-insulator device structures The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. ... 09/22/05 - 20050205933 - Intermediate semiconductor device having activated oxide-based layer for electroless plating An intermediate semiconductor device that includes a semiconductor substrate and an oxide-based layer over the substrate. The oxide-based layer has an activated catalytic surface on at least one selected area thereof which is adapted for electroless plating. The intermediate may also include high aspect ratio capacitor containers, trenches, vias, and ... 09/22/05 - 20050205932 - Strained-channel fin field effect transistor (fet) with a uniform channel thickness and separate gates A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric formed between the first ... 09/22/05 - 20050205931 - Soi cmos device with reduced dibl CMOS devices formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant through openings in a masking layer and through channel regions of the p- and n-wells, into ... 09/22/05 - 20050205930 - Silicon-on-insulator active pixel sensors Active pixel sensors are defined on double silicon on insulator (SOI) substrates such that a first silicon layer is selected to define radiation detection regions, and a second silicon layer is selected to define readout circuitry. The first and second silicon layers are separated by an insulator layer, typically an ... 09/22/05 - 20050205929 - Semiconductor substrate, manufacturing method therefor, and semiconductor device A semiconductor substrate and a manufacturing method therefore, and a semiconductor device using the semiconductor substrate comprise a strained Si region and unstrained Si region formed at substantially the same level. In an aspect of the invention, a semiconductor substrate is provided by comprising a support substrate, a first semiconductor ... 09/15/05 - 20050199954 - Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. ... 09/08/05 - 20050194641 - Thin film transistor and method for manufacturing the same A simplified method for forming a TFT includes four photolithographic processes. A first photolithographic process is used for forming a gate electrode (42). A second photolithographic process is used for forming a source electrode (742), a drain electrode (741), a channel layer (82), a source ohmic contact layer (832), and ... 09/08/05 - 20050194640 - Organic thin-film transistor The present invention relates to organic thin-film transistors using an organic compound in the semiconductor layer thereof. The organic semiconductor layer is made by means of Cascade Crystallization Process. Said layer is characterized by a globally ordered crystalline structure with intermolecular spacing of 3.4±0.3 Å in the direction of one ... 09/01/05 - 20050189592 - Semiconductor device and method of manufacturing the same When a crystalline semiconductor thin film formed by using a catalytic element for facilitating crystallization is subjected to a heat treatment in an atmosphere containing a halogen element at a temperature exceeding 700° C., a crystal structure in which crystal grain boundaries do not substantially exist can be obtained. In ... 09/01/05 - 20050189591 - Active manipulation of light in a silicon-on-insulator (soi) structure An arrangement for actively controlling, in two dimensions, the manipulation of light within an SOI-based optical structure utilizes doped regions formed within the SOI layer and a polysilicon layer of a silicon-insulator-silicon capacitive (SISCAP) structure. The regions are oppositely doped so as to form an active device, where the application ... 09/01/05 - 20050189590 - Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device includes a step of forming a device region 5 that is separated by a device-separation insulating film 4 formed in a part of an SOI layer, a step of forming a gate insulating film 6a on a device region 5 so that the ... 09/01/05 - 20050189589 - Hybrid soi/bulk semiconductor transistors Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater ... 08/25/05 - 20050184341 - Biased, triple-well fully depleted soi structure In one illustrative embodiment, the device comprises a transistor formed above a silicon-on-insulator substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the bulk. substrate being doped with a first type of dopant material and a first well formed in the bulk substrate, the first ... 08/25/05 - 20050184340 - Transistor and logic circuit on thin silicon-on-insulator wafers based on gate induced drain leakage currents A transistor structure fabricated on thin SOI is disclosed. The transistor on thin SOI has gated n+ and p+ junctions, which serve as switches turning on and off GIDL current on the surface of the junction. GIDL current will flow into the floating body and clamp its potential and can ... 08/18/05 - 20050179086 - Structures with seeded single-crystal domains Single-crystal devices and a method for forming semiconductor film single-crystal domains are provided. The method comprises: forming a substrate, such as glass or Si; forming an insulator film overlying the substrate; forming a single-crystal seed overlying the substrate and insulator; forming an amorphous film overlying the seed; annealing the amorphous ... 08/11/05 - 20050173764 - Self-aligned body tie for a partially depletion soi device structure A silicon-on-insulator (SOI) device structure 100 formed using a self-aligned body tie (SABT) process. The SABT process connects the silicon body of a partially depleted (PD) structure to a bias terminal. In addition, the SABT process creates a self-aligned area of silicon around the edge of the active areas, as ... 08/11/05 - 20050173763 - Semiconductor device A semiconductor device includes a glass substrate having a main surface, a polysilicon film formed on the main surface, having a channel region formed and having a source region and a drain region formed on opposing sides of the channel region, a gate insulating film provided so as to be ... 08/11/05 - 20050173762 - Thin film transistor, liquid crystal display using thin film transistor, and method of manufacturing thin film transistor A semiconductor film, which is located over a gate electrode for forming a channel region between a source electrode and a drain electrode, has a width greater than a width of the source electrode and a width of the drain electrode located over the gate electrode. Irregularities are formed in ... 08/11/05 - 20050173761 - Semiconductor device and method for fabricating the same A semiconductor device includes a substrate with an insulating surface and a single crystal semiconductor layer, which is bonded to the insulating surface of the substrate. The device further includes a first insulating layer, which is provided between the insulating surface of the substrate and the single crystal semiconductor layer, ... 08/04/05 - 20050167752 - Electronic apparatuses, silicon-on-insulator integrated circuits, and fabrication methods An electronic apparatus includes an insulative substrate containing an aluminum-based glass and a layer containing a semiconductive material over the substrate. The insulative substrate can include aluminum oxycarbide. The insulative substrate can exhibit a CTE sufficiently close to a CTE of the semiconductive material layer such that a strain of ... 08/04/05 - 20050167751 - Semiconductor memory device for storing data as state of majority carriers accumulated in channel body and method of manufacturing the same A semiconductor memory device comprises a substrate; a semiconductor layer of a first conductive type isolated from the substrate by an insulator layer; a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in the semiconductor layer, and a channel body ... 08/04/05 - 20050167750 - Methods and structures for planar and multiple-gate transistors formed on soi A semiconductor device includes an insulator layer, a semiconductor layer, a first transistor, and a second transistor. The semiconductor layer is overlying the insulator layer. A first portion of the semiconductor layer has a first thickness. A second portion of the semiconductor layer has a second thickness. The second thickness ... 07/28/05 - 20050161742 - Semiconductor device and semiconductor device production system It is a problem to provide a semiconductor device production system using a laser crystallization method capable of preventing grain boundaries from forming in a TFT channel region and further preventing conspicuous lowering in TFT mobility due to grain boundaries, on-current decrease or off-current increase. An insulation film is formed ... 07/28/05 - 20050161741 - Buried transistors for silicon on insulator technology A buried transistor particularly suitable for SOI technology, where the transistor is fabricated within a trench in a substrate and the resulting transistor incorporates completely isolated active areas. The resulting substrate has a decreased topography and there is no need for polysilicon (or other) plugs to connect to the transistor, ... 07/28/05 - 20050161740 - Dual panel-type organic electroluminescent device and method for fabricating the same A dual panel-type active matrix organic electroluminescent device includes: first and second substrates spaced apart from each other; a driving thin film transistor on an inner surface of the first substrate; a connection electrode layer connected to the driving thin film transistor and formed of a first conductive material having ... 07/28/05 - 20050161739 - Method and structure to create multiple device widths in finfet technology in both bulk and soi Disclosed is a structure and method for producing a fin-type field effect transistor (FinFET) that has a buried oxide layer over a substrate, at least one first fin structure and at least one second fin structure positioned on the buried oxide layer. First spacers are adjacent the first fin structure ... 07/28/05 - 20050161738 - Thin film transistor, circuit device and liquid crystal display A thin film transistor includes a one conductive type semiconductor layer; a source region and a drain region which are separately provided in the semiconductor layer; and a gate electrode provided above or below the semiconductor layer with an insulating film interposed therebetween, wherein the width of the junction face ... 07/21/05 - 20050156247 - Device and method for protecting gate terminal and lead A resist region covering the gate terminal and lead of the gate electrode line and between a passivation layer and a gate insulating layer is used to protect the gate terminal and lead. The resist region is located at a scribing line on margin of the color filter substrate of ... 07/21/05 - 20050156246 - Methods of forming strained-semiconductor-on-insulator device structures The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. ... 07/21/05 - 20050156245 - Semiconductor device formed in semiconductor layer arranged on substrate with one of insulating film and cavity interposed between the substrate and the semiconductor layer A semiconductor device according to an aspect of the present invention comprises a first semiconductor layer and a plurality of second semiconductor layers. The first semiconductor layer is formed in a first region of a semiconductor substrate with one of an insulating film and a cavity interposed between the semiconductor ... 07/21/05 - 20050156244 - Thin film apparatus, a manufacturing method of the thin film apparatus, an active matrix substrate, a manufacturing method of the active matrix substrate, and an electro-optical apparatus having the active matrix substrate A manufacturing method of a thin film apparatus, includes: a first step for forming a separation layer on a heat resistant substrate; a second step for forming a thin film device on the separation layer; a third step for providing a surface layer on the thin film device; and a ... 07/21/05 - 20050156243 - Thin film transistors and methods of forming thin film transistors A method of forming a thin film transistor over a substrate is provided whereby at least one of the source region or the drain region is conductively doped while preventing conductivity doping of the channel region without any masking of the channel region occurring by any separate masking layer. A ... 07/21/05 - 20050156242 - Semiconductor device, method of manufacturing same and method of designing same A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) ... 07/21/05 - 20050156241 - Pressure sensor A pressure sensor includes a silicon-on-insulator (SOI) substrate, a glass substrate bonded to the SOI substrate by anode bonding, a silicon island formed on a part of a silicon layer of the SOI substrate and surrounded by a groove extending to an insulating layer of the SOI substrate, a through ... 07/21/05 - 20050156240 - Thin film transistors and semiconductor constructions A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer ... 07/21/05 - 20050156239 - Method for forming pattern of stacked film and thin film transistor A method for forming a pattern of a stacked film, includes steps (a) to (e). The step (a) is forming sequentially a first base insulating film and a light shielding material on a transparent substrate. The step (b) is patterning the light shielding material to obtain a light shielding film ... 07/21/05 - 20050156238 - Silicide gate transistors and method of manufacture A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried ... 07/14/05 - 20050151197 - Production method of flexible electronic device A flexible electronic device excellent in heat liberation characteristics and toughness and a production method for actualizing thereof in low cost and with satisfactory reproducibility are provided. A protection film is adhered onto the surface of a substrate on which surface a thin film device is formed. Successively, the substrate ... 07/14/05 - 20050151196 - Polysilicon thin film transistor array panel and manufacturing method thereof A method of manufacturing a thin film transistor array panel is provided, which includes: depositing an amorphous silicon layer on an insulating substrate; converting the amorphous silicon layer to a polysilicon layer by a plurality of laser shots using a mask; forming a gate insulating layer on the polysilicon layer; ... 07/14/05 - 20050151195 - Method of manufacturing a thin film transistor, thin film transistor, thin film transistor circuit, electronic device, and electronic apparatus Aspects of the invention can provide a method of manufacturing a thin film transistor capable of manufacturing a high-performance thin film transistor with a simple process, a thin film transistor manufactured using the method of manufacturing a thin film transistor, and a thin film transistor circuit, an electronic device, and ... 07/14/05 - 20050151194 - Method of forming thin-film transistor devices with electro-static discharge protection A silicon layer is formed on a substrate, and then the silicon layer is patterned, and source regions, drain regions and connectors, all with the same conductivity, are formed. The source regions are connected with the drain regions electrically by the connectors, and short circuits are thus constructed. Then, subsequent ... 07/14/05 - 20050151193 - Discriminative soi with oxide holes underneath dc source/drain A selective SOI structure having body contacts for all the devices while excluding the buried oxide that is directly underneath diffusions of DC nodes such as applied voltage Vdd, ground GND, reference voltage Vref, and other like DC nodes is provided. The selective SOI structure of the present invention can ... 07/14/05 - 20050151192 - Reduction of chemical mechanical planarization (cmp) scratches with sacrificial dielectric polish stop Disclosed in a method of planarizing a silicon on insulator (SOI) structure. The invention performs a first chemical mechanical planarization (CMP) process on an insulator (e.g., oxide) layer. However, this first CMP process creates scratches on the insulator layer. The invention forms a polish stop insulator (e.g., nitride) over the ... 07/07/05 - 20050145940 - Semiconductor device and method of manufacturing same There is provided a semiconductor device which is formed on a semiconductor substrate and allows effective use of the feature of the semiconductor substrate, and there is also provided a method of manufacturing the same. An N-channel MOS transistor including a P-type body layer (3a), and a P-type active layer ... 07/07/05 - 20050145939 - Thin film forming apparatus When a solution sprayed by a spray nozzle portion reaches one surface portion of a substrate, a thin film forming material contained the solution decomposes thermally because the substrate is heated to a prescribed temperature, and a thin film is formed on the one surface portion of the substrate. An ... 07/07/05 - 20050145938 - Soi mosfet with multi-sided source/drain silicide A microelectronic device including an insulator located over a substrate, a semiconductor feature and a contact layer. The semiconductor feature has a thickness over the insulator, a first surface opposite the insulator, and a sidewall spanning at least a portion of the thickness. The contact layer has a first member ... 07/07/05 - 20050145937 - Sti liner for soi structure In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer ... 06/30/05 - 20050139924 - Poly crystalline silicon semiconductor device and method of fabricating the same Provided are a poly crystalline silicon semiconductor device and a method of fabricating the same. Portions of a silicon layer except for gates are removed to reduce a parasitic capacitance caused from the silicon layer existing on gate bus lines. The silicon layer exists under the gates only, thus the ... 06/30/05 - 20050139923 - Semiconductor device with modified mobility and thin film transistor having the same Provided are a semiconductor device including an active area which is defined as high and low mobility areas and a thin film transistor having the semiconductor device. The mobility of the active area can be lowered to a level enough to satisfy the requirement of the semiconductor device. The lowering ... 06/30/05 - 20050139922 - Liquid crystal display device and manufacturing method thereof A manufacturing method of a liquid crystal display device is provided. The method includes forming a gate line and a data line on a substrate; forming a thin film transistor connected to the gate and data lines, the thin film transistor including a gate electrode, a semiconductor layer, a source ... 06/30/05 - 20050139921 - Nmos device, pmos device, and sige hbt device formed on soi substrate and method of fabricating the same Provided are an NMOS device, a PMOS device and a SiGe HBT device which are implemented on an SOI substrate and a method of fabricating the same. In manufacturing a Si-based high speed device, a SiGe HBT and a CMOS are mounted on a single SOI substrate. In particular, a ... 06/30/05 - 20050139920 - Semiconductor device, method of manufacturing a semiconductor device, electroluminescence device, and method of manufacturing an electroluminescence device A semiconductor device is provided. The semiconductor device includes an element; a mounting board; and a single film made of a conductive material directly coupling the element with the mounting board. ... 06/30/05 - 20050139919 - Method of forming a polysilicon film, thin film transistor including a polysilicon film and method of manufacturing the same In a method of forming a polysilicon film, a thin film transistor including a polysilicon film, and a method of manufacturing a thin film transistor including a polysilicon film, the thin film transistor includes a substrate, a first heat conduction film on the substrate, a second heat conduction film adjacent ... 06/30/05 - 20050139918 - Polycrystalline liquid crystal display device having large width channel and method of fabricating the same A polysilicon liquid crystal display (LCD) device having a large width channel includes a buffer layer formed on a substrate, an active layer formed on the buffer layer and having a plurality of heat releasing parts, a gate line formed in a width direction of the active layer, at least ... 06/30/05 - 20050139917 - Semiconductor device A semiconductor device has an anode impurity region and a cathode impurity region on a semiconductor substrate with a SOI (Silicon-On-Insulator) structure. An impurity region for voltage control is formed between the anode impurity region and the cathode impurity region. ... 06/23/05 - 20050133865 - Member which includes porous silicon region, and method of manufacturing member which contains silicon A technique capable of forming a high-quality nonporous layer with little defects is provided. When an average pore size and pore density are defined as D (nm) and N (pores/cm2), respectively, a silicon wafer is anodized to satisfy 0<N≦1.9×1012 and 0.235 nm≦D<91 nm to form a porous silicon region in ... 06/23/05 - 20050133864 - Semiconductor device and method of manufacturing the same Plural trench isolation films (4) are provided with portions of an SOI layer (3) interposed therebetween in a surface of the SOI layer (3) in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive element (30) are formed on the trench isolation films (4), respectively. ... 06/16/05 - 20050127443 - Semiconductor device and method for preparing the same A semiconductor device and a method for preparing the same that can solve crack of a semiconductor film, capacitance electrodes and the like due to stress when forming a source electrode and a drain electrode in a semiconductor device having a thin film transistor and a holding capacitance with three ... 06/16/05 - 20050127442 - Method and apparatus for forming an soi body-contacted transistor A method for forming a silicon-on-insulator transistor (80) includes forming an active region (82) overlying an insulating layer (122), wherein a portion of the active region provides an intrinsic body region (126). A body tie access region (128) is also formed within the active region, overlying the insulating layer and ... 06/16/05 - 20050127441 - Body contact layout for semiconductor-on-insulator devices A method and structure is provided for an improved body contact layout for semiconductor-on-insulator (SOI) devices. In one embodiment, an insulated gate field effect transistor and method for fabrication of such a transistor is provided. The insulated gate field effect transistor includes a source, a drain, and a channel formed ... 06/09/05 - 20050121722 - Semiconductor device having patterned soi structure and method for fabricating the same A method for fabricating a semiconductor device, including forming a first insulation film, a first semiconductor layer, and a second insulation film in sequence in first to third regions of a semiconductor substrate, removing the first insulation film, the first semiconductor layer, and the second insulation film in the first ... 06/09/05 - 20050121721 - Insulated-gate field-effect thin film transistors A new Insulated-Gate Field-Effect Thin Film Transistor (Gated-FET) is disclosed. A semiconductor thin film Gated-FET device, comprising: a lightly doped resistive channel region formed on a semiconductor thin film layer, the thickness of the channel comprising the entire thin film thickness; and an insulator layer deposited on said channel surface ... 06/02/05 - 20050116292 - Thin film transistor using a metal induced crystallization process and method for fabricating the same and active matrix flat panel display using the thin film transistor Provided is a thin film transistor that may be manufactured using Metal Induced Crystallization (MIC) and method for fabricating the same. Also provided is an active matrix flat panel display using the thin film transistor, which may be created by forming a crystallization inducing metal layer below a buffer layer ... 06/02/05 - 20050116291 - Organic electroluminescence display device and method for fabricating the same The present invention relates to a thin film transistor for easily displaying gradation of an organic electroluminescence display device and a fabrication method of the thin film transistor, and an organic electroluminescence display device using the thin film transistor. The present invention provides an organic electroluminescence display device comprising a ... 06/02/05 - 20050116290 - Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers A method utilizing localized amorphization and recrystallization of stacked template layers is provided for making a planar substrate having semiconductor layers of different crystallographic orientations. Also provided are hybrid-orientation semiconductor substrate structures built with the methods of the invention, as well as such structures integrated with various CMOS circuits comprising ... 06/02/05 - 20050116289 - Ultra-thin si channel mosfet using a self-aligned oxygen implant and damascene technique The present invention provides a thin channel MOSFET having low external resistance. In broad terms, a silicon-on-insulator structure comprising a SOI layer located atop a buried insulating layer, said SOI layer having a channel region which is thinned by the presence of an underlying localized oxide region that is located ... ### FreshPatents.com Support |