Single Crystal Semiconductor Layer On Insulating Substrate (soi)

Single Crystal Semiconductor Layer On Insulating Substrate (soi) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

01/24/08 - 20080017924 - Semiconductor device and method of manufacturing the same
A semiconductor device having an SOI structure including a semiconductor substrate, a buried insulating layer and an SOI layer, including first and second semiconductor regions of a predetermined conductivity type provided in an element formation region of said SOI layer, and a partial insulating film provided in an upper layer ...

01/17/08 - 20080012076 - Display device, method for manufacturing thereof, and television device
The invention provides a display device and a method for manufacturing thereof by increasing a material efficiently as well as simplifying steps. Also, the invention provides a technique for forming a pattern such as a wiring, that is used for forming a display device, to have a predetermined shape with ...

01/17/08 - 20080012074 - Low temperature sol-gel silicates as dielectrics or planarization layers for thin film transistors
Traditionally, sol-gel silicates have been reported as being high temperature processable at 400 C to give reasonably dense films that showed good leakage current densities (<5×10−8 A/cm2). Recently we have discovered that we are able to prepare films from particular combinations of sol-gel silicate precursors that cure at 135° C. ...

01/10/08 - 20080006877 - Method of forming a solution processed device
Embodiments of methods, apparatuses, devices, and/or systems for forming a solution processed device are described. ...

01/03/08 - 20080001225 - Microelectronic structure by selective deposition
A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the ...

12/27/07 - 20070296032 - Artificial dielectrics using nanostructures
Artificial dielectrics using nanostructures, such as nanowires, are disclosed. In embodiments, artificial dielectrics using other nanostructures, such as nanorods, nanotubes or nanoribbons and the like are disclosed. The artificial dielectric includes a dielectric material with a plurality of nanowires (or other nanostructures) embedded within the dielectric material. Very high dielectric ...

12/06/07 - 20070278578 - Memory cell array, method of producing the same, and semiconductor memory device using the same
A memory cell array includes isolated semiconductor regions formed on a supporting insulating substrate, memory cells formed in the respective semiconductor regions, and insulating regions formed so as to insulate the memory cells. Each memory cell formed in a semiconductor region includes a source region, a drain region, a front ...

12/06/07 - 20070278577 - Semiconductor device and manufacturing method of the same
To reduce the adverse affect that characteristics of end portions of a channel forming region of a semiconductor film have on characteristics of a transistor. A gate electrode is formed over a channel forming region of a semiconductor film over a substrate, with a gate insulating film interposed therebetween. The ...

12/06/07 - 20070278575 - Transistor and fabrication process
Process for fabricating a transistor, in which an electron-sensitive resist layer lying between at least two semiconductor fingers is formed and said resist lying between at least two wires is converted into a dielectric. For example, in one embodiment of the present disclosure an integrated circuit includes a transistor having ...

11/22/07 - 20070267699 - Transistor including a deposited channel region having a doped portion
A transistor having a gate electrode, a source electrode, a drain electrode, a dielectric material and a channel region disposed between the source electrode and drain electrode. The channel region includes a portion doped with an impurity to change the fixed charge density within the portion relative to a remainder ...

11/22/07 - 20070267698 - Dual wired integrated circuit chips
A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side ...

11/22/07 - 20070267696 - Mobile transforming plug
A mobile transforming plug includes an insulating main body, a shell cover, a linking element and a linker. At the front side of the insulating main body, a connecting part is formed. A carrying part is formed at the rear side of the insulating main body. There is a connection ...

11/15/07 - 20070262379 - Metal structure of glass substrate and formation thereof
Aluminum gate electrode parasitic resistance and capacitance delay suffers performance, and even makes the signal loss to high-resolution and small-size requests for thin film transistor liquid crystal display. An important technology employed in manufacturing thin film transistor is to convert surface of glass substrate into a silicon nitride layer, and ...

11/15/07 - 20070262378 - Technique for stable processing of thin/fragile substrates
A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second ...

11/08/07 - 20070257313 - Semiconductor memory device including an soi substrate
A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain ...

11/08/07 - 20070257312 - Semiconductor-on-insulator (soi) substrates and semiconductor devices using void spaces
An SOI substrate is fabricated by providing a substrate having a sacrificial layer thereon, an active semiconductor layer on the sacrificial layer remote from the substrate and a supporting layer that extends along at least two sides of the active semiconductor layer and the sacrificial layer and onto the substrate, ...

11/08/07 - 20070257311 - Semiconductor device and method for manufacturing the same
The present invention provides a method for manufacturing massively and efficiently a minute device which can receive or send data in contact, preferably, out of contact by forming an integrated circuit which is formed by a thin film over a large glass substrate and by peeling the integrated circuit from ...

11/08/07 - 20070257310 - Body-tied mosfet device with strained active area
A body-tied MOSFET device and method of fabrication are presented. In the method of fabrication, oxygen diffuses and reacts down a first axis of a pFET or nFET. This results in a partial oxidation of a buried-oxide/silicon island interface. The partial oxidation produces a thickness variation in the silicon island ...

11/01/07 - 20070252210 - Semiconductor element, semiconductor device and methods for manufacturing thereof
The present invention provides a method of manufacturing a semiconductor element having a miniaturized structure and a semiconductor device in which the semiconductor element having a miniaturized structure is integrated highly, by overcoming reduction of the yield caused by alignment accuracy, accuracy of a processing technique by reduced projection exposure, ...

11/01/07 - 20070252206 - Semiconductor thin film and method of manufacturing the same and semiconductor device and method of manufacturing the same
A thin film semiconductor transistor structure has a substrate with a dielectric surface, and an active layer made of a semiconductor thin film exhibiting a crystallinity as equivalent to the single-crystalline. To fabricate the transistor, the semiconductor thin film is formed on the substrate, which film includes a mixture of ...

10/25/07 - 20070246774 - Semiconductor device with substantial driving current and decreased junction leakage current
The semiconductor device includes an active region, a stepped recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The stepped recess channel region is formed in the active region. ...

10/18/07 - 20070241399 - Semiconductor device and method of fabricating the same
In a semiconductor device including a multi-gate MIS transistor having a channel on a plurality of surfaces, a gate electrode is formed on a gate insulating film on side surfaces of an island-like semiconductor layer formed along a given direction on an insulating film, and source/drain electrodes are formed in ...

10/18/07 - 20070241398 - Error detection and correction in semiconductor structures
A semiconductor structure and a method for operating the same. The semiconductor structure includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is on top of and bonded to the second semiconductor chip. The first and second semiconductor chips include a first and a second ...

10/11/07 - 20070235804 - Soi lateral semiconductor device and method of manufacturing the same
The SOI lateral semiconductor device includes a semiconductor region of a first conductivity type, a buried oxide film layer in the semiconductor region, a thin active layer on the buried oxide film layer, an anode region in the thin active layer, and a drain layer contacting the buried oxide film ...

10/04/07 - 20070228469 - Thin-film transistor formed on insulating substrate
There is provided a thin-film transistor that is formed on an insulating substrate, is capable of a high-speed operation, has small non-uniformity among devices, is hardly susceptible to device destruction due to high voltage, and is free from the effect of a parasitic transistor that forms at an edge part ...

10/04/07 - 20070228466 - Pixel structure, thin film transistor array substrate and liquid crystal display panel
A pixel structure, suitable being driven by a scan line and a data line on a substrate, is provided. The pixel structure includes a thin film transistor (TFT) and a pixel electrode. Wherein, the TFT includes a gate, a first and a second dielectric layer, a semiconductor layer, a source, ...

10/04/07 - 20070228465 - Improved soi substrate and soi device, and method for forming the same
An improved semiconductor-on-insulator (SOI) substrate is provided, which has a substantially planar upper surface and comprises at least first and second patterned buried insulator layers. Specifically, the first patterned buried insulator layer has a first thickness and is located in the SOI substrate at a first depth from the substantially ...

09/27/07 - 20070221991 - Semiconductor device with increased channel area and decreased leakage current
The semiconductor device includes an active region, a recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess channel region is formed in the active region. The vertical ...

09/27/07 - 20070221990 - Grounding front-end-of-line structures on a soi substrate
Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including ...

09/20/07 - 20070215945 - Light control device and display
Provided is a light control device including: a thin film transistor; and a light control element including an electrode electrically connected to the thin film transistor, in which a semiconductor region of the thin film transistor and an pixel electrode are composed of the same semiconductor layer, and the same ...

09/20/07 - 20070215941 - Semiconductor-on-insulator substrate comprising a buried diamond-like carbon layer and method for making same
The substrate successively comprises a base, a diamond-like carbon layer, a dielectric layer and a semi-conducting material layers which is designed to constitute microelectronic elements. A nucleation layer is preferably disposed between the base and the diamond-like carbon layer. The dielectric material is chosen such that the upper level of ...

09/13/07 - 20070210382 - Semiconductor device and method of manufacturing the same
Provided is a semiconductor device formed to an SOI substrate including a MOS transistor in which a parasitic MOS transistor is suppressed. The semiconductor device formed on the SOI substrate by employing a LOCOS process is structured such that a part of a a polysilicon layer to becomes a gate ...

09/13/07 - 20070210381 - Electronic device and a process for forming the electronic device
An electronic device can have an insulating layer lying between a first semiconductor layer and a base layer. A second semiconductor layer, having a different composition and stress as compared to the first semiconductor layer, can overlie at least a portion of the first semiconductor layer. In one embodiment, a ...

09/13/07 - 20070210380 - Body connection structure for soi mos transistor
A body connection structure for a SOI MOS transistor is described, including a first and a second control transistors. The first control transistor includes a gate electrically connecting with the gate of the SOI MOS transistor, a first S/D region electrically connecting with the first S/D region of the SOI ...

09/06/07 - 20070205463 - Semiconductor-on-insulator silicon wafer
A method of fabricating a semiconductor-on-insulator semiconductor wafer is described that includes providing first and second semiconductor substrates. A first insulating layer is formed on the first substrate with a first predetermined stress and a second insulating layer is formed on the second substrate with a second predetermined stress different ...

08/30/07 - 20070200177 - Semiconductor laser device and semiconductor laser device manufacturing method
A semiconductor laser device comprising: an active layer, a semiconductor layer formed on the active layer and having a wurtzite structure, wherein a principal surface of the active layer is substantially perpendicular to a (0001) surface of the semiconductor layer, a current path portion in the semiconductor layer extends along ...

08/30/07 - 20070200175 - Functional device and method of manufacturing it
A functional device which is composed of a nanometer-sized functional structure, which can reduce connection resistance in connecting the functional structure to an external electrode, and which includes a wiring section capable of minimizing constraints given to structural designs of various functional structures, and a method of manufacturing it are ...

08/30/07 - 20070200174 - Soi substrate, mask blank for charged particle beam exposure, and mask for charged particle beam exposure
The invention provides an SOI substrate 10 comprising on one major surface of a silicon single crystal 13 a silicon thin-film layer 11 via a buried silicon oxide film 12, characterized in that a substrate warp preventive layer 14 is provided on another major surface of the silicon single crystal ...

08/30/07 - 20070200173 - Embedded substrate interconnect for underside contact to source and drain regions
A semiconductor topography (10) is provided which includes a semiconductor-on-insulator (SOI) substrate having a conductive line (16) arranged within an insulating layer (22) of the SOI substrate. A method for forming an SOI substrate with such a configuration includes forming a first conductive line (16) within an insulating layer (22) ...

08/30/07 - 20070200172 - Thin film power mos transistor, apparatus, and method
A thin film power transistor includes a plurality of first doped regions over a substrate and a second doped region forming a body. At least a portion of the body is disposed between the plurality of first doped regions. The thin film power transistor also includes a gate over the ...

08/23/07 - 20070194379 - Amorphous oxide and thin film transistor
The present invention relates to an amorphous oxide and a thin film transistor using the amorphous oxide. In particular, the present invention provides an amorphous oxide having an electron carrier concentration less than 1018/cm3, and a thin film transistor using such an amorphous oxide. In a thin film transistor having ...

08/23/07 - 20070194378 - Eeprom memory cell for high temperatures
An electrically erasable programmable read-only memory (EEPROM) memory cell is produced using a silicon on insulator (SOI) technology, which is suitable for use at high temperatures. An EEPROM cell is formed from a memory transistor comprising a floating gate and a high-voltage select transistor. The select transistor comprises a freely ...

08/16/07 - 20070187760 - Thin film transistor including low resistance conductive thin films and manufacturing method thereof
A thin film transistor includes a substrate, and a pair of source/drain electrodes (i.e., a source electrode and a drain electrode) formed on the substrate and defining a gap therebetween. A pair of low resistance conductive thin films are provided such that each coats at least a part of one ...

08/16/07 - 20070187758 - Sb-mosfet (schottky barrier metal-oxide-semiconductor field effect transistor) with low barrier height and fabricating method thereof
Provided is a high-performance n-type Schottky barrier tunneling transistor with low Schottky barrier for electrons due to a Schottky junction formed on a Si (111) surface created through anisotropic etching. The Schottky barrier tunneling transistor includes: a silicon on insulator (SOI) substrate; a source and a drain formed on the ...

08/09/07 - 20070181946 - Method and apparatus for forming a semiconductor-on-insulator (soi) body-contacted device
A method for making a semiconductor device includes patterning a semiconductor layer, overlying an insulator layer, to create a first active region and a second active region, wherein the first active region is of a different height from the second active region, and wherein at least a portion of the ...

08/09/07 - 20070181945 - Semiconductor device and manufacturing method thereof
An island-like interlayer insulating film is formed selectively in a region where a source interconnection and a gate interconnection intersect. For example, by use of ink jet method, a solution containing an insulating material is dropped on a region where the gate interconnection and the source interconnection intersect or a ...

08/02/07 - 20070176237 - Semiconductor device and manufacturing method thereof
A semiconductor device comprises a support layer made of semiconductor, a diffusion layer formed by implanting impurities in a surface layer of the support layer, a buried insulating layer provided on the diffusion layer, an island-like active layer provided on the buried insulating layer, a channel region formed in the ...

08/02/07 - 20070176234 - Semiconductor device
The present invention is to provide a semiconductor device that achieves high mechanical strength without reducing the circuit scale and that can prevent the data from being forged and altered illegally while suppressing the cost. The present invention discloses a semiconductor device typified by an ID chip that is formed ...

07/26/07 - 20070170507 - Structure and method for manufacturing planar strained si/sige substrate with multiple orientations and different stress levels
The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; forming a first concentration of lattice modifying material atop the first orientation ...

07/26/07 - 20070170505 - Semiconductor device and manufacturing method thereof
To provide a wireless identification semiconductor device provided with a display function, which is capable of effectively utilizing electric power supplied by an electromagnetic wave. The following are included: an antenna; a power source generating circuit electrically connected to the antenna; an IC chip circuit and a display element electrically ...

07/26/07 - 20070170502 - Semiconductor device and method for manufacturing the same
The present invention provides a high-quality semiconductor device in which deterioration in transistor characteristics and an increase in interface layer due to a gate insulating film are suppressed, and a method for manufacturing the same. In the present invention, an interface layer, a diffusion suppressing layer and a high dielectric ...

07/19/07 - 20070164361 - Micro-mechanically strained semiconductor film
A semiconductor structure embodiment comprises a semiconductor membrane with local strained areas. The membrane with local strained areas is formed by a process including performing a local oxidation of silicon (LOCOS) process in a substrate and removing resulting oxide to form a recess in the substrate, and bonding a semiconductor ...

07/19/07 - 20070164360 - Semiconductor device and method of fabricating the same
A semiconductor device has a supporting substrate applied with a predetermined potential, an insulating layer formed on the supporting substrate, a semiconductor layer formed on the insulating layer, a FDSOI transistor formed on the semiconductor layer and including a source region, a drain region, and a channel region, the channel ...

07/19/07 - 20070164359 - Area-efficient gated diode structure and method of forming same
An area-efficient gated diode includes a semiconductor layer of a first conductivity type, an active region of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, and at least one trench electrode extending substantially vertically through the active region and at least ...

07/19/07 - 20070164358 - Structure and method to form semiconductor-on-pores (sop) for high device performance and low manufacturing cost
A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein ...

07/19/07 - 20070164357 - Structure and method for mosfet gate electrode landing pad
A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is ...

07/19/07 - 20070164356 - Strained semiconductor-on-insulator (ssoi) by a simox method
A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that ...

07/12/07 - 20070158745 - Semiconductor device and manufacturing method thereof
When a metal layer 11 is provided over a substrate, an oxide layer 12 is provided in contact with the metal layer 11, a layer to be peeled 13 is formed, and the metal layer 11 is irradiated with a laser beam to perform oxidization and form a metal oxide ...

07/12/07 - 20070158743 - Thin silicon single diffusion field effect transistor for enhanced drive performance with stress film liners
The present invention provides a semiconducting device structure including a thin SOI region, wherein the SOI device is formed with an optional single thin diffusion, i.e., offset, spacer and a single diffusion implant. The device silicon thickness is thin enough to permit the diffusion implants to abut the buried insulator ...

07/12/07 - 20070158742 - Mos transistor and manufacturing method thereof
There are provided a MOS transistor and a manufacturing method thereof. The MOS transistor includes a substrate on which an insulating layer is formed, a gate embedded in the insulating layer, wherein the top surface of the gate is exposed, a gate oxide layer formed on the insulating layer and ...

06/28/07 - 20070145482 - Thin film transistor and manufacturing method thereof, and liquid crystal display device having thin film transistor and manufacturing method thereof
A liquid crystal display device includes a substrate, a gate line and a data line intersected with each other to define a pixel region on the substrate, a thin film transistor having a nanowire channel layer in an intersection region of the gate line and the data line, and a ...

06/28/07 - 20070145481 - Silicon-on-insulator chip having multiple crystal orientations
A silicon-on-insulator device having multiple crystal orientations is disclosed. In one embodiment, the silicon-on-insulator device includes a substrate layer, an insulating layer disposed on the substrate layer, a first silicon layer, and a strained silicon layer. The first silicon layer has a first crystal orientation and is disposed on a ...

06/28/07 - 20070145480 - Thin film transistor, electrode thereof and method of fabricating the same
A method of forming an electrode of a semiconductor device is provided. A material layer comprising an organo-metallic compound is first formed on a substrate. Thereafter, an electrode is formed by irradiating the material layer through utilizing the heating property of laser. Next, the material layer is patterned by utilizing ...

06/21/07 - 20070138557 - Semiconductor device
A transistor region is a region where a plurality of MOS transistors, including an MOS transistor, are formed, and a dummy region is a region lying under a spiral inductor. In the dummy region, a plurality of dummy active layers are disposed in the main surface of an SOI substrate ...

06/21/07 - 20070138556 - Self-aligned planar double-gate process by self-aligned oxidation
A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the ...

06/21/07 - 20070138555 - One transistor soi non-volatile random access memory cell
Various semiconductor structure embodiments include a substrate, a buried insulator over at least a portion of the substrate, a body region over the buried insulator, first and second source/drain regions to provide a channel region in the body region, a gate insulator over the channel region, and a gate over ...

06/21/07 - 20070138554 - Full depletion soi-mos transistor
A method of manufacturing a full depletion SOI-MOS transistor including a substrate, a buried oxide layer, a thin silicon layer, an isolation layer, a gate insulation layer, a gate electrode and a polysilicon layer. The buried oxide layer is formed on a main surface of the substrate. The thin silicon ...

06/21/07 - 20070138553 - Method of manufacturing semiconductor substrate and semiconductor device
A method of manufacturing a semiconductor substrate comprises: forming a first mono crystalline semiconductor layer in a portion having a mono crystalline area exposed on an active surface side of a mono crystalline semiconductor base material, the first mono crystalline semiconductor layer being made of a mono crystalline material having ...

06/14/07 - 20070132026 - Method for manufacturing semiconductor substrate, method for manufacturing semiconductor device, and semiconductor device
A method for manufacturing a semiconductor substrate includes forming a first semiconductor layer on a semiconductor base; forming a second semiconductor layer having a lower etching selection ratio than the first semiconductor layer on the first semiconductor layer; removing a part of the second semiconductor layer and a part of ...

06/14/07 - 20070132025 - Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device
A method for manufacturing a semiconductor substrate comprises: forming a silicon on insulator (SOI) area and an element isolation film on a semiconductor base; forming a first semiconductor layer on the semiconductor base in the SOI structure area; forming a second semiconductor layer having an etching selection ratio smaller than ...

06/14/07 - 20070132024 - Thin film transistor array panel and method of manufacturing the same
The present invention provides a thin film transistor array panel which includes a substrate, gate lines formed on the substrate, polycrystalline semiconductors formed on the gate lines, data lines formed on the polycrystalline semiconductors and including first electrodes, second electrodes formed on the polycrystalline semiconductors and facing the first electrodes, ...

06/14/07 - 20070132023 - Organic thin film transistor, method of manufacturing the same, and organic light emitting display device having the same
Provided is an organic thin film transistor that can prevents damage to source and drain electrodes when patterning an organic semiconductor layer, and a method of manufacturing an organic light emitting display device having the organic thin film transistor. The organic thin film transistor includes a source electrode and a ...

06/14/07 - 20070132022 - Semiconductor device and method of manufacturing the same
First and second preliminary epitaxial layers are grown from single-crystalline seeds in openings in an insulation layer until the first and second epitaxial layers are connected to each other. While the first and second preliminary epitaxial layers are being grown, a connection structure of a material having an amorphous state ...

06/07/07 - 20070126060 - Sram cell with improved layout designs
A 6T SRAM cell includes a first inverter having a first pull-up transistor and a first pull-down transistor serially coupled between a supply source and a complementary supply source, and a second inverter cross-coupled with the first inverter having a second pull-up transistor and a second pull-down transistor serially coupled ...

05/31/07 - 20070120189 - Crystalline semiconductor thin film, method of fabricating the same, semiconductor device, and method of fabricating the same
There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. An amorphous semiconductor thin film is irradiated with ultraviolet light or infrared light, to obtain a crystalline semiconductor thin film (102). Then, the crystalline semiconductor thin film (102) is ...

05/31/07 - 20070120188 - Light-emitting device and electronic apparatus
A light-emitting device includes a drive transistor that controls a current to be supplied to a light-emitting element from a power supply line, an electrical continuity portion that electrically connects the drive transistor with the light-emitting element, an initializing transistor that is turned ON to diode-connect the drive transistor, and ...

05/31/07 - 20070120187 - Lateral soi semiconductor device
This invention is generally concerned with semiconductor-on-insulator devices, particularly for high voltage applications. A lateral semiconductor-on-insulator device is described, comprising: a semiconductor substrate; an insulating layer on said semiconductor substrate; and a lateral semiconductor device on said insulator; said lateral semiconductor device having: a first region of a first conductivity ...

05/24/07 - 20070114609 - Semiconductor substrate and method of manufacturing the same
A method of manufacturing a semiconductor substrate can effectively prevent a chipping phenomenon and the production of debris from occurring in part of the insulation layer and the semiconductor by removing a outer peripheral portion of the semiconductor substrate so as to make the outer peripheral extremity of the insulation ...

05/24/07 - 20070114608 - Lateral thin-film soi device having a field plate with isolated metallic regions
In a lateral thin-film Silicon-On-Insulator (SOI) device, a field plate is provided to extend substantially over a lateral drift region to protect the device from package and surface charge effects. In particular, the field plate comprises a layer of plural metallic regions which are isolated laterally from one another by ...

05/17/07 - 20070108523 - Semiconductor device and fabrication method for the same
In a semiconductor device including a monocrystalline thin film transistor 16a that has been formed on a monocrystalline Si wafer 100 and then is transferred to a insulating substrate 2, LOCOS oxidization is performed with respect to the element-isolation region of the monocrystalline Si wafer 100 so as to create ...

05/17/07 - 20070108522 - Soi substrate and method of manufacturing the same
The SOI substrate includes a supporting substrate, an insulating layer (first insulating layer), another insulating layer (second insulating layer), and a silicon layer (silicon active layer). On a surface of the supporting substrate, which is the surface on the side of the silicon layer, the first insulating layer is provided. ...

05/17/07 - 20070108521 - Flexible semiconductor device and identification label
Provided is a flexible device (100) having an integrated circuit (5) and an antenna (6) which is incorporated or directly coupled to the interconnect structure of the integrated circuit (5). The interconnect structure extends outside of the active area. An electrically insulating or dielectric layer (4) is present as support ...

05/10/07 - 20070102762 - Semiconductor device, and semiconductor package and circuit device using the same
A first semiconductor element and a second semiconductor element each have an electrode forming surface with an electrode pad thereon. The first semiconductor element and the second semiconductor element are stacked to expose each electrode pad and bonded while facing the electrode forming surfaces each other. The electrode pads of ...

05/10/07 - 20070102761 - Semiconductor device and method of fabricating the same
A semiconductor device includes a semiconductor substrate, a channel region formed above the semiconductor substrate, a first gate electrode formed above the channel region via a first gate insulating film, a second gate electrode formed below the channel region via a second gate insulating film to face the first gate ...

05/10/07 - 20070102760 - Inhibiting radiation hardness of integrated circuits
A system and method for inhibiting radiation hardness of Silicon on Insulator (SOI) integrated circuits is described. An electrical connection is used to connect a substrate below a buried oxide layer to the topside above the buried oxide layer. A bias is then applied to the substrate. The bias may ...

05/03/07 - 20070096211 - Method of evaluating semiconductor device
The present invention provides a semiconductor device having an active region bent at right angles, wherein an interval between patterns for the active region and a gate is set larger than an arc radius of a curved portion (portion where a line is brought to arcuate form) formed inside the ...

05/03/07 - 20070096210 - Semiconductor device and method of forming the same
An insulated gate semiconductor device comprising an insulator substrate having provided thereon a source and a drain region; a channel region being incorporated between said source and said drain regions, said channel region comprising a polycrystalline, a single crystal, or a semi-amorphous semiconductor material; and a region provided under said ...

05/03/07 - 20070096209 - Image displaying device and method for manufacturing same
A technique for improving the manufacturing yield of an image displaying device is disclosed. A fabrication method of the image displaying device includes the steps of forming on an insulative substrate a plurality of island-like semiconductor layers, forming a gate insulating film on the island-like semiconductor layers, defining more than ...

05/03/07 - 20070096208 - Manufacturing method for flat panel display
A dummy glass substrate supporting a plastic insulation substrate for a display apparatus wherein the dummy glass substrate includes a stress relaxation portion having grooves that reduce thermal deformation of the plastic insulation substrate. ...

05/03/07 - 20070096207 - Semiconductor device and method for manufacturing the same
A semiconductor device includes at least one thin film transistor including a semiconductor layer that has a crystalline region including a channel region, a source region and a drain region, a gate insulating film disposed at least on the channel region, the source region and the drain region of the ...

05/03/07 - 20070096206 - Gate electrode stress control for finfet performance enhancement
A finFET and its method for fabrication include a gate electrode formed over a channel region of a semiconductor fin. The semiconductor fin has a crystallographic orientation and an axially specific piezoresistance coefficient. The gate electrode is formed with an intrinsic stress determined to influence, and preferably optimize, charge carrier ...

04/26/07 - 20070090458 - Semiconductor device having first and second separation trenches
A semiconductor device includes: a SOI substrate having a SOI layer, a buried oxide layer and a support substrate; multiple first separation trenches on the SOI layer; multiple MOS transistors, each of which is surrounded with one first separation trench; a second separation trench on the SOI layer including n-ply ...

04/26/07 - 20070090457 - Thin film transistor substrate for display unit
A thin film transistor (TFT) substrate comprises: a plastic insulation substrate; a first silicon nitride layer with a first refractive index, formed one surface of the plastic insulation substrate; and a TFT comprising a second silicon nitride layer formed with a second refractive index smaller than the first refractive index ...

04/26/07 - 20070090456 - Soi device and method for fabricating the same
A semiconductor-on-insulator (SOI) device is described, including a substrate, a first insulating layer and a second insulating layer on the substrate, a semiconductor layer covering the first and the second insulating layers, a gate dielectric layer and a gate on the semiconductor layer, and two doped regions as source/drain regions ...

04/19/07 - 20070085138 - Semiconductor device and manufacturing method thereof
The invention relates to a semiconductor device including a plurality of thin film transistors provided on a base member having a curved surface. The surface may be bent in either a convex shape or a concave shape. All channel length directions of the plurality of thin film transistors may also ...

04/05/07 - 20070075369 - Thin film transistor and method of fabricating the same
A thin film transistor and a method of fabricating the same capable of reducing stress of a substrate caused by a metal layer of the drain and source electrodes, the thin film transistor including a substrate; a semiconductor layer disposed on the substrate and including source, drain and channel regions; ...

04/05/07 - 20070075368 - Cmos inverter cell
A CMOS inverter cell having a small horizontal length which is reduced by substituting metal lines for supplying data signals to gates with a connection pattern which is mounted in one end of a supply voltage area of the CMOS inverter cell and is made of the same material as ...

04/05/07 - 20070075367 - Soi semiconductor component with increased dielectric strength
An SOI semi-conductor element has field electrodes and/or field zones which are arranged between a first and a second semi-conductor zone. Electric coupling is possible between the field electrodes and the field zones. ...

04/05/07 - 20070075366 - Semiconductor memory device and method for manufacturing the same
According to the present invention, there is provided a semiconductor memory device having: a semiconductor layer of a first conductivity type formed above a semiconductor substrate via an embedded insulation film, a gate electrode formed above the semiconductor layer via a gate insulation film, a floating body region of a ...

04/05/07 - 20070075365 - Thin-film transistor and method of making the same
A thin-film transistor includes a substrate having a substantially outwardly protruding support structure formed thereon such that a portion adjacent to the structure is exposed. The support structure has opposed sidewalls sloped at an angle relative to the substrate surface. A stack is established over the portion and over a ...

03/29/07 - 20070069292 - Semiconductor device having ldmos transistor and method for manufacturing the same
A semiconductor device includes: a semiconductor substrate having a first semiconductor layer, an insulation layer and a second semiconductor layer, which are stacked in this order; a LDMOS transistor disposed on the first semiconductor layer; and a region having a dielectric constant, which is lower than that of the first ...

03/29/07 - 20070069291 - Method and apparatus improving gate oxide reliability by controlling accumulated charge
A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in ...

03/22/07 - 20070063283 - Thin film transistor, liquid crystal display using thin film transistor, and method of manufacturing thin film transistor
A semiconductor film, which is located over a gate electrode for forming a channel region between a source electrode and a drain electrode, has a width greater than a width of the source electrode and a width of the drain electrode located over the gate electrode. Irregularities are formed in ...

03/22/07 - 20070063282 - Soi-like structures in a bulk semiconductor substrate
Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the ...

03/22/07 - 20070063281 - Semiconductor device and manufacturing method thereof, soi substrate and display device using the same, and manufacturing method of the soi substrate
A polycrystalline Si thin film and a single crystal Si thin film are formed on an SiO2 film deposited on an insulating substrate. A polycrystalline Si layer is grown by thermally crystallizing an amorphous Si thin film so as to form the polycrystalline Si thin film. A single crystal Si ...

03/22/07 - 20070063280 - Thin film transistor array substrate
A thin film transistor array substrate having a display area and a non-display area is provided. Pixel units, scan lines and data lines are disposed within the display area, and the scan line and data line are electrically connected to the corresponding pixel units. The non-display region has first chip ...

03/22/07 - 20070063279 - Insulation layer for silicon-on-insulator wafer
A method of forming a silicon-on-insulator wafer begins by providing a silicon wafer having a first surface. An ion implantation process is then used to implant oxygen within the silicon wafer to form an oxygen layer that is buried within the silicon wafer, thereby forming a silicon device layer that ...

03/22/07 - 20070063278 - Highly manufacturable sram cells in substrates with hybrid crystal orientation
The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially ...

03/22/07 - 20070063277 - Multiple low and high k gate oxides on single gate for lower miller capacitance and improved drive current
The present invention provides a semiconductor structure having at least one CMOS device in which the Miller capacitances, i.e., overlap capacitances, are reduced and the drive current is improved. The inventive structure includes a semiconductor substrate having at least one overlaying gate conductor, each of the at least one overlaying ...

03/22/07 - 20070063276 - Dense chevron finfet and method of manufacturing same
A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal ...

03/15/07 - 20070057326 - Semiconductor device and manufacturing method of the same
A semiconductor device comprises: a channel region of a transistor formed in a predetermined region of silicon layer formed on insulation film; a gate electrode formed on the channel region via gate insulation film; and source/drain regions formed in the silicon layer thicker than said channel region located out of ...

03/15/07 - 20070057325 - Semiconductor finfet structures with encapsulated gate electrodes and methods for forming such semiconductor finfet structures
Semiconductor structures in which the gate electrode of a FinFET is masked from the process introducing dopant into the fin body of the FinFET to form source/drain regions and methods of fabricating such semiconductor structures. The gate doping, and hence the work function of the gate electrode, is advantageously isolated ...

03/15/07 - 20070057324 - Strained semiconductor device and method of making the same
In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall ...

03/15/07 - 20070057323 - Silicon-on-insulator (soi) read only memory (rom) array and method of making a soi rom
A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper surface ...

03/08/07 - 20070052026 - Semiconductor device and method of manufacturing the same
A semiconductor device is disclosed, which comprises a semiconductor substrate, source/drain regions formed in the semiconductor substrate, a gate insulating film formed on a channel region between the source/drain regions, a gate electrode formed on the gate insulating film, and a sidewall insulating film formed on a sidewall surface of ...

03/08/07 - 20070052025 - Oxide semiconductor thin film transistor and method of manufacturing the same
Provided is a thin film transistor comprising a channel layer comprised of an oxide semiconductor containing In, M, Zn, and O, M including at least one selected from the group consisting of Ga, Al, and Fe. The channel layer is covered with a protective film. ...

03/08/07 - 20070052024 - Thin film transistor having a nano semiconductor sheet and method of manufacturing the same
Provided are a nano semiconductor sheet, a thin film transistor (TFT) using the nano semiconductor sheet, and a flat panel display using nano semiconductor sheet. The nano semiconductor sheet has excellent characteristics, can be manufactured at room temperature, and has good flexibility. The nano semiconductor sheet includes: a first film ...

03/08/07 - 20070052023 - Thin film transistor and method of fabricating the same
A thin film transistor and a method of fabricating the same are disclosed. The method includes: sequentially depositing an amorphous silicon layer, a capping layer, and a metal catalyst layer; annealing the entire layer to crystallize the amorphous silicon layer into a polysilicon layer; removing the capping layer; and, when ...

03/08/07 - 20070052022 - Thin film transistor, method of fabricating the same, and a display device including the thin film transistor
A thin film transistor (TFT), a method of fabricating the same, and a display device including the TFT, are provided. In the TFT, a channel region is connected to a gate electrode so that the influence of a substrate bias is reduced or eliminated. Thus, the threshold voltage of the ...

03/08/07 - 20070052021 - Transistor, and display device, electronic device, and semiconductor device using the same
It is an object of an invention disclosed in the present specification to provide a transistor having low contact resistance. In the transistor, a semiconductor film including an impurity element imparting P-type or N-type conductivity, an insulating film formed thereover, and an electrode or a wiring that is electrically connected ...

03/08/07 - 20070052020 - Thin film transistor and method of manufacturing the same
A Thin Film Transistor comprises a gate electrode formed on a substrate; a gate insulation layer covering the gate electrode; an amorphous silicon (a-Si) region disposed on the gate insulation layer and above the gate electrode; a doped a-Si region formed on the a-Si region; the source and drain metal ...

03/08/07 - 20070052019 - Transistor device wiwth metallic electrodes and a method for use in forming such a device
A transistor device having a metallic source electrode, a metallic drain electrode, a metallic gate electrode and a channel in a deposited semiconductor material, the transistor device comprising: a first layer comprising the metallic gate electrode, a first metal portion of the metallic source electrode and a first metal portion ...

03/01/07 - 20070045740 - Thin film transistor, method of fabricating the same, and a display device including the thin film transistor
A thin film transistor (TFT), a method of fabricating the same, and a display device including the TFT, are provided. The method includes forming an edge region that is doped with impurities of a conductivity type opposite to a conductivity type of impurities doped into source and drain regions. The ...

03/01/07 - 20070045739 - Method for manufacturing semiconductor substrate and method for manufacturing semiconductor apparatus and photomask
A method for manufacturing a semiconductor substrate, includes: forming a first semiconductor layer on a semiconductor base material; forming a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having an etching selectivity larger than that of the first semiconductor layer; forming, at the second semiconductor layer ...

03/01/07 - 20070045738 - Method for the manufacture of a strained silicon-on-insulator structure
The present invention is directed to a strained silicon on insulator (SSOI) structure having improved surface characteristics, such as reduced roughness, low concentration of LPDs, and lower contamination, and a method for making such a structure. ...

03/01/07 - 20070045737 - Semiconductor device and method for manufacturing the same
A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions including ...

03/01/07 - 20070045736 - Finfet and method for manufacturing the same
A gate electrode is arranged in a direction parallel or perpendicular to a specified crystal orientation of a substrate. A first transistor of a first conductivity type has a first active region, which is arranged in a direction perpendicular to the gate electrode. A second transistor of a second conductivity ...

03/01/07 - 20070045735 - Finfet structure with contacts
A FinFET, which by its nature has both elevated source/drains and an elevated channel that are portions of an elevated semiconductor portion that has parallel fins and one source/drain on one side of the fins and another source/drain on the other side of the fins, has all of the source/drain ...

03/01/07 - 20070045734 - Thin film transistor and fabrication method thereof
A thin film transistor is provided, including a substrate, a gate, a first dielectric layer, a channel layer, a source/drain and a second dielectric layer. The gate is disposed on the substrate, and the gate and the substrate are covered with the first dielectric layer. The channel layer is at ...

03/01/07 - 20070045733 - Programmable random logic arrays using pn isolation
Disclosed are a programmable, random logic device array, and a method of forming such a device. The device comprises a substrate, and a semiconductor layer above the substrate. That semiconductor layer, in turn, includes a first region of a first semiconductor type, an array of spaced apart second regions of ...

03/01/07 - 20070045732 - Integrated circuit having a transistor level top side wafer contact and a method of manufacture therefor
The present invention provides an integrated circuit and a method of manufacture therefor. The integrated circuit (100), in one embodiment without limitation, includes a dielectric layer (120) located over a wafer substrate (110), and a semiconductor substrate (130) located over the dielectric layer (120), the semiconductor substrate (130) having one ...

03/01/07 - 20070045731 - Flash memory device having resistivity measurement pattern and method of forming the same
A flash memory device has a resistivity measurement pattern and method of forming the same. A trench is formed in an isolation film in a Self-Aligned Floating Gate (SAFG) scheme. The trench is buried to form a resistivity measurement floating gate. This allows the resistivity of the floating gate to ...

02/22/07 - 20070040218 - Hybrid-orientation technology buried n-well design
A semiconductor structure is provided that includes a hybrid orientated substrate having at least two coplanar surfaces of different surface crystal orientations, wherein one of the coplanar surfaces has bulk-like semiconductor properties and the other coplanar surface has semiconductor-on-insulator (SOI) properties. In accordance with the present invention, the substrate includes ...

02/15/07 - 20070034954 - Thin film conductor and method of fabrication
A thin film conductor having improved adhesion and superior conductivity, a method for fabricating the same, a thin film transistor (TFT) plate including the thin film conductor, and a method for fabricating the TFT plate are provided. The thin film conductor includes an adhesive layer containing an oxidation-reactive metal or ...

02/15/07 - 20070034953 - Semiconductor device and method of fabricating same
A semiconductor device includes: a semiconductor substrate; a first transistor including a first gate electrode including a first metallic silicide layer, the first gate electrode being formed on the semiconductor substrate through a first gate insulating film, a first gate sidewall insulating film formed on a side face of the ...

02/15/07 - 20070034952 - Method of manufacturing semiconductor device having impurity region under isolation region
In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming ...

02/15/07 - 20070034951 - Schotiky barrier tunnel transistor and method of manufacturing the same
Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The ...

02/15/07 - 20070034950 - Semiconductor wafer and method of fabricating the same
Disclosed is a semiconductor wafer and method of fabricating the same. The semiconductor wafer is comprised of a semiconductor layer formed on an insulation layer on a base substrate. The semiconductor layer includes a surface region organized in a first crystallographic orientation, and another surface region organized in a second ...

02/08/07 - 20070029614 - Semiconductor device with thin-film transistors and method of fabricating the same
A semiconductor device with a TFT includes a substrate, an island-shaped semiconductor film serving as an active layer of the TFT on or over the substrate, a pair of source/drain regions formed in the semiconductor film, and a channel region formed between the pair of source/drain regions in the semiconductor ...

02/08/07 - 20070029613 - Electro-optical device, electronic apparatus, and method of manufacturing electro-optical device
An electro-optical device includes: an electro-optical device substrate; step portions having a concave shape that are formed on a predetermined insulating film of the electro-optical device substrate; side wall portions each of which is formed on a side surface of the concave step portion between the surface of the insulating ...

02/08/07 - 20070029612 - Scalable high performance carbon nanotube field effect transistor
A structure and fabrication process for a carbon nanotube field effect transistor is disclosed herein. The structure employs an asymmetric gate which is closer to the source and farther from the drain, which helps to minimize “off current” drain leakage when the drain is biased and the gate is otherwise ...

02/08/07 - 20070029611 - Integrated circuit having a top side wafer contact and a method of manufacture therefor
The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the ...

02/01/07 - 20070023837 - Thin film transistor substrate and method of making the same
The present invention relates to a thin film transistor substrate comprising: an insulating substrate; a source electrode and a drain electrode which are formed on the insulating substrate and separated from each other and have a channel area therebetween; a wall exposing at least portions of the source electrode and ...

02/01/07 - 20070023836 - Semiconductor device
The present invention provides an MOSFET having a semiconductor substrate, an insulating layer provided on the semiconductor substrate, and an SOI layer provided on the insulating layer. A source region and a drain region are provided in the SOI layer. A non-doped region is provided at a position interposed between ...

02/01/07 - 20070023835 - Asymmetry thin-film transistor
An asymmetry thin-film transistor includes a substrate, a semiconductor layer positioned on the substrate, and a gate positioned on the substrate. The semiconductor layer has a channel region, a single lightly doped region and a first heavily doped region positioned at a side of the channel region, and a second ...

02/01/07 - 20070023834 - Method of measuring a surface voltage of an insulating layer
In a method of measuring a surface voltage of an insulating layer, the number of times that surface voltages are measured in a depletion region increases so that precise data about the depletion region may be obtained. The number of times that the surface voltages are measured in an accumulation ...

02/01/07 - 20070023833 - Method for reading a memory cell having an electrically floating body transistor, and memory cell and array implementing same
An integrated circuit device (for example, logic or discrete memory device) including a memory cell including an electrically floating body transistor, wherein the electrically floating body transistor includes a source region, a drain region, a body region disposed between the source region and the drain region, wherein the body region ...

01/25/07 - 20070018247 - Method and apparatus for use in improving linearity of mosfet's using an accumulated charge sink
A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, ...

01/25/07 - 20070018246 - Semiconductor device and semiconductor device manufacturing method
A semiconductor device includes a back gate electrode composed of a first single-crystal semiconductor layer formed on a first insulating layer, a second insulating layer formed on the first single-crystal semiconductor layer, a second single-crystal semiconductor layer formed on the second insulating layer and having a film thickness smaller than ...

01/18/07 - 20070013002 - Field effect transistor with a heterostructure and associated production method
A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1-x), where the proportion x ...

01/18/07 - 20070013001 - Epitaxial imprinting
The present invention provides an epitaxial imprinting process for fabricating a hybrid substrate that includes a bottom semiconductor layer; a continuous buried insulating layer present atop said bottom semiconductor layer; and a top semiconductor layer present on said continuous buried insulating layer, wherein said top semiconductor layer includes separate planar ...

01/11/07 - 20070007596 - Method to manufacture silicon quantum islands and single-electron devices
The present invention provides a method of manufacturing a single-electron transistor device (100). The method includes forming a thinned region (110) in a silicon substrate (105), the thinned region (110) offset by a non-selected region (115). The method also includes forming at least one quantum island (145) from the thinned ...

01/11/07 - 20070007595 - Semiconductor device with effective heat-radiation
The semiconductor device has a silicon layer (SOI layer) (12) formed through a silicon oxide film (11) on a support substrate (10). A transistor (T1) is formed in the SOI layer (12). The wiring (17a) is connected with a source of the transistor (T1) through a contact plug (15a). A ...

01/11/07 - 20070007594 - Semiconductor device and method of manufacturing the same
According to the present invention, there is provided a semiconductor device manufacturing method comprising: depositing a semiconductor layer and mask material in order over a semiconductor substrate on an insulating film; patterning the semiconductor layer and mask material to form a semiconductor layer in a predetermined region; removing a surface ...

01/04/07 - 20070001228 - Semiconductor device and method of manufacturing the same
In a conventional method of crystallization using a laser beam, variance (or dispersion) in a TFT characteristic becomes large, which causes various functions of a semiconductor device comprising TFTs as components of its electronic circuit to be restrained. A first shape of semiconductor region having on its one side a ...

01/04/07 - 20070001227 - Manufacturing processing for an isolated transistor with strained channel
Transistor type semiconducting device comprising: a substrate, an insulating layer comprising sidewalls formed on each part of the source zone and the drain zone, drain, channel and source zones, the channel zone being formed on the insulating layer and being strained by the drain and the source zones, between the ...

01/04/07 - 20070001226 - Semiconductor device
The present invention provides a semiconductor device in which a first conductive layer included in a stack having a transistor and a second conductive layer over a substrate are electrically connected. The semiconductor device provides a s conductive layer for electrically connecting the first conductive layer included in the stack ...

01/04/07 - 20070001225 - Semiconductor device and manufacturing method of the same
To provide a manufacturing method in which LDD regions with different widths are formed in a self-aligned manner, and the respective widths are precisely controlled in accordance with each circuit. By using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function formed of ...

01/04/07 - 20070001224 - Minute structure, micromachine, organic transistor, electric appliance, and manufacturing method thereof
A micromachine is generally formed using a semiconductor substrate such as a silicon wafer. One of the objects of the present invention is to realize further reduction in cost by integrating a minute structure and a semiconductor element controlling the minute structure over one insulating surface in one step. A ...

01/04/07 - 20070001223 - Ultrathin-body schottky contact mosfet
An ultra thin SOI MOSFET device structure and method of fabrication is presented. The device has a terminal composed of silicide, which terminal is forming a Schottky contact with the channel. A plurality of impurities are segregated on the silicide/channel interface, and these segregated impurities determine the resistance of the ...

01/04/07 - 20070001222 - Single transistor memory cell with reduced recombination rates
A semiconductor fabrication method includes forming a semiconductor structure including source/drain regions disposed on either side of a channel body wherein the source/drain regions include a first semiconductor material and wherein the channel body includes a migration barrier of a second semiconductor material. A gate dielectric overlies the semiconductor structure ...

12/28/06 - 20060289934 - Semiconductor device, liquid crystal display panel, electronic device, and method of manufacturing semiconductor device
In a plurality of transistors in which the thresholds that are required in the circuit design are equal, a transistor having an initial threshold at a lower limit within an acceptable range of the required threshold is arranged at a circuit position where an absolute value of a threshold voltage ...

12/21/06 - 20060284253 - Organic thin film transistor and method of manufacturing the same
An organic thin film transistor (OTFT) includes a substrate, a gate electrode formed on the transparent substrate, a gate insulation film formed on the gate electrode, a source electrode and a drain electrode formed spaced apart from each other on the gate insulation film, a device insulation film formed over ...

12/21/06 - 20060284252 - Process for holding strain in an island etched in a strained thin layer and structure obtained by implementation of this process
The invention relates to structures useful for the manufacture of electronic components, which comprise a substrate, a strain holding layer, and a layer of a strained semiconducting material. These structures are particularly useful where islands are later formed in the strained semiconducting material because the strain holding layer limits relaxation ...

12/21/06 - 20060284251 - Coplanar silicon-on-insulator (soi) regions of different crystal orientations and methods of making the same
In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI ...

12/21/06 - 20060284250 - Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates
A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions ...

12/14/06 - 20060278927 - Body biasing structure of soi
A body biasing structure of devices connected in series on an SOI substrate is provided. According to some embodiments, the shallow junction of common source/drain regions enables all devices to bias by only one body contact on an SOI substrate like a conventional bulk MOSFET, and the floating body effect ...

12/14/06 - 20060278926 - Capacitorless dram on bulk silicon
A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A ...

12/07/06 - 20060273394 - Semiconductor device and method of manufacturing same
A semiconductor device which achieves reductions in malfunctions and operating characteristic variations by reducing the gain of a parasitic bipolar transistor, and a method of manufacturing the same are provided. A silicon oxide film (6) is formed partially on the upper surface of a silicon layer (3). A gate electrode ...

12/07/06 - 20060273393 - Structure and method of making field effect transistor having multiple conduction states
A field effect transistor (“FET”) is provided has a semiconductor region including a channel region, a source region and a drain region and a gate conductor overlying the channel region. Such FET has a first threshold voltage having a first magnitude and a second threshold voltage having a second magnitude ...

11/30/06 - 20060267097 - Method for forming a mos transistor and structure thereof
A method for forming a MOS transistor having LDD structure by a simple and a few number of processes and a structure thereof are described. In accordance with the present invention, a low concentration of an impurity region can be formed in a semiconductor film part between an end of ...

11/30/06 - 20060267096 - Method of designing semiconductor device, semiconductor device and recording medium
A semiconductor device including a transistor having an SOI structure the operating speed of which is not affected is provided. A MOS transistor having the SOI structure is formed which satisfies R·C·f<1 where C is a gate capacitance (F), R is a body resistance (Ω), f is a clock operating ...

11/30/06 - 20060267095 - Semiconductor device
A semiconductor device capable of reducing deterioration of electron mobility while suppressing depletion of gate electrodes is provided. This semiconductor device includes a metal-containing layer so formed that at least either a first gate electrode or a second gate electrode partially covers a corresponding first or second gate insulating film ...

11/30/06 - 20060267094 - Organic thin film transistor, method of fabricating the same, and flat panel display having the organic thin film transistor
An organic thin film transistor that prevents the surface of an organic semiconductor layer from being damaged and reduces turn-off current, a method of fabricating the same, and an organic light-emitting device incorporating the organic thin film transistor. The organic thin film transistor includes a substrate, source and drain electrodes ...

11/30/06 - 20060267093 - Floating-body dynamic random access memory and method of fabrication in tri-gate technology
A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A ...

11/23/06 - 20060261409 - Si nanowire substrate, method of manufacturing the same, and method of manufacturing thin film transistor using the same
A silicon nanowire substrate having a structure in which a silicon nanowire film having a fine line-width is formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the silicon nanowire substrate includes preparing ...

11/16/06 - 20060255409 - Anomaly notification control in disk array
In a storage device incorporating a plurality of kinds of disk drives with different interfaces, the controller performs sparing on a disk drive, whose errors that occur during accesses exceed a predetermined number, by swapping it with a spare disk drive that is prepared beforehand. ...

11/16/06 - 20060255408 - Semiconductor device and method for manufacturing the same
There is provided a semiconductor device in which the characteristic variations of a transistor and the degradation of a gate oxide layer are reduced during a WP process and a method for manufacturing the same. The semiconductor device includes a semiconductor chip having an SOI transistor. The SOI transistor includes ...

11/16/06 - 20060255407 - Semiconductor device and manufacturing method of the same
In a peripheral insulating film in a peripheral region, concave parts are provided. At least one of the concave parts is made to have an opening as a contact hole with an Al wiring layer, and a plurality of contact holes may be provided. Accordingly, frictions between the Al wiring ...

11/16/06 - 20060255406 - Semiconductor device
An object of the present invention is to provide a semiconductor device which enables to reduce the device area, while securing the breakdown voltage between the drain and the source of each MOS transistor for the semiconductor device including plural MOS transistors, which are arrayed adjacently each other, with different ...

11/16/06 - 20060255405 - Fully-depleted soi mosfet device and process for fabricating the same
The present invention proposes a nano-scale high-performance SOI MOSFET device and a process for manufacturing the same. The device is characterized by comprising: a metal oxide semiconductor, formed on the SOI substrate; a silicide layer (05), wherein a gate consists of a single full silicide gate (10), a high-K dielectric ...

11/09/06 - 20060249790 - Method for fabricating sige-on-insulator (sgoi) and ge-on-inulator (goi) substrates
A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the ...

11/09/06 - 20060249789 - Inter-digitated silicon photodiode based optical receiver on soi
A photodiode includes SOI substrate and a plurality of interdigitated electrodes comprising of different doped regions. A silicon device region is defined in the SOI substrate having a thickness between 0.5 and 5 microns. ...

11/02/06 - 20060244066 - Contacts to semiconductor fin devices
A method for forming a contact to a semiconductor fin which can be carried out by first providing a semiconductor fin that has a top surface, two sidewall surfaces and at least one end surface; forming an etch stop layer overlying the fin; forming a passivation layer overlying the etch ...

11/02/06 - 20060244065 - Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate having first and second regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in the second region and having an upper surface higher than an upper surface of the first insulating film, ...

11/02/06 - 20060244064 - Semiconductor device for limiting leakage current
Formed on an insulator (9) are an N− type semiconductor layer (10) having a partial isolator formed on its surface and a P− type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P+ type semiconductor layers are provided on the semiconductor layer (10) ...

11/02/06 - 20060244063 - Thin film transistor and manufacturing method thereof
The present invention provides a thin film transistor in which a substantial length of a channel is shortened to miniaturize a semiconductor device and a manufacturing method thereof. In addition, the present invention provides a semiconductor device which realizes high-speed operation and high-performance of the semiconductor device and a manufacturing ...

11/02/06 - 20060244062 - Silicon-on-insulator based radiation detection device and method
Structures and a method for detecting ionizing radiation using silicon-on-insulator (SOI) technology are disclosed. In one embodiment, the invention includes a substrate having a buried insulator layer formed over the substrate and an active layer formed over the buried insulator layer. Active layer may be fully depleted. A transistor is ...

11/02/06 - 20060244061 - Integrated circuit (ic) with high-q on-chip discrete capacitors
A semiconductor structure that may be a discrete capacitor, a Silicon On Insulator (SOI) Integrated Circuit (IC) including circuits with discrete such capacitors and/or decoupled by such discrete capacitors and an on-chip decoupling capacitor (decap). One capacitor plate may be a well (N-well or P-well) in a silicon bulk layer ...

10/26/06 - 20060237790 - Structure and method for manufacturing planar soi substrate with multiple orientations
The present invention provides a method of forming a substantially planar SOI substrate having multiple crystallographic orientations including the steps of providing a multiple orientation surface atop a single orientation layer, the multiple orientation surface comprising a first device region contacting and having a same crystal orientation as the single ...

10/26/06 - 20060237789 - Thin film transistor (tft) and flat panel display including the tft
A Thin Film Transistor (TFT) that can reduce leakage current and can prevent crosstalk between adjacent TFTs includes: a substrate; a gate electrode disposed on the substrate; a source electrode and a drain electrode separated from each other and insulated from the gate electrode; and a semiconductor layer which is ...

10/26/06 - 20060237788 - Semiconductor device and its fabrication method
A semiconductor device has a semiconductor substrate, a first MOSFET which has a first gate insulating film made of a high dielectric material formed above the semiconductor substrate and a first gate electrode formed above the first gate insulating film, an insulating film which is formed directly on sidewalls of ...

10/19/06 - 20060231894 - Transistor
A transistor comprises: an insulating layer; a semiconductor layer provided on a major surface of the insulating layer; a gate insulating layer provided on the base region; and a gate electrode provided on the gate insulating layer. The semiconductor layer has a source portion having a plurality of source regions ...

10/19/06 - 20060231893 - Hybrid crystal orientation cmos structure for adaptive well biasing and for power and performance enhancement
The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device ...

10/19/06 - 20060231892 - Enhanced silicon-on-insulator (soi) transistors and methods of making enhanced soi transistors
Enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. A selective epitaxial growth is utilized in the source/drain regions ...

10/19/06 - 20060231891 - Soi sram products with reduced floating body effect and the method thereof
A memory device is formed on a semiconductor-on-insulator (SOI) structure, the SOI structure including a substrate, an insulating layer on the substrate, and a semiconductor film on the insulating layer. The memory device includes a memory array in a memory region of the SOI structure, a plurality of first substrate ...

10/12/06 - 20060226486 - Semiconductor device
The present invention provides a semiconductor device which has a substrate formed as a rigid body, stress relaxation layers formed by filling in concave portions defined in a first main surface of the substrate, and a device forming layer which covers part of the first main surface and is formed ...

10/12/06 - 20060226485 - Semiconductor device
A semiconductor element is configured to prevent deterioration thereof due to an electrical charge occurring at a top surface/bottom surface of a support substrate during a plasma process in manufacturing a semiconductor device using an SOI substrate. The semiconductor