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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Short Channel Insulated Gate Field Effect Transistor > With Lightly Doped Portion Of Drain Region Adjacent Channel (e.g., Ldd Structure) With Lightly Doped Portion Of Drain Region Adjacent Channel (e.g., Ldd Structure)With Lightly Doped Portion Of Drain Region Adjacent Channel (e.g., Ldd Structure) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.12/06/07 - 20070278573 - High-voltage pmos transistor In a high-voltage PMOS transistor having an insulated gate electrode (18), a p-conductive source (15) in an n-conductive well (11), a p-conductive drain (14) in a p-conductive well (12) which is arranged in the n-conductive well, and having a field oxide area (13) between the gate electrode and drain, the ... 10/25/07 - 20070246773 - Drive circuit and drain extended transistor for use therein A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also comprises a drain region of the first conductivity type and electrically communicating with a second semiconductor region that differs from the first semiconductor region. An interface exists between ... 10/18/07 - 20070241397 - Semiconductor apparatus and method of manufacturing the same A semiconductor apparatus is disclosed. The semiconductor apparatus comprises a gate electrode formed on a surface of a semiconductor substrate with a gate insulating film provided therebetween. The semiconductor apparatus further comprises a gate sidewall insulating film having a three-layered structure formed of a first nitride film, an oxide film, ... 10/04/07 - 20070228464 - Mos transistor A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, ... 08/16/07 - 20070187757 - Semiconductor devices and methods of fabricating the same The present disclosure provides an example of a semiconductor device. In addition, a method for fabricating a semiconductor device is outlined. The semiconductor device may be fabricated by providing a semiconductor substrate, forming a gate over the substrate, forming diffusion barrier ion regions, forming halo regions, forming a source, and ... 08/09/07 - 20070181944 - Electronic device including space-apart radiation regions and a process for forming the same An electronic device can include a first radiation region, a second radiation region spaced apart from the first radiation region, and an insulating region. The insulating region can have a first side and a second side opposite the first side. The first radiation region can lie immediately adjacent to the ... 07/26/07 - 20070170501 - Mos transistors including silicide layers on source/drain regions A MOS transistor can include a substrate and a field region formed at the semiconductor substrate to define an active region. An I-shaped spacer is on sidewalls of the gate electrode. A lightly doped region and a heavily doped region are on the semiconductor substrate on sides of the gate ... 07/05/07 - 20070152270 - Transistors and manufacturing methods thereof Transistors and manufacturing methods thereof are disclosed. An example transistor includes a semiconductor substrate divided into device isolation regions and a device active region. The example transistor includes a gate insulating film formed in the active region of the semiconductor substrate, a gate formed on the gate insulating film, a ... 06/28/07 - 20070145479 - Semiconductor device having super junction structure A semiconductor device includes: two main electrodes; multiple first regions; and multiple second regions. The first region having a first impurity concentration and a first width and the second region having a second impurity concentration and a second width are alternately repeated. A product of the first impurity concentration and ... 06/21/07 - 20070138552 - Method to produce high voltage device A high-voltage semiconductor device includes a silicon substrate having a main surface, a gate on the main surface of the silicon substrate, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main ... 06/14/07 - 20070132021 - Semiconductor device and method of manufacturing the semiconductor device A semiconductor device includes a substrate having a recess, a gate electrode in the recess in the substrate, and a source electrode and a drain electrode disposed on opposite sides of the gate electrode. An insulating film is on at least on a surface of the gate electrode and a ... 06/07/07 - 20070126059 - Semiconductor device An object is to provide a semiconductor device which includes an anti-collision function during or after production of an IC chip just by a change of a program, even when there is a change of a specification of a product accompanying a change of the kind or standard of a ... 06/07/07 - 20070126058 - Semiconductor device and manufacturing method thereof It is an object of the present invention to obtain a transistor with a high ON current including a silicide layer without increasing the number of steps. A semiconductor device comprising the transistor includes a first region in which a thickness is increased from an edge on a channel formation ... 04/19/07 - 20070085137 - Semiconductor integrated circuit device and a manufacturing method for the same Provided is a manufacturing method for a power management semiconductor device or an analog semiconductor device both including a CMOS. According to the method, a substance having high thermal conductivity is additionally provided above a semiconductor region constituting a low impurity concentration drain region so as to expand the drain ... 03/08/07 - 20070052018 - Method of providing electrical separation in intergrated devices and related device An integrated device includes two sections, such as a DFB laser and an EAM modulator, having a semi-insulating separation region therebetween. The separation region is of a material acting as a trap on electrons and configured to impede current flow between the two sections due to holes. The separation region ... 03/01/07 - 20070045730 - Semiconductor device, method of manufacturing the same, and electronic device having the same A semiconductor device, which can improve the effect of a hydrogenation treatment in case of using a GOLD structure, and a method of manufacturing thereof is provided. A gate insulating film is formed on a semiconductor layer, and a source region, a drain region, and LDD regions are formed in ... 03/01/07 - 20070045729 - Technique for forming recessed strained drain/source regions in nmos and pmos transistors By forming a strained semiconductor layer in a PMOS transistor, a corresponding compressively strained channel region may be achieved, while, on the other hand, a corresponding strain in the NMOS transistor may be relaxed. Due to the reduced junction resistance caused by the reduced band gap of silicon/germanium in the ... 02/15/07 - 20070034948 - Silicidation process for an nmos transistor and corresponding integrated circuit An integrated circuit provided with an NMOS transistor includes a metal silicide on source, drain and gate regions and also on at least one portion of the source and drain extension zones The metal silicide portion located on the source and drain extension zones is thinner than the metal silicide ... 02/01/07 - 20070023832 - Semiconductor device and method of fabricating the same In view of micronizing semiconductor device and of suppressing current leakage in a shared contact allowing contact between a gate electrode and an impurity-diffused region, a semiconductor device 100 includes a first gate electrode 108, a fourth source/drain region 114b, and a shared contact electrically connecting the both, wherein in ... 01/25/07 - 20070018245 - Fringing field induced localized charge trapping memory The present invention includes a semiconductor layer formed over an insulation layer and a substrate. Doped regions are formed in a portion of the semiconductor layer. A gate dielectric and a gate are respectively formed over the semiconductor layer. The arrangement of the gate sidewall and semiconductor layer surface is ... 12/21/06 - 20060284249 - Impurity co-implantation to improve transistor performance A pMOS transistor having reduced diffusion from source/drain regions and a method of forming the same are provided. The pMOS transistor includes a source/drain region doped with a p-type impurity and a diffusion-retarding material in a semiconductor substrate. The pMOS transistor further includes a gate dielectric over a channel region ... 10/05/06 - 20060220125 - Semiconductor device In a semiconductor device of the present invention, a thin gate oxide film is formed on a P-type diffusion layer. On the gate oxide film, a gate electrode is formed. N-type diffusion layers are formed in the P-type diffusion layer, and the N-type diffusion layer is used as a drain ... 10/05/06 - 20060220124 - Semiconductor device and fabrication method of the same A semiconductor device includes a gate electrode, a source electrode, a drain electrode and an electrode part. The gate electrode is formed above a semiconductor layer. The source electrode and the drain electrode are formed on the semiconductor layer. The gate electrode is located between the source electrode and the ... 09/14/06 - 20060202267 - Methods of optimization of implant conditions to minimize channeling and structures formed thereby Methods of forming a microelectronic structure are described. Those methods comprise implanting a first concentration of a species into an active area with a first energy, wherein the species pre-damages a portion of the active area, and then implanting a second concentration of the species into the active area with ... 09/14/06 - 20060202266 - Field effect transistor with metal source/drain regions A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in ... 08/24/06 - 20060186471 - Manufacturing method for semiconductor device A semiconductor device with simple device structure enables reduction in the number of manufacturing steps and the manufacturing cost. A gate insulation film and a gate electrode are formed in a certain area on a semiconductor substrate. A semiconductor substrate non-removed section is formed under the gate insulation film, and ... 08/24/06 - 20060186470 - Strained transistor with hybrid-strain inducing layer A semiconductor device having a hybrid-strained layer and a method of forming the same are discussed. The semiconductor device comprises: a gate dielectric over a substrate; a gate electrode over the gate dielectric; an optional pair of spacers along the sidewalls of the gate dielectric and the gate electrode; a ... 07/13/06 - 20060151832 - Semiconductor transistor having a stressed channel A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the ... 07/06/06 - 20060145254 - Semiconductor devices including carrier accumulation layers and methods for fabricating the same A semiconductor device includes a gate structure on a channel region of a semiconductor substrate adjacent to a source/drain region therein and a surface insulation layer directly on the source/drain region of the substrate adjacent to the gate structure. The device further includes a spacer on a sidewall of the ... 07/06/06 - 20060145253 - Mos transistor and method of manufacturing the same A manufacturing method of a double LDD MOS transistor includes forming a gate electrode on a semiconductor substrate; forming a first LDD area by implanting and thermally annealing impurity ions using the gate electrode as a mask; forming a first spacer on both lateral walls of the gate electrode; forming ... 04/27/06 - 20060086975 - Device junction structure A semiconductor device includes a gate structure having a plurality of gate layers, which are layered upon a gate dielectric. A pair of thin spacers is formed on corresponding sidewalls of the gate structure. Each thin spacer is at most 25 nanometers (nm) wide. Length of the gate structure is ... 04/20/06 - 20060081927 - Method of manufacturing an esd protection device with the same mask for both ldd and esd implantation A method of manufacturing a semiconductor device having a first and second transistor of an ESD protection and internal circuit respectively. The method includes the steps of providing a substrate, forming gates of the first and second transistor on the substrate, depositing a mask layer and patterning the mask layer ... 04/20/06 - 20060081926 - Method of forming shallow doped junctions having a variable profile gradation of dopants Disclosed is an electrical device having, and a process for forming, a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention includes first providing and masking a surface on an in-process integrated circuit wafer on which the shallow junction is to be formed. ... 04/20/06 - 20060081925 - Semiconductor device with asymmetric pocket implants A semiconductor device (1) has a source (2) a gate (3) and a drain (4), a single deep-pocket ion implant (8) in a source-drain depletion region, and a single shallow-pocket ion implant (9) in the source-drain depletion region. ... 03/30/06 - 20060065928 - Semiconductor device The invention provides a semiconductor apparatus capable of achieving a device having a snap-back resisting pressure of about 5 to 10 V by a self-aligning process. The semiconductor apparatus includes two or more sub-gates placed next to a main gate at a predetermined interval, and low concentration layers placed continuously ... 03/02/06 - 20060043482 - Programming and erasing structure for an nvm cell A non-volatile memory (NVM) has a silicon germanium (SiGe) drain that is progressively more heavily doped toward the surface of the substrate. The substrate is preferably silicon and the drain is formed by first forming a cavity in the substrate in the drain location. SiGe is epitaxially grown in the ... 02/16/06 - 20060033158 - Method for fabricating a recessed channel field effect transistor (fet) device A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a ... 02/09/06 - 20060027866 - Method of forming a recessed buried-diffusion device A method of forming a device (and the device so formed) comprising the following steps. A structure having a gate structure formed thereover is provided. Respective low doped drains are formed within the structure at least adjacent to the gate structure. A pocket implant is formed within the structure. The ... 12/29/05 - 20050285191 - Semiconductor device and method of fabricating the same According to the present invention, there is provided a semiconductor device comprising: a gate electrode formed on a surface of a semiconductor device via a gate insulating film; gate electrode sidewalls formed on side surfaces of said gate electrode; a first source region and first drain region formed, in a ... 11/10/05 - 20050247976 - Notched spacer for cmos transistors A notched spacer for CMOS transistors and a method of manufacture is provided. A gate electrode is formed on a substrate. A first ion implant mask is formed alongside the gate electrode such that the first ion implant mask is at least partially removed along the surface of the substrate. ... 10/27/05 - 20050236667 - Manufacture of semiconductor device with selective amorphousizing A p-channel MOS transistor capable of lowering the height of a gate electrode, suppressing penetration of boron through a gate insulating film, and reducing a source/drain parasitic capacitance. A method for manufacturing a semiconductor device comprises the steps of: (a) forming a gate insulating film on each surface of active ... 10/13/05 - 20050224874 - Forming a retrograde well in a transistor to enhance performance of the transistor A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into ... 10/13/05 - 20050224873 - Method of forming a recessed buried-diffusion device A method of forming a device (and the device so formed) comprising the following steps. A structure having a gate structure formed thereover is provided. Respective low doped drains are formed within the structure at least adjacent to the gate structure. A pocket implant is formed within the structure. The ... 10/06/05 - 20050218449 - Semiconductor device realizing characteristics like a soi mosfet In a semiconductor device, source/drain layers have a low resistivity region and an extension region extending from the low resistivity region toward the channel region. The extension regions are lower in impurity concentration and shallower in depth than the low resistivity regions. The device also has a first impurity-doped layer ... 09/29/05 - 20050212043 - Semiconductor device and manufacturing method thereof A semiconductor device with simple device structure enables reduction in the number of manufacturing steps and the manufacturing cost. A gate insulation film and a gate electrode are formed in a certain area on a semiconductor substrate. A semiconductor substrate non-removed section is formed under the gate insulation film, and ... 09/22/05 - 20050205927 - Semiconductor device having mosfet with offset-spacer, and manufacturing method thereof A semiconductor device includes a gate insulating film which is formed on the major surface of a semiconductor substrate, a gate electrode which is formed on the gate insulating film, a first offset-spacer which is formed in contact with one side surface of the gate electrode, a first spacer which ... 08/18/05 - 20050179085 - Semiconductor device and manufacturing method of the same Substitution reaction between polysilicon and Al (aluminum) is utilized. Namely, polysilicon films are formed by patterning at first as in the related art, and after an Al film is formed on an interlayer insulating film to be in contact with the polysilicon films, the polysilicon films in the interlayer insulating ... 07/28/05 - 20050161736 - Semiconductor device and method of fabricating semiconductor device To provide a semiconductor device which makes it possible to avoid deterioration in the step coverage property at a gate electrode provided on an operating region and decrease a leakage current between the operating region and the gate electrode. The semiconductor device arranged as a HEMT is made to include ... 07/21/05 - 20050156236 - Mos transistor with a three-step source/drain implant A new MOS transistor is described. The transistor has a source/drain region that comprises 3 portions. Each portion is the result of an separate ion implant step. The combination of the three portions of the source/drain region yields a transistor of superior performance with high drive current, low sub-threshold current ... 07/14/05 - 20050151191 - Semiconductor device and method of manufacturing the same A semiconductor device includes a post-oxide film comprising first, second and third portions. The first portion extends on the sidewall of a gate electrode provided on a gate insulating film on the surface of the semiconductor substrate to the surface of the semiconductor substrate. The second portion extends on the ... ### FreshPatents.com Support |