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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Short Channel Insulated Gate Field Effect Transistor > Active Channel Region Has A Graded Dopant Concentration Decreasing With Distance From Source Region (e.g., Double Diffused Device, Dmos Transistor) > In Integrated Circuit Structure > With Complementary Field Effect Transistor

With Complementary Field Effect Transistor

With Complementary Field Effect Transistor patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

09/11/14 - 20140252471 - Shared contacts for mosfet devices
In one aspect, the present invention provides electronic devices that comprise a doped semiconductor shared contact between (a) a gate conductor region of at least one transistor and (b) a source/drain diffusion region of at least one transistor. One specific example of such as shared contact, among many others, is...

07/03/14 - 20140183631 - Low cost transistors
An integrated circuit containing an analog MOS transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the gate, but exposes a channel region to the well dopants. A thermal drive step diffuses the implanted well dopants across the two diluted...

06/19/14 - 20140167158 - Integrated device and method for fabricating the integrated device
The invention relates to the field of fabricating a semiconductor integrated circuit and particularly to an integrated device and a method for fabricating the integrated device in order to address the problem that a drift area is fabricated on an epitaxial layer but the application scope of the LDMOS is...

06/05/14 - 20140151797 - Semiconductor device including alternating source and drain regions, and respective source and drain metallic strips
A semiconductor device and method of forming the same including, in one embodiment, a substrate and a plurality of source and drain regions formed as alternating pattern on the substrate. The semiconductor device also includes a plurality of gates formed over the substrate between and parallel to ones of the...

03/13/14 - 20140070314 - Semiconductor device and semiconductor integrated circuit device using the same
There is provided an MOSFET having a large current density, which can be mixed with a logic circuit, and is used in a circuit that conducts the operation of applying a negative voltage to a drain electrode. An electrode surrounded by an insulating film is formed, at an intermediate position...

02/20/14 - 20140048876 - Semiconductor device including a high breakdown voltage dmos and method of manufacturing the same
A semiconductor device includes a high breakdown voltage DMOS transistor formed on a first conductivity type semiconductor substrate. The semiconductor device includes: a DMOS second conductivity type well; a DMOS first conductivity body region; a DMOS second conductivity type source region; a DMOS second conductivity type drain region; a LOCOS...

02/06/14 - 20140035033 - Semiconductor device and fabrication method thereof
A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a P type well region and an N type well region formed in a substrate, a gate insulating layer having a non-uniform thickness and formed on the P type well region and the N type well...

11/14/13 - 20130299904 - Ldmos one-time programmable device
According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a pass gate dielectric, and a programming gate including a programming gate electrode and a programming gate dielectric. The programming gate is spaced from...

11/07/13 - 20130292765 - Semiconductor device having a drain-gate isolation portion
An inventive semiconductor device includes a semiconductor layer, a source region provided in a surface layer portion of the semiconductor layer, a drain region provided in the surface of the semiconductor layer in spaced relation from the source region, a gate insulation film provided in opposed relation to a portion...

09/26/13 - 20130249000 - Short channel semiconductor devices with reduced halo diffusion
A short channel semiconductor device is formed with halo regions that are separated from the bottom of the gate electrode and from each other. Embodiments include implanting halo regions after forming source/drain regions and source/drain extension regions. An embodiment includes forming source/drain extension regions in a substrate, forming source/drain regions...

09/12/13 - 20130234248 - Semiconductor device, printing apparatus, and manufacturing method thereof
A manufacturing method of a semiconductor device including a DMOS transistor, an NMOS transistor and a PMOS transistor arranged on a semiconductor substrate, the DMOS transistor including a first impurity region and a second impurity region formed to be adjacent to each other, the first impurity region being of the...

08/08/13 - 20130200453 - Semiconductor devices including bipolar transistors, cmos transistors and dmos transistors, and methods of manufacturing the same
Semiconductor devices having a bipolar transistor, a CMOS transistor, a drain extension MOS transistor and a double diffused MOS transistor are provided. The semiconductor device includes a semiconductor substrate including a logic region in which a logic device is formed and a high voltage region in which a high power...

07/11/13 - 20130175614 - Semiconductor devices and methods of fabricating the same
Semiconductor devices and methods of fabricating the same are provided. The semiconductor device includes a substrate having a first region including a first element and a second region including a second element and including a lower substrate and an upper substrate bonded to each other, an epitaxial layer and an...

01/24/13 - 20130020638 - Electronic devices and systems, and methods for making and using the same
Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and...

01/24/13 - 20130020639 - Electronic devices and systems, and methods for making and using the same
Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and...

01/17/13 - 20130015522 - Semiconductor device
A semiconductor device includes an active region formed in a semiconductor substrate made of silicon, and surrounded by an isolation region; and a gate electrode formed on the active region and the isolation region with a gate insulating film interposed between the gate electrode and the active region or the...

12/20/12 - 20120319201 - Semiconductor devices having vertical device and non-vertical device and methods of forming the same
In a semiconductor device, a vertical transistor comprises: a first diffusion region on a substrate; a channel region on the first diffusion region and extending in a vertical direction; a second diffusion region on the channel region; and a gate electrode at a sidewall of, and insulated from, the channel...

12/06/12 - 20120306013 - Metal oxide semiconductor output circuits and methods of forming the same
Metal oxide semiconductor (MOS) protection circuits and methods of forming the same are disclosed. In one embodiment, an integrated circuit includes a pad, a p-type MOS (PMOS) transistor, and first and second n-type MOS (NMOS) transistors. The first NMOS transistor includes a drain, a source and a gate electrically connected...

09/27/12 - 20120241859 - Switch circuit using ldmos element
The present invention relates to a switch circuit, and more particularly, to a switch circuit that uses an LDMOS (lateral diffusion metal oxide semiconductor) device inside an IC (Integrated Circuit). In the switch circuit that uses the LDMOS device according to an embodiment of the present invention, a gate-source voltage...

09/27/12 - 20120241860 - Semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error
A semiconductor integrated circuit device includes a gate electrode of at least one of a P-channel MISFET (metal-insulator-semiconductor field-effect transistor) and an N-channel MISFET provided in a direction parallel to a direction of a well isolation boundary phase between the P-channel MISFET and the N-channel MISFET, a first diffusion layer...

03/29/12 - 20120074492 - Method of fabricating a semicoductor device having a lateral double diffused mosfet transistor with a lightly doped source and a cmos transistor
Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described....

12/22/11 - 20110309441 - Integrated semiconductor device having an insulating structure and a manufacturing method
An integrated semiconductor device is provided. The integrated semiconductor device has a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type forming a pn-junction with the first semiconductor region, a non-monocrystalline semiconductor layer of the first conductivity type arranged on the second...

06/30/11 - 20110156144 - Compensated isolated p-well denmos devices
An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor...

06/23/11 - 20110147837 - Dual work function gate structures
A semiconductor chip having a transistor is described. The transistor having a gate electrode disposed over a gate dielectric. The gate electrode comprised of first gate material disposed on the gate dielectric and second gate material disposed on the gate dielectric. The first gate material being different than the second...

12/23/10 - 20100320537 - Semiconductor device and method of fabricating the same
Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device using a DMOS device includes: a semiconductor substrate, in which a first conductive type well is formed; a first conductive type gate electrode formed on the semiconductor substrate with a gate insulating layer intervening...

11/04/10 - 20100276752 - Monolithic output stage with verticle high-side pmos and verticle low-side nmos interconnected using buried metal, structure and method
A voltage converter can include an output circuit having a vertical high-side device and a vertical low-side device which can be formed on a single die (i.e. a “PowerDie”). The high side device can be a PMOS transistor, while the low side device can be an NMOS transistor. The source...

07/29/10 - 20100187606 - Semiconductor device that includes ldmos transistor and manufacturing method thereof
A manufacturing method of a semiconductor device including an LDMOS transistor includes: a process (a) of forming a first conductive well diffusion layer in the semiconductor substrate; a process (b) of sequentially forming a gate insulator film, a gate conductive film, and a photoresist film on a region on the...

04/29/10 - 20100102387 - Semicoductor device
An inventive semiconductor device includes a semiconductor layer, a source region provided in a surface layer portion of the semiconductor layer, a drain region provided in the surface of the semiconductor layer in spaced relation from the source region, a gate insulation film provided in opposed relation to a portion...

02/04/10 - 20100025761 - Design structure, structure and method of latch-up immunity for high and low voltage integrated circuits
Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic....

01/07/10 - 20100001342 - Method for manufacturing semiconductor device and semiconductor device
A method for manufacturing a semiconductor device is disclosed. The method includes: forming a LDMOS region, an offset drain MOS region, and a CMOS region; simultaneously forming a first well in the LDMOS region and the offset drain MOS region; simultaneously forming a second well in the first well of...

12/31/09 - 20090321825 - Semiconductor device and method for fabricating the same, bipolar-cmos-dmos and method for fabricating the same
A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial...

12/10/09 - 20090302383 - High-voltage transistor and component containing the latter
In a high-voltage NMOS transistor with low threshold voltage, it is proposed to realize the body doping that defines the channel region in the form of a deep p-well, and to arrange an additional shallow p-doping as a channel stopper on the transistor head, wherein this additional shallow p-doping is...

10/08/09 - 20090250753 - Semiconductor device and method of fabricating the same
Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device using a DMOS device includes: a semiconductor substrate, in which a first conductive type well is formed; a first conductive type gate electrode formed on the semiconductor substrate with a gate insulating layer intervening...

10/01/09 - 20090242982 - Self-aligned complementary ldmos
The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown...

09/17/09 - 20090230470 - Semiconductor device
Provided is a semiconductor device capable of easily setting a holding voltage with a low trigger voltage by locally forming a P-type diffusion layer between N-type source and drain diffusion layers of an NMOS transistor having a conventional drain structure used as an electrostatic protective element of the semiconductor device....

08/06/09 - 20090194815 - High voltage transistor
A high voltage transistor that includes a substrate where an active region is defined, a first impurity region and a second impurity region in the active region and a third impurity region between the first and second impurity regions, and a first gate electrode on the active region between the...

06/18/09 - 20090152626 - Super halo formation using a reverse flow for halo implants
Shrinking dimensions of MOS transistors in integrated circuits requires tighter distributions of dopants in pocket regions from halo ion implant processes. In conventional fabrication process sequences, halo dopant distributions spread during source/drain anneals. The instant invention is a method of fabricating MOS transistors in an integrated circuit in which halo...

03/05/09 - 20090057759 - Mos device and process having low resistance silicide interface using additional source/drain implant
An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a...