FREE patent keyword monitoring and additional FREE benefits. http://images1.freshpatents.com/images/triangleright (1K) REGISTER now for FREE triangleleft (1K)
FreshPatents.com Logo    FreshPatents.com icons
Monitor Keywords Patent Organizer File a Provisional Patent Browse Inventors Browse Industry Browse Agents


Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Short Channel Insulated Gate Field Effect Transistor > Active Channel Region Has A Graded Dopant Concentration Decreasing With Distance From Source Region (e.g., Double Diffused Device, Dmos Transistor)

Active Channel Region Has A Graded Dopant Concentration Decreasing With Distance From Source Region (e.g., Double Diffused Device, Dmos Transistor)

Active Channel Region Has A Graded Dopant Concentration Decreasing With Distance From Source Region (e.g., Double Diffused Device, Dmos Transistor) patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

07/24/14 - 20140203358 - Semiconductor device with enhanced 3d resurf
A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and...

07/17/14 - 20140197485 - Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate, and a gate electrode formed on the substrate on a gate insulation film. The semiconductor device also includes a source diffusion layer and a drain diffusion layer which are formed on the substrate where the gate electrode is sandwiched between the source diffusion layer...

07/03/14 - 20140183628 - Metal oxide semiconductor devices and fabrication methods
A semiconductor device includes a first well and a second well implanted in a semiconductor substrate. The semiconductor device further includes a raised drain structure above and in contact with the second well and separate from the gate structure. The raised drain structure includes a drain connection point above the...

06/12/14 - 20140159150 - Semiconductor device and semiconductor device manufacturing method
In aspects of the invention, an n-type epitaxial layer that forms an n− type drift layer is formed on the upper surface of an n-type semiconductor substrate formed by being doped with a high concentration of antimony. A p-type anode layer is formed on a surface of the n− type...

06/05/14 - 20140151792 - High voltage high side dmos and the method for forming thereof
A high voltage high side DMOS removing the N-buried layer from the DMOS bottom provides lower Ron*A at given breakdown voltage. The high voltage high side DMOS has a P-type substrate, an epitaxial layer, a field oxide, an N-type well region a gate oxide, a gate poly, a P-type base...

05/15/14 - 20140131795 - Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same
An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped...

05/08/14 - 20140124856 - Semiconductor device and fabricating method thereof
A semiconductor device including a semiconductor substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed thereon is disclosed. A well region of a second conductivity type is formed in the epitaxial structure and the semiconductor substrate. A drain region and a source region...

04/17/14 - 20140103429 - Method and structure to boost mosfet performance and nbti
The present disclosure provides one embodiment of a method forming a p-type field effect transistor (pFET) structure. The method includes forming a mask layer on a semiconductor substrate, the mask layer including an opening that exposes a semiconductor region of the semiconductor substrate within the opening; forming a n-type well...

04/17/14 - 20140103430 - Lateral high-voltage transistor and method for manufacturing the same
A lateral high-voltage transistor includes: a semiconductor substrate; a semiconductor layer being provided on one main surface of the semiconductor substrate; a source region being provided selectively in a surface of the semiconductor layer; a drain region being provided selectively in the surface of the semiconductor layer; a gate electrode...

04/03/14 - 20140091389 - High voltage metal-oxide-semiconductor transistor device
A high voltage metal-oxide-semiconductor transistor device includes a substrate having an insulating region formed therein, a gate covering a portion of the insulating region and formed on the substrate, a source region and a drain region formed at respective sides of the gate in the substrate, a body region formed...

03/27/14 - 20140084366 - Esd protection circuit
A device having a substrate defined with a device region is presented. The device region includes an ESD protection circuit having a transistor. The transistor includes a gate having first and second sides, a first diffusion region adjacent to the first side of the gate and a second diffusion region...

03/13/14 - 20140070311 - Semiconductor device and related fabrication methods
Semiconductor device structures and related fabrication methods are provided. An exemplary method of fabricating a semiconductor device on a doped region of semiconductor material having a first conductivity type involves forming a first region having a second conductivity type within the doped region, forming a body region having the first...

02/27/14 - 20140054693 - Semiconductor device
According to one embodiment, a first distance is a distance between both ends of the first insulating film in a direction connecting the fourth semiconductor layer and the sixth semiconductor layer. The first distance in the first region is longer than the first distance in the second region. A second...

02/13/14 - 20140042537 - Semiconductor device and method of making the same
A semiconductor device includes a drift region in a first region of a semiconductor body. The drift region includes dopants of a first conductivity type. A dopant retarding region is formed at least adjacent an edge of the drift region. Dopants of a second conductivity type are implanted into the...

02/06/14 - 20140035031 - Semiconductor device and method of fabricating the same
According to one embodiment, a semiconductor device, including a semiconductor layer including a first region and a second region isolated from the first region, a source in a surface of the first region, a drain in a surface of the second region, a back-gate in the surface of the source,...

01/23/14 - 20140021539 - Power transistor with high voltage counter implant
Presented herein is a field effect transistor device, optionally a lateral power transistor, and a method for forming the same, comprising providing a substrate, creating a doped buried layer, and creating a primary well in the substrate on the buried layer. A drift drain may be created in the primary...

01/16/14 - 20140015048 - Finfet with trench field plate
An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region...

12/26/13 - 20130341713 - Semiconductor devices and methods for manufacturing the same
Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, a method includes forming a first shielding layer on a substrate. The method further includes forming one of source and drain regions, which is stressed, with the first shielding layer as a mask. The method further includes...

12/26/13 - 20130341714 - Semiconductor device having power metal-oxide-semiconductor transistor
A semiconductor device includes a power metal-oxide-semiconductor (MOS) transistor including a semiconductor substrate, an impurity region on the semiconductor substrate, the impurity region having a first conductivity, a drift region in the impurity region, the drift region having the first conductivity, a body region in the impurity region adjacent to...

12/19/13 - 20130334598 - Semiconductor device and method for manufacturing same
A semiconductor device includes first to fourth semiconductor layers, a gate electrode, a field plate electrode, an insulating film, first and second main electrodes, and an insulating section. The second semiconductor layer has the first conductivity type and is provided on the first semiconductor layer. The third semiconductor layer has...

12/12/13 - 20130328123 - Semiconductor device
A semiconductor device includes a semiconductor substrate, a buried layer disposed in the semiconductor substrate; a deep well disposed in the semiconductor substrate; a first doped region disposed in the deep well, wherein the first doped region contacts the buried layer; a conductive region having the first conductivity type surrounding...

11/28/13 - 20130313639 - Semiconductor device
According to one embodiment, a semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of a second conductivity type provided on the semiconductor substrate, a second semiconductor layer of the first conductivity type provided on the first semiconductor layer, a first well of the...

11/21/13 - 20130307069 - Method for forming semiconductor layout patterns, semiconductor layout patterns, and semiconductor structure
A method for forming semiconductor layout patterns providing a pair of first layout patterns being symmetrical along an axial line, each of the first layout patterns comprising a first side proximal to the axial line and a second side far from the axial line; shifting a portion of the first...

11/14/13 - 20130299902 - Formation method and structure for a well-controlled metallic source/drain semiconductor device
A device and method for forming a semiconductor device include growing a raised semiconductor region on a channel layer adjacent to a gate structure. A space is formed between the raised semiconductor region and the gate structure. A metal layer is deposited on at least the raised semiconductor region. The...

11/07/13 - 20130292763 - Semiconductor devices having reduced on resistance
Semiconductor devices are provided including a substrate having a first conductivity type; a source region having a second conductivity type, different from the first conductivity type; a drain region, separate from the source region and having the second conductivity type; a body region having the first conductivity type and on...

10/10/13 - 20130264639 - Column iv transistors for pmos integration
Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibit reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain...

09/26/13 - 20130248998 - Semiconductor device
According to one embodiment, a semiconductor device includes, a drain, source, base and drift regions, a gate electrode, a gate insulating film, a first semiconductor region, a drain electrode, and a source electrode. The drain region has a first portion, and a second portion having a surface extending in a...

09/26/13 - 20130248999 - Contact resistance reduction employing germanium overlayer pre-contact metalization
Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such...

09/19/13 - 20130240989 - Selective germanium p-contact metalization through trench
Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such...

09/12/13 - 20130234246 - Semiconductor device with composite drift region
A device includes a semiconductor substrate, a channel region in the semiconductor substrate having a first conductivity type, and a composite drift region in the semiconductor substrate, having a second conductivity type. The composite drift region includes a first drift region and a second drift region spaced from the channel...

09/12/13 - 20130234247 - Lateral mosfet with dielectric isolation trench
A lateral trench MOSFET comprises a dielectric isolation trench formed over a silicon-on-insulator substrate. The lateral trench MOSFET further comprises a first drift region formed between a drain/source region and an insulator, and a second drift region formed between the dielectric isolation trench and the insulator. The dielectric trench and...

08/22/13 - 20130214352 - Dual gate lateral mosfet
A dual gate lateral MOSFET comprises a drift region over a substrate, an isolation region formed in the drift region and a channel region formed in the drift region. The dual gate lateral MOSFET comprises a drain region formed in the drift region and a source region formed in the...

07/18/13 - 20130181285 - Lateral dmos device with dummy gate
An LDMOS transistor with a dummy gate comprises an extended drift region formed over a substrate, a drain region formed in the extended drift region, a channel region formed in the extended drift region, a source region formed in the channel region and a dielectric layer formed over the extended...

07/18/13 - 20130181286 - High voltage device
A method of forming a device is presented. The method includes providing a substrate having a device region which includes a source region, a gate and a drain region defined thereon. The method also includes implanting the gate. The gate comprises one or more doped portions with different dopant concentrations....

07/18/13 - 20130181287 - High voltage device
A method of forming a device is disclosed. A substrate having a device region is provided. The device region comprises a source region, a gate and a drain region defined thereon. A drift well is formed in the substrate adjacent to a second side of the gate. The drift well...

07/04/13 - 20130168766 - Drain extended mos transistor and method for fabricating the same
A drain extended MOS (DEMOS) transistor including at least one of: (1) A p-type epitaxial layer grown over an n-type semiconductor substrate. (2) An n-type well formed in a portion of the epitaxial layer. (3) A p-type drift region formed in another portion of the epitaxial layer. (4) A p-type...

06/13/13 - 20130146973 - Customized shield plate for a field effect transistor
A customized shield plate field effect transistor (FET) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the...

06/13/13 - 20130146974 - Semiconductor devices and methods of forming the same
A method of forming a semiconductor device is provided. The method includes preparing a substrate having a transistor region and an alignment region, forming a first trench and a second trench in the substrate of the transistor region and in the substrate of the alignment region, respectively, forming a drift...

06/06/13 - 20130140632 - Lateral transistor component and method for producing same
A transistor component includes an active transistor region arranged in the semiconductor body. And insulation region surrounds the active transistor region in the semiconductor body in a ring-shaped manner. A source zone, a drain zone, a body zone and a drift zone are disposed in the active transistor region. The...

05/30/13 - 20130134509 - Semiconductor device arrangement comprising a semiconductor device with a drift region and a drift control region
A semiconductor device includes a source region, a drain region, a body region, and a drift region. The drift region is arranged between the body and the drain and the body is arranged between the source and the drift region in a semiconductor body. A gate electrode is adjacent the...

05/23/13 - 20130126968 - High voltage semiconductor device
A high voltage semiconductor device is provided. A first-polarity buried layer is formed in the substrate. A first high voltage second-polarity well region is located over the first-polarity buried layer. A second-polarity base region is disposed within the first high voltage second-polarity well region. A source region is disposed within...

05/23/13 - 20130126969 - Lateral double diffusion metal-oxide semiconductor device and method for manufacturing the same
Disclosed is an LDMOS device, which is configured to reduce an electric field concentrated to a gate oxide film and lower an ON-resistance produced when the device conducts a forward action, and a method for manufacturing the same. More specifically, when an n-drift region is formed on a P-type substrate,...

05/23/13 - 20130126970 - Configuration and fabrication of semiconductor structure using empty and filled wells
A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of...

05/09/13 - 20130113041 - Semiconductor transistor device with optimized dopant profile
Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation...

05/02/13 - 20130105892 - Laterally diffused metal oxide semiconductor transistor for radio frequency power amplifier and method therefor
A lateral diffused metal oxide semiconductor (LDMOS) transistor is provided. The LDMOS transistor includes a substrate having a source region, channel region, and a drain region. A first implant is formed to a first depth in the substrate. A gate electrode is formed over the channel region in the substrate...

04/25/13 - 20130099312 - Semiconductor structure having a through substrate via (tsv) and method for forming
A semiconductor device structure includes a substrate having a background doping of a first concentration and of a first conductivity type. A through substrate via (TSV) is through the substrate. A device has a first doped region of a second conductivity on a first side of the substrate. A second...

04/18/13 - 20130093009 - Method of manufacturing nmos transistor with low trigger voltage
A method for forming an NMOS transistor includes forming a P-substrate; forming an N-well on the P-substrate; forming an N-drift region on the N-well; forming an n+ drain on the N-drift region; forming a plurality of first contacts on the n+ drain along a longitudinal direction; forming a P-body on...

04/18/13 - 20130093010 - High-voltage mosfets having current diversion region in substrate near fieldplate
To limit or prevent current crowding, various HV-MOSFET embodiments include a current diversion region disposed near a drain region of an HV-MOSFET and near an upper surface of the semiconductor substrate. In some embodiments, the current diversion region is disposed near a field plate of the HV-MOSFET, wherein the field...

04/18/13 - 20130093011 - High voltage device and manufacturing method thereof
The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a substrate. The high voltage device includes: a gate, a source and drain, a drift region, and a mitigation region. The gate is formed on an upper surface of the...

04/18/13 - 20130093012 - High voltage device
A method of forming a device is disclosed. The method includes providing a substrate having a device region. The device region includes a source region, a gate region and a drain region defined thereon. The substrate is prepared with gate layers on the substrate. The gate layers are patterned to...

04/18/13 - 20130093013 - High voltage transistor and manufacturing method therefor
A high-voltage transistor may include a semiconductor substrate, and a gate electrode formed on and/or over the semiconductor substrate. Further, the high-voltage transistor may include source/drain regions formed on and/or over the semiconductor substrate at one side of the gate electrode, and impurity layers having a super junction structure and...