REGISTER now for FREE 
|
FREE patent keyword monitoring and additional FREE benefits. REGISTER now for FREE
|
|
|
Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Short Channel Insulated Gate Field Effect Transistor Short Channel Insulated Gate Field Effect TransistorShort Channel Insulated Gate Field Effect Transistor patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.12/13/07 - 20070284655 - Semiconductor device and method for fabricating the same A semiconductor device includes a device isolation structure formed on a semiconductor substrate to define an active region. A first Si-based epitaxial pattern is formed over the active region corresponding to a bit line contact region and a portion of a gate region at both sides adjacent to the bit ... 11/22/07 - 20070267690 - Dmosfet with current injection This invention disclosed a novel method for the reduction the resistance of the drift region by using the minority carrier current injector near the drift region. This current injector is a p-n junction or a p-n junction in connection with a resistor to the gate or the p-n junction in ... 10/04/07 - 20070228458 - Dual metal integration scheme based on full silicidation of the gate electrode An integration scheme that enables full silicidation (FUSI) of the nFET and pFET gate electrodes at the same time as that of the source/drain regions is provided. The FUSI of the gate electrodes eliminates the gate depletion problem that is observed with polysilicon gate electrodes. In addition, the inventive integration ... 09/27/07 - 20070221988 - Charge trapping device and method of producing the charge trapping device A charge-trapping device includes a field effect transistor, which has source and drain regions. The source and drain regions have a dopant concentration profile, which has a gradient each in a vertical and a lateral direction with respect to a surface of a semiconductor substrate. The gradient in the lateral ... 09/20/07 - 20070215936 - Diffusion topography engineering for high performance cmos fabrication Semiconductor structures are formed using diffusion topography engineering (DTE). A preferred method includes providing a semiconductor substrate, forming trench isolation regions that define a diffusion region, performing a DTE in a hydrogen-containing ambient on the semiconductor substrate, and forming a MOS device in the diffusion region. The DTE causes silicon ... 09/06/07 - 20070205460 - Nonvolatile memory devices and methods of forming the same Embodiments herein present device, method, etc. for a hybrid orientation scheme for standard orthogonal circuits. An integrated circuit of embodiments of the invention comprises a hybrid orientation substrate, comprising first areas having a first crystalline orientation and second areas having a second crystalline orientation. The first crystalline orientation of the ... 07/12/07 - 20070158739 - Higher performance cmos on (110) wafers A semiconductor (e.g., complementary metal oxide semiconductor (CMOS)) structure formed on a (110) substrate that has improved performance, in terms of mobility enhancement is provided. In accordance with the present invention, the inventive structure includes at least one of a single tensile stressed liner, a compressively stressed shallow trench isolation ... 07/05/07 - 20070152266 - Method and structure for reducing the external resistance of a three-dimensional transistor through use of epitaxial layers The fabrication of a tri-gate transistor formed with a replacement gate process is described. A nitride dummy gate, in one embodiment, is used allowing the growth of epitaxial source and drain regions immediately adjacent to the dummy gate. This reduces the external resistance. ... 06/14/07 - 20070132012 - Semiconductor device A semiconductor device includes: a semiconductor layer of a first conductivity type; a plurality of first cylindrical semiconductor pillar regions of the first conductivity type periodically provided on a major surface of the semiconductor layer; a plurality of second cylindrical semiconductor pillar regions of a second conductivity type provided on ... 05/17/07 - 20070108510 - Process for production of soi substrate and process for production of semiconductor device A process for producing an adhered SOI substrate without causing cracking and peeling of a single-crystal silicon thin film. The process consists of selectively forming a porous silicon layer in a single-crystal semiconductor substrate, adding hydrogen into the single-crystal semiconductor substrate to form a hydrogen-added layer, adhering the single-crystal semiconductor ... 05/10/07 - 20070102757 - Semiconductor device and a method of manufacturing the same To reduce the size and improve the power added efficiency of an RF power module having an amplifier element composed of a silicon power MOSFET, the on resistance and feedback capacitance, which were conventionally in a trade-off relationship, are reduced simultaneously by forming the structure of an offset drain region ... 05/10/07 - 20070102756 - Finfet transistor fabricated in bulk semiconducting material A field effect transistor (FET) device structure and method for forming FETs for scaled semiconductor devices. Specifically, FinFET devices are fabricated from bulk semiconductor wafers, as opposed to silicon-on-insulator (SOI) or separation by implantation of oxygen (SIMOX) wafers, in a highly uniform and reproducible manner. The method facilitates formation of ... 04/26/07 - 20070090451 - Lateral dmos transistors including retrograde regions therein and methods of fabricating the same A metal-oxide semiconductor transistor includes a semiconductor substrate including a source region and a drain region adjacent a surface of the substrate and a drift region between the source region and the drain region. The drift region has an impurity concentration distribution such that a peak impurity concentration of the ... 03/29/07 - 20070069285 - Semiconductor device and method for fabricating the same A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed in the upper part of the semiconductor substrate so as to be spaced; a channel region formed in a part of the semiconductor substrate between the source region and the drain region; a first dielectric ... 03/15/07 - 20070057321 - Semiconductor device In a semiconductor device of the present invention, a MOS transistor is disposed in an elliptical shape. Linear regions in the elliptical shape are respectively used as the active regions, and round regions in the elliptical shape is used respectively as the inactive regions. In each of the inactive regions, ... 03/15/07 - 20070057320 - Semiconductor devices with stressed channel regions and methods forming the same A semiconductor device includes a substrate having a semiconductor channel region therein. A gate electrode is provided on the channel region. A SiGeC stress-inducing region is provided adjacent the channel region. The SiGeC region is configured to form a semiconductor junction with the channel region and induce a net mobility-enhancing ... 02/15/07 - 20070034940 - Mos semiconductor device A semiconductor device comprises a gate electrode provided on a gate insulating film, a side wall insulating film provided on a side wall of the gate electrode through a protection insulating film, a barrier SiN film provided to cover the gate electrode and the side wall insulating film, an inter-level ... 02/08/07 - 20070029608 - Offset spacers for cmos transistors An offset spacer for CMOS transistors and a method of manufacture is provided. A gate electrode is formed on a substrate, and an offset mask layer is formed over the surface of the gate electrode and the substrate. The offset mask may be formed of an oxide layer and acts ... 02/01/07 - 20070023826 - Vertical-type metal insulator semiconductor field effect transistor device, and production method for manufacturing such transistor device In a vertical-type metal insulator field effect transistor device having a first conductivity type drain region layer, a plurality of second conductivity type base regions are produced and arranged in the first conductivity type drain region layer, and a first conductivity type source region is produced in each of the ... 02/01/07 - 20070023825 - Semiconductor device A semiconductor device having: a semiconductor layer; an interlayer dielectric formed on the semiconductor layer; a buffer layer formed on the interlayer dielectric; and an electrode pad formed on the interlayer dielectric, the buffer layer being formed to be covered by an edge portion of at least part of the ... 01/25/07 - 20070018238 - Semiconductor device A semiconductor device includes a semiconductor layer, a pair of a source region and a drain region formed to face each other in a direction on the semiconductor layer and made of a metal or a metal silicide, a first dielectric film formed on at least the semiconductor layer between ... 01/18/07 - 20070012994 - Semicondutor device and manufacturing method thereof A semiconductor device is provided. The semiconductor device has a gate structure, a source region, a drain region, and a pair of dielectric barrier layers. The gate structure is formed on a substrate. The source region and the drain region are formed in the substrate next to the gate structure, ... 01/04/07 - 20070001219 - Block contact architectures for nanoscale channel transistors A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch. ... 12/14/06 - 20060278920 - Metal oxide semiconductor field-effect transistor (mosfet) and method of fabricating the same A Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) is provided. The MOSFET includes a semiconductor substrate, a device isolating region disposed on a predetermined portion of the semiconductor substrate to define an active region, a source region and a drain region spaced apart from each other about a channel region within ... 11/30/06 - 20060267081 - Semiconductor device and method of manufacturing the same by using atomic layer deposition A method of manufacturing a semiconductor device by using atomic layer deposition includes depositing a silicon atomic layer film on a semiconductor substrate. The method may also include forming an epitaxial silicon film on the silicon atomic layer film by using the silicon atomic layer film as a seed layer. ... 11/09/06 - 20060249784 - Field effect transistor device including an array of channel elements and methods for forming The present invention relates to a semiconductor structure such as a field effect transistors (FETs) in which the channel region of each of the FETs is composed of an array of more than one electrically isolated channel. In accordance with the present invention, the distance between each of the channels ... 11/09/06 - 20060249783 - Ultrascalable vertical mos transistor with planar contacts A doped silicon block or island, formed above a drain electrode in substrate of a die or chip, has a height corresponding to the desired length of a channel. A source electrode is formed above the silicon island and allows for contact from above. Contact from above may also be ... 11/02/06 - 20060244052 - Short-channel schottky-barrier mosfet device and manufacturing method A MOSFET device and method of fabricating is provided. The MOSFET device and method of fabricating utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a MOSFET device structure to eliminate the requirement for halo/pocket implants and shallow source/drain extensions to control short channel effects. ... 11/02/06 - 20060244051 - Semiconductor manufacturing method and semiconductor device A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the ... 09/21/06 - 20060208313 - Double gate fet and fabrication process A method of fabricating a double gate FET on a silicon substrate includes the steps of sequentially epitaxially growing a lower gate layer of crystalline rare earth silicide material on the substrate, a lower gate insulating layer of crystalline rare earth insulating material, an active layer of crystalline semiconductor material, ... 09/14/06 - 20060202262 - Semiconductor device and method for manufacturing the same A semiconductor device and a method for manufacturing the same are provided. A gate insulating film is formed under a vacuum condition to prevent deterioration of reliability of the device due to degradation of a gate insulating material and to have stable operating characteristics. The semiconductor device includes an element ... 07/27/06 - 20060163647 - Mos semiconductor device While using conventional manufacturing processes, it is intended to apply a compressive strain in the channel direction to the p-channel MOS field effect transistor and also apply a tensile strain in the channel direction to the n-channel MOS field effect transistor for increasing both MOS currents. In the MOS semiconductor ... 07/13/06 - 20060151829 - Semiconductor device and a method for manufacturing therefor An object of the present invention is to provide a semiconductor device capable of radiating electron-beams only to a desired region without forming a layer for restricting the radiating rays. A source electrode 22 made of aluminum prevents the generation of bremsstrahlung even when the electron-beams are radiated to the ... 07/13/06 - 20060151828 - Semiconductor device In a semiconductor device in which gate trenches and source trenches are formed, when the semiconductor device is flatly viewed, N+ type source areas are formed in parallel with the gate trenches to ease the miniaturization of the semiconductor device. P+ type diffusion areas are separately formed in a direction ... 07/06/06 - 20060145245 - Field-effect transistor, its manufacturing method, and complementary field-effect transistor A field effect transistor comprises: a semiconductor substrate; a semiconductor layer provided on the semiconductor substrate, the semiconductor layer including a body region which contains an impurity of a first conductivity type; a gate dielectric film provided on the semiconductor layer; a gate electrode provided on the gate dielectric film; ... 06/29/06 - 20060138531 - Method for fabricating vertical cmos image sensor A method of fabricating a vertical CMOS image sensor is disclosed, to improve the integration with the decrease in size of pixel by minimizing the lateral diffusion, in which phosphorous and arsenic ions are implanted while controlling the dose and energy, the method including forming a first photodiode in a ... 04/20/06 - 20060081917 - Method for forming a hard mask for gate electrode patterning and corresponding device A method for forming a hard mask for gate electrode patterning in a semiconductor device is disclosed. The method includes providing a polysilicon layer to be etched and forming over the polysilicon layer, a nitride hardmask with a relatively high etch rate to hydrofluoric acid, as compared to the etch ... 04/06/06 - 20060071267 - Power semiconductor device where t is the thickness of the first semiconductor layer, and d is the thickness of the second semiconductor layer. ... 03/16/06 - 20060054969 - Semiconductor device having a junction extended by a selective epitaxial growth (seg) layer and method of fabricating the same In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a protrusion extending from a substrate and a selective epitaxial growth (SEG) layer surrounding an upper portion of the protrusion, the SEG layer exposing sidewalls of a channel region of the protrusion. ... 03/16/06 - 20060054968 - Thin channel mosfet with source/drain stressors Methods of manufacturing microelectronic device including, in one embodiment, forming a gate electrode over a substrate having an insulating layer interposing a bulk semiconductor portion and a thin semiconductor layer, and removing at least a portion of the thin semiconductor and insulating layers, thereby defining a pedestal comprising a portion ... 03/16/06 - 20060054967 - Integrated half-bridge power circuit A down converter includes an integrated circuit, which includes a control FET (CF) and a synchronous rectifier FIT (SF). The control FET is a lateral double-diffused (LDMOS) FET, and the conductivity-type of the LDMOS FET and the conductivity-type of the substrate are of the same type. ... 03/02/06 - 20060043470 - Method for producing a buried n-doped semiconductor zone in a semiconductor body and semiconductor component A method for producing a buried n-doped semiconductor zone in a semiconductor body. In one embodiment, the method includes producing an oxygen concentration at least in the region to be doped in the semiconductor body. The semiconductor body is irradiated via one side with nondoping particles for producing defects in ... 02/09/06 - 20060027860 - Field-effect transistor A field-effect transistor is provided. The field-effect transistor includes a gate electrode, a gate-insulating layer, source/drain electrodes, and an organic semiconductor layer constituting a channel region. The source/drain electrodes each include a conductive portion composed of a metal and an organic conductive material layer which at least partially covers the ... 02/02/06 - 20060022261 - Insulated gate semiconductor device and method of making the same The invention further relates to an insulated gate semiconductor device, comprising a semiconductor substrate (1) having an essentially planar top surface and an insulated gate formed on the top surface by a layered structure (2) that comprises at least one electrically insulating layer (22), wherein at least one strip (41, ... 12/29/05 - 20050285186 - Semiconductor device and method of fabricating the same According to the present invention, there is provided a semiconductor device comprising: a semiconductor layer formed on a semiconductor substrate via a first insulating film and having a projecting shape; a second insulating film formed on said first insulating film, and having a film thickness by which said semiconductor layer ... 12/22/05 - 20050280076 - Method for production of a buried stop zone in a semiconductor component and semiconductor component comprising a buried stop zone A method for the production of a stop zone in a doped zone of a semiconductor body having a first side and a second side, comprises the following method steps: applying a mask having cutouts to one of the sides of the semiconductor body, irradiating the side having the mask ... 12/08/05 - 20050269629 - Fin field effect transistors and methods of fabricating the same A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a ... 11/24/05 - 20050258477 - Semiconductor device and method of manufacturing the same According to the present invention, there is provided a semiconductor device manufacturing method comprising: depositing a semiconductor layer and mask material in order over a semiconductor substrate on an insulating film; patterning the semiconductor layer and mask material to form a semiconductor layer in a predetermined region; removing a surface ... 11/24/05 - 20050258476 - Planarizing method for forming fin-fet device A method for forming a FIN-FET device employs a blanket planarizing layer formed upon a blanket topographic gate electrode material layer. The blanket planarizing layer is patterned and employed as a mask layer for patterning the blanket topographic gate electrode material layer to form a gate electrode. Since the blanket ... 10/13/05 - 20050224867 - Slim spacer device and manufacturing method A CMOS structure including a Slim spacer and method for forming the same to reduce an S/D electrical resistance and improve charge mobility in a channel region, the method including providing a semiconductor substrate including a polysilicon gate structure including at least one overlying hardmask layer; forming spacers selected from ... 09/22/05 - 20050205925 - Semiconductor device and method for manufacturing the same A semiconductor device includes a dielectric layer, a semiconductor layer provided above the dielectric layer, a gate dielectric layer provided above the semiconductor layer, a gate electrode provided above the gate dielectric layer, a source region and a drain region provided in the semiconductor layer, a body region other than ... 09/15/05 - 20050199948 - Fin field effect transistors with epitaxial extension layers and methods of forming the same A fin field-effect transistor (FinFET) device includes a fin-shaped semiconductor active region vertically protruding from a substrate and a gate structure on an upper surface and sidewalls of the fin-shaped semiconductor active region at a first portion thereof. The FinFET further includes a semiconductor epitaxial extension layer on the upper ... 09/01/05 - 20050189583 - Field effect transistors having multiple stacked channels Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate ... 08/25/05 - 20050184335 - Semiconductor device and fabricating method thereof A semiconductor device and fabricating method thereof in which a lightly doped drain junction is graded using a diffusion property of dopant implanted in heavily doped source/drain region are disclosed. An example semiconductor device includes a gate electrode having a gate insulating layer underneath and disposed on a semiconductor substrate; ... 08/04/05 - 20050167739 - Semiconductor device An electrostatic discharge protected transistor of the present invention includes transistors in an active region composed of a p-type semiconductor substrate and surrounded by element isolation regions. On the active region composed of the p-type semiconductor substrate, an on-source silicide film and an on-drain silicide film are provided. The on-drain ... 08/04/05 - 20050167738 - Semiconductor device and manufacturing method of the same A semiconductor device and a method for manufacturing the semiconductor device capable of reducing a short channel effect are provided. The semiconductor device is made up of a pair of impurity regions for a source and a drain formed on a semiconductor substrate, a gate having a gate electrode used ... 07/28/05 - 20050161732 - Semiconductor device A semiconductor device includes a semiconductor substrate of a first conductivity type, a lightly-doped semiconductor layer of the first conductivity type formed on the first major surface of the substrate, a first semiconductor region of the first conductivity type formed on an island-shaped region on the lightly-doped semiconductor layer, a ... 07/21/05 - 20050156230 - Output prediction logic circuits with ultra-thin vertical transistors and methods of formation Very fast integrated OPL circuits, such as pseudo-NMOS OPL and dynamic OPL, comprising CMOS gate arrays having ultra-thin vertical NMOS transistors are disclosed. The ultra-thin vertical NMOS transistors of the CMOS gate arrays are formed with relaxed silicon germanium (SiGe) body regions with graded germanium content and strained silicon channels. ... 07/21/05 - 20050156229 - Integrated circuit device and method therefor A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that ... 07/14/05 - 20050151186 - Semiconductor device ON resistance and leakage current of a vertical power MOSFET are to be diminished. In a vertical high breakdown voltage MOSFET with unit MOSFETs (cells) arranged longitudinally and transversely over a main surface of a semiconductor substrate, the cells are made quadrangular in shape, and in each of the cells, ... 07/07/05 - 20050145931 - Semiconductor device and fabricating method thereof The present invention provides a semiconductor device and fabricating method thereof, by which dislocation is previously prevented from occurring between a spacer and a substrate. The present invention includes forming a gate having a gate insulating layer underneath on a semiconductor substrate, forming a pair of lightly doped regions in ... 07/07/05 - 20050145930 - High voltage drain-extended transistor The present invention provides, in one embodiment, a transistor (100). The transistor (100) comprises a doped semiconductor substrate (105) and a drain-extended well (115) having a curved region (125) and a straight region (130) surrounded by the doped semiconductor substrate (105). The drain-extended well (115) has an opposite dopant type ... 06/30/05 - 20050139908 - Semiconductor device A semiconductor device includes: a silicon substrate, having a main surface, in which trenches are formed; element isolation oxide films filling in trenches; a tunnel oxide film, formed on main surface located between element isolation oxide film and element isolation oxide film, having birds beak portions in birds beak forms ... 06/30/05 - 20050139907 - Semiconductor device and manufacturing method therefor The present invention provides a semiconductor device that permits free setting of characteristics of individual semiconductor elements which are mixedly mounted and have different characteristics, and is free of steps between formed semiconductor elements, and a manufacturing method for the same. In the semiconductor device, an n-type silicon layer is ... 06/30/05 - 20050139906 - Vertical-conduction and planar-structure mos device with a double thickness of gate oxide and method for realizing power vertical mos transistors with improved static and dynamic performances and high scaling down density A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the ... 06/23/05 - 20050133858 - High-voltage vertical transistor with a multi-gradient drain doping profile A high-voltage transistor includes first and second trenches that define a mesa in a semiconductor substrate. First and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members being separated from the mesa by a dielectric layer. ... 06/23/05 - 20050133857 - Power semiconductor component having a gentle turn-off behavior A vertical semiconductor component having a semiconductor body, which has an inner region and an edge region that is arranged between the inner region and an edge of the semiconductor body. At least one semiconductor junction between a first semiconductor zone of a first conduction type, said first semiconductor zone ... 06/23/05 - 20050133856 - Vertical-type metal insulator semiconductor field effect transistor device, and production method for manufacturing such transistor device In a vertical-type metal insulator field effect transistor device having a first conductivity type drain region layer, a plurality of second conductivity type base regions are produced and arranged in the first conductivity type drain region layer, and a first conductivity type source region is produced in each of the ... 06/23/05 - 20050133855 - Semiconductor component arrangement with a defect identification circuit the defect identification circuit (110) being arranged adjacent to the at least one semiconductor switching element (M), comprising a temperature sensor (DS) and also an evaluation circuit (AWS) and being designed to make a defect signal (DS) available in the event of a temperature indicating a defect in the at ... 06/23/05 - 20050133854 - Semiconductor device having pad structure for preventing and buffering stress of silicon nitride film The present invention discloses a semiconductor device having a pad structure for preventing a stress of a silicon nitride film. The semiconductor device includes a semiconductor substrate, a lower structure formed on the semiconductor substrate, a first insulation film formed on the lower structure, a first metal layer coupled to ... 06/16/05 - 20050127436 - Method for forming a notched gate insulator for advanced mis semiconductor devices and devices thus obtained Methods of providing a semiconductor device with a control electrode structure having a controlled overlap between control electrode and first and second main electrode extensions without many spacers are disclosed. A preferred method provides a step of etching back an insulating layer performed after amorphizing and implanting the main electrode ... 06/16/05 - 20050127435 - Method of forming self-aligned poly for embedded flash A method of manufacturing a microelectronic device including, in one embodiment, providing a substrate having a plurality of partially completed microelectronic devices including at least one partially completed memory device and at least one partially completed transistor. At least a portion of the partially completed transistor is protected by forming ... 06/16/05 - 20050127434 - Mos power component with a reduced surface area A MOS power component in which the active regions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof. A MOS power transistor according to the present invention alternately includes a source region of a first conductivity type, an intermediary region, and a drain region ... 06/16/05 - 20050127433 - Recessed gate structure with reduced current leakage and overlap capacitance A gate structure and method for forming the same the method including providing a silicon substrate including one of N and P-well doped regions and an overlying the CVD silicon oxide layer; forming an opening in the CVD silicon oxide layer to include a recessed area extending into a thickness ... 06/16/05 - 20050127432 - Semiconductor device having substantially planar contacts and body A method of manufacturing a semiconductor device, wherein a gate structure is formed over a substrate, an interconnect layer is formed over the gate structure and the substrate, and a cap layer is formed over the interconnect layer. The interconnect layer and the cap layer are then planarized to form ... 06/02/05 - 20050116283 - Semiconductor device In conventional semiconductor devices, there observed a problem that cells on the devices may not function uniformly because of voltage drop in a main wiring layer due to a uniform and narrow width of the main wiring layer through which a main current flows. In a semiconductor device of the ... 06/02/05 - 20050116282 - Closed cell trench metal-oxide-semiconductor field effect transistor Embodiments of the present invention provide an improved closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET). The closed cell TMOSFET comprises a drain, a body region disposed above the drain region, a gate region disposed in the body region, a gate insulator region, a plurality of source regions disposed at ... ### FreshPatents.com Support |