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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Variable Threshold (e.g., Floating Gate Memory Device) > Multiple Insulator Layers (e.g., Mnos Structure) Multiple Insulator Layers (e.g., Mnos Structure)Multiple Insulator Layers (e.g., Mnos Structure) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/03/08 - 20080001212 - Non-volatile semiconductor memory devices A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater ... 12/27/07 - 20070296026 - Sonos memory device A SONOS memory device, and a method of manufacturing the same, includes a substrate and a multifunctional device formed on the substrate. The multifunctional device performs both switching and data storing functions. The multifunctional device includes first and second impurities areas, a channel formed between the first and second impurities ... 12/27/07 - 20070296025 - Random number generating device A random number generating device includes a semiconductor device including a source region, a drain region, a channel region provided between the source region and the drain region, and an insulating portion provided on the channel region, the insulating portion including a trap insulating film having traps based on dangling ... 11/22/07 - 20070267689 - One-transistor composite-gate memory One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more ... 11/15/07 - 20070262374 - Semiconductor memory device and manufacturing method thereof After an ONO film in which a silicon nitride film (22) formed by a plasma nitriding method using a plasma processor having a radial line slot antenna is sandwiched by silicon oxide films (21), (23), a bit line diffusion layer (17) is formed in a memory cell array region (11) ... 11/08/07 - 20070257307 - Nand non-volatile two-bit memory and fabrication method A NAND non-volatile two-bit memory cell comprises a cell stack and two select stacks disposed on an active area of a substrate. Each select stack is respectively disposed on a side of the cell stack with a sidewall between the cell stack and a respective select stack. The cell stack ... 09/13/07 - 20070210373 - Semiconductor device and method of manufacturing the same A semiconductor device includes a bit line that is provided in a semiconductor substrate, a silicide layer that has side faces and a bottom face surrounded by the bit line and is provided within the bit line, an ONO film that is provided on the semiconductor substrate, and sidewalls that ... 08/30/07 - 20070200168 - Monos type nonvolatile memory cell, nonvolatile memory, and manufacturing method thereof A MONOS type nonvolatile memory cell is structured such that a laminated insulating film which is formed by sequentially laminating a tunnel insulating layer, a charge storage insulating layer, and a charge block insulating layer is provided on a convex curved surface portion of a semiconductor substrate, and a control ... 08/30/07 - 20070200167 - Nonvolatile semiconductor storage device and manufacturing method thereof An object of the present invention is to provide a nonvolatile semiconductor storage device with a superior charge holding characteristic in which highly-efficient writing is possible at low voltage, and to provide a manufacturing method thereof. The nonvolatile semiconductor storage device includes a semiconductor film having a pair of impurity ... 08/02/07 - 20070176227 - Mos device with nano-crystal gate structure Methods and apparatus are provided for non-volatile semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate ... 08/02/07 - 20070176226 - Memory cell using a dielectric having non-uniform thickness A memory cell is programmed by injecting charge into a charge storage layer of the memory cell. A desired programmed charge results in the charge storage layer over an edge portion of a channel region of the memory cell. An undesired programmed charge results in the charge storage layer over ... 07/26/07 - 20070170496 - Nrom flash memory devices on ultrathin silicon An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on ... 07/19/07 - 20070164352 - Multi-bit-per-cell nvm structures and architecture A transistor structure, such as a Double-gated FET (DG FET), that has been modified to include a charge-trapping region used to store either 2- or 4-bits of information. The charge-trapping region can, for example, be embedded in the gate dielectric stack underneath each gate electrode, or placed on the sidewalls ... 07/05/07 - 20070152265 - Semiconductor memory device and method for manufacturing the same A semiconductor memory device includes: a memory cell array region formed in a semiconductor region of a first conductivity type and having a plurality of memory cells arranged in rows and columns; a plurality of word lines each of which collectively connects ones of the plurality of memory cells aligned ... 06/21/07 - 20070138541 - Method of erasing data from sonos memory device A SONOS memory device, and a method of erasing data from the same, includes injecting charge carriers of a second sign into a trapping film, which traps charge carriers of a first sign to store data therein. The charge carriers of the second sign are generated by an electric field ... 06/21/07 - 20070138540 - Group iii nitride based compound semiconductor optical device An object of the invention is to prevent defoliation of a first electrode layer of the device of the invention including a high-reflectance metal layer. In the group III nitride based compound semiconductor optical device of the invention, an electrode formed on a p-type layer has a first electrode layer ... 06/21/07 - 20070138539 - Non-volatile memory device having a nitride-oxide dielectric layer A non-volatile memory cell may include a semiconductor substrate; a source region in a portion of the substrate; a drain region within a portion of the substrate; a well region within a portion of the substrate. The memory cell may further include a first carrier tunneling layer over the substrate; ... 06/14/07 - 20070132011 - Semiconductor device and method of fabricating the same background A semiconductor device includes a semiconductor layer formed on a semiconductor substrate by epitaxial growth, a first embedded insulating layer embedded in a first region between the semiconductor substrate and the substrate layer, and a second embedded insulating layer embedded in a second region between the semiconductor substrate and the ... 06/14/07 - 20070132010 - Enhanced multi-bit non-volatile memory device with resonant tunnel barrier A non-volatile memory cell uses a resonant tunnel barrier that has an amorphous silicon and/or amorphous germanium layer between two layers of either HfSiON or LaAlO3. A charge trapping layer is formed over the tunnel barrier. A high-k charge blocking layer is formed over the charge trapping layer. A control ... 06/07/07 - 20070126054 - Nonvolatile memory devices having insulating spacer and manufacturing method thereof A nonvolatile memory device that effectively prevents the occurrence of the hump phenomenon as well as a manufacturing method for fabricating the same, is presented. In one embodiment, the nonvolatile memory device includes an insulating spacer formed at interface between the active region and isolation layer, and a charge trapping ... 06/07/07 - 20070126053 - Non-volatile memory array structure A memory array having a smaller active area pitch is provided. In accordance with embodiments of the present invention, active regions are formed in a substrate and transistors are formed between adjacent active regions such that the active regions form the source/drain regions of the transistors. Word lines are formed ... 06/07/07 - 20070126052 - Method and apparatus for strapping the control gate and the bit line of a monos memory array A method of manufacturing a non-volatile semiconductor memory. The method includes forming a word gate poly layer on a substrate, wherein an upper surface of the substrate defines a plane of the substrate. The method also includes forming a first dielectric layer coupled to the word gate poly layer and ... 05/31/07 - 20070120180 - Transition areas for dense memory arrays A non-volatile memory chip has word lines spaced a sub-F (sub-minimum feature size F) width apart with extensions of the word lines in at least two transition areas. Neighboring extensions are spaced at least F apart. The present invention also includes a method for word-line patterning of a non-volatile memory ... 05/31/07 - 20070120179 - Sonos type non-volatile memory devices having a laminate blocking insulation layer and methods of manufacturing the same A SONOS type non-volatile memory device includes a substrate having source/drain regions doped with impurities and a channel region between the source/drain regions. A tunnel insulation layer including silicon oxide is formed on the channel region of the substrate. A charge-trapping insulation layer including silicon nitride is formed on the ... 05/24/07 - 20070114597 - Twin insulator charge storage device operation and its fabrication method The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be ... 05/24/07 - 20070114596 - Integrated electronic circuit incorporating a capacitor A non-volatile memory element includes a transistor for selecting the element and a capacitor for recording a binary value by electrical breakdown of an insulating layer (13) of the capacitor. A structure of the memory element is modified in order to allow a higher degree of integration of the element ... 05/17/07 - 20070108509 - Semiconductor memory and method for manufacturing the same A semiconductor memory is provided with memory cells including bit lines made of a diffusion layer formed in a semiconductor substrate, charge-trapping gate insulating films formed between the bit lines and word lines formed on the gate insulating films. An interlayer insulating film is formed over the memory cells and ... 05/17/07 - 20070108508 - Single-poly non-volatile memory device A single-poly, P-channel non-volatile memory (NVM) cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layers on ... 05/10/07 - 20070102755 - Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or ... 05/10/07 - 20070102754 - Non-volatile memory device A single-poly non-volatile memory device invented to integrate into logic process is disclosed. This non-volatile memory device includes a memory cell unit comprising a PMOS access transistor that is serially connected to a PMOS storage transistor formed in a cell array area, and, in a peripheral circuit area, a high-voltage ... 05/03/07 - 20070096202 - Semiconductor device and method for fabricating the same Methods for forming semiconductor memory structures including air gaps between adjacent gate structures are provided. The volume of the air gaps is maximized and the width thereof made uniform in order to minimize the parasitic capacitance and any variance therein between the gate structures. The methods include forming an insulation ... 04/26/07 - 20070090449 - Non-volatile memory devices and methods of forming the same A non-volatile memory device and a method of forming the same are provided. The non-volatile memory device may include a cell isolation pattern and a semiconductor pattern sequentially stacked on a predetermined or given region of a semiconductor substrate, a cell gate line on the semiconductor pattern and on a ... 04/26/07 - 20070090448 - Systems and methods for memory structure comprising embedded flash memory A memory structure that combines multiple embedded flash memory. The flash memory can be used, e.g., as air replacement cells or back up memory, or additional memory cells. In one aspect, the flash memory cells are stacked on top of the flash memory cells and the flash memory cells share ... 04/05/07 - 20070075358 - Flash memory structure and method for fabricating the same A flash memory structure comprises a silicon substrate having at least one concave structure, two doped regions positioned in the semiconductor substrate and at two sides of the concave structure, at least one carrier trapping region positioned in the concave structure, and a conductive layer positioned above the concave structure. ... 03/29/07 - 20070069284 - Method and apparatus for operating a string of charge trapping memory cells A string of memory cells with a charge trapping structure is read, by selecting part of a memory cell selected by a word line. Part of the memory cell is selected by turning on one of the pass transistors on either side of the string of memory cells. The charge ... 03/29/07 - 20070069283 - Method of forming bottom oxide for nitride flash memory A non-volatile memory device on a semiconductor substrate may include a bottom oxide layer over the substrate, a middle layer of silicon nitride over the bottom oxide layer, and a top oxide layer over the middle layer. The bottom oxide layer may have a hydrogen concentration of up to 5E19 ... 03/22/07 - 20070063267 - Self aligned 1 bit local sonos memory cell A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell and a method of fabricating the same has high uniformity between adjacent SONOS cells, since the lengths of nitride layers do not vary due to misalignment when etching word lines of the 1 bit SONOS cells. An insulating layer ... 03/22/07 - 20070063266 - Semiconductor device and method for manufacturing the same A semiconductor device includes a semiconductor region; a first high dielectric constant insulating film provided on the semiconductor region, the first high dielectric constant insulating film being a film other than alumina; a second high dielectric constant insulating film provided on the first high dielectric constant insulating film, the second ... 03/15/07 - 20070057319 - Flash memory device and a method of manufacturing the same The present invention provides a flash memory device and a method of forming the same. The method includes: forming an isolation layer and a plurality of gate lines on a semiconductor substrate; forming a source/drain region by ion-implanting impurities into the semiconductor substrate using the gate lines as a mask; ... 03/15/07 - 20070057318 - Semiconductor memory device and method of production A semiconductor substrate is provided with a recess. A memory layer or memory layer sequence is applied to sidewalls and the bottom of the recess. The memory layer is formed into two separate portions at opposite sidewalls of the recess either by reducing the memory layer to sidewall spacers or ... 03/15/07 - 20070057317 - Non-volatile memory cell and fabricating method thereof and method of fabricating non-volatile memory A method of fabricating a non-volatile memory is provided. In the fabricating method, a plurality of stack gate structures is formed on a substrate and a plurality of doped regions is formed in the substrate beside the stack gate structures. Then, a plurality of spacers is formed on the sidewalls ... 03/08/07 - 20070052011 - Scalable multi-functional and multi-level nano-crystal non-volatile memory device A multi-functional and multi-level memory cell is comprised of a tunnel layer formed over a substrate. In one embodiment, the tunnel layer is comprised of two layers such as HfO2 and LaAlO3. A charge blocking layer is formed over the tunnel layer. In one embodiment, this layer is formed from ... 03/08/07 - 20070052010 - Memory cell and method for manufacturing the same The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the ... 03/01/07 - 20070045720 - Semiconductor device and manufacturing method therefor A semiconductor device is provided which includes a gate electrode (30) provided on a semiconductor substrate (10), an oxide/nitride/oxide (ONO) film (18) that is formed between the gate electrode (30) and the semiconductor substrate (10) and has a charge storage region (14) under the gate electrode (30), and a bit ... 03/01/07 - 20070045719 - Multi-purpose semiconductor device A semiconductor device having at least two controllable states that can be connected to function as a binary memory device (e.g. a DRAM) or alternately as a multi-state (for example four levels) memory device. The device can also be arranged to function substantially as a non-volatile device. The device is ... 03/01/07 - 20070045718 - Band engineered nano-crystal non-volatile memory device utilizing enhanced gate injection Non-volatile memory devices and arrays are described that utilize reverse mode non-volatile memory cells that have band engineered gate-stacks and nano-crystal charge trapping in EEPROM and block erasable memory devices, such as Flash memory devices. Embodiments of the present invention allow a reverse mode gate-insulator stack memory cell that utilizes ... 03/01/07 - 20070045717 - Charge-trapping memory device and method of production A plurality of parallel shallow trenches is etched at a main surface of a semiconductor substrate. A sequence of dielectric materials that are suitable for charge-trapping is applied on the whole surface including sidewalls and bottom surfaces of the etched trenches. This layer sequence completely fills the trenches and forms ... 03/01/07 - 20070045716 - Non-volatile memory and operating method thereof A non-volatile memory including a substrate, a first doped region, a second doped region, a third doped region, a first gate structure, and a second gate structure is disclosed. The doped regions are disposed in the substrate and the second doped region is disposed between the first doped region and ... 02/22/07 - 20070040211 - Nonvolatile memory device and method of forming the same A multi-bit memory cell includes a substrate; a multi-bit charge-trapping cell over the substrate, the multi-bit charge-trapping cell having a first lateral side and a second lateral side; a source region in the substrate, a portion of the source region being under the first side of the multi-bit charge-trapping cell; ... 02/01/07 - 20070023824 - Semiconductor memory device and manufacturing method for semiconductor memory device The object is simplification of a manufacturing process for nonvolatile memory by reducing additional processes for forming a charge storage structure, and downsizing of nonvolatile memory. The solution is a manufacturing method for semiconductor memory device including a process for forming sequentially a first oxide film 102, a first nitride ... 01/25/07 - 20070018237 - Non-volatile memory device having fin-type channel region and method of fabricating the same A non-volatile memory device with improved integration and/or improved performance by reducing an area per bit and controlling a body bias, and a method of fabricating the same. The non-volatile memory device may use surface portions of the outer side surfaces and/or the upper surfaces of at least one pair ... 01/25/07 - 20070018236 - Semiconductor device and manufacturing method thereof A semiconductor device includes a semiconductor substrate, a monocrystalline channel region of a first conductivity type formed on the surface of the semiconductor substrate, a gate electrode formed on the channel region via a gate insulating film, a pair of source/drain electrodes of a second conductivity type provided on both ... 01/18/07 - 20070012993 - Non-volatile memory device, non-volatile memory cell thereof and method of fabricating the same The present invention disclosed a non-volatile memory device and fabricating method thereof. The structure of non-volatile memory device at least comprises a substrate, several dielectric strips, several bit lines, a dielectrically stacking multi-layer, and several word lines. The substrate has several recesses. The dielectric strips are formed on the substrate, ... 01/11/07 - 20070007584 - Nitride semiconductor light emitting diode and method of manufacturing the same The present invention relates to a GaN-based semiconductor light emitting diode and a method of manufacturing the same. The GaN-based semiconductor light emitting diode includes: a substrate; a n-type nitride semiconductor layer formed on the substrate; an active layer formed on a predetermined portion of the n-type nitride semiconductor layer; ... 01/11/07 - 20070007583 - Gate structure and related non-volatile memory device and method A gate structure adapted for use in a SONOS device unit cell is disclosed. The gate structure comprises a charge trap insulator and a single electrode. The charge trap insulator comprises a multilayer structure comprising a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer. ... 12/28/06 - 20060289927 - Non-volatile memory with hole trapping barrier A non-volatile memory is described having memory cells with a gate dielectric. The gate dielectric is a multilayer charge trapping dielectric between a control gate and a channel region of a transistor to trap positively charged holes. The multilayer charge trapping dielectric comprises two layers of dielectric having different band ... 12/21/06 - 20060284246 - Memory utilizing oxide nanolaminates Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide insulator nanolaminate layers with charge ... 12/21/06 - 20060284245 - Sonos memory device having curved surface and method for fabricating the same A new SONOS memory device is provided, in which a conventional planar surface of multi-dielectric layers (ONO layers) is instead formed with a curved surface such as a cylindrical shape, and included is a method for fabricating the same. A radius of curvature of the upper surface of a blocking ... 12/21/06 - 20060284244 - Erasable non-volatile memory device using hole trapping in high-k dielectrics A non-volatile memory is described having memory cells with a gate dielectric. The gate dielectric is a multilayer charge trapping dielectric between a control gate and a channel region of a transistor to trap positively charged holes. The multilayer charge trapping dielectric comprises at least one layer of high-K. ... 12/21/06 - 20060284243 - Electrically erasable programmable read only memory (eeprom) cell and method for making the same An asymmetrically doped memory cell has first and second N+ doped junctions on a P substrate. A composite charge trapping layer is disposed over the P substrate and between the first and the second N+ doped junctions. A N− doped region is positioned adjacent to the first N+ doped junction ... 11/30/06 - 20060267080 - Non-volatile memory and method of controlling the same A single cell that has a gate insulating film formed with an ONO film is provided in a region in which two bit lines cross one word line. The single cell is a four-bit multi-value cell, and has four charge accumulation regions. Two plug-like control electrodes are provided in the ... 11/30/06 - 20060267079 - Memory array including isolation between memory cell and dummy cell portions A semiconductor memory device structure includes an isolation region formed along an edge of a memory cell portion adjacent to a dummy cell portion to isolate the memory cell portion from leakage current generated in the dummy cell portion. ... 11/23/06 - 20060261404 - Vertical nrom nand flash memory array Memory devices, arrays, and strings are described that facilitate the use of NROM memory cells in NAND architecture memory strings, arrays, and devices. NROM NAND architecture memory embodiments of the present invention include NROM memory cells in high density vertical NAND architecture arrays or strings facilitating the use of reduced ... 11/23/06 - 20060261403 - Semiconductor memory device and method of production An array of charge-trapping memory cells and pluralities of parallel wordlines and parallel bitlines running transversely to the wordlines are arranged on a substrate surface. Gate electrodes are located between the wordlines and bitlines and are, in their sequence along the direction of the wordlines, connected alternatingly to one of ... 11/16/06 - 20060255400 - One-transistor composite-gate memory One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more ... 11/16/06 - 20060255399 - nonvolatile memory device having a plurality of trapping films Provided is a nonvolatile memory device which includes a tunneling insulating film formed on a semiconductor substrate, a storage node formed on the tunneling insulating film, a blocking insulating film formed on the storage node, and a control gate electrode formed on the blocking insulating film. The storage node includes ... 11/16/06 - 20060255398 - Ultra-violet protected tamper resistant embedded eeprom A pre-metal dielectric structure of a single-poly EEPROM structure includes a UV light-absorbing film, which prevents the charge on a floating gate of the EEPROM structure from being changed in response to UV radiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer, an amorphous silicon ... 11/09/06 - 20060249782 - Non-volatile storage element and manufacturing method thereof A non-volatile storage element 100 has a silicon substrate 102, a first memory region 106a composed of a first lower silicon oxide film 108a, a first silicon nitride film 110a, and a first upper layer silicon oxide film 112a provided in this order, a second memory region 106b composed of ... 11/02/06 - 20060244050 - Semiconductor device and method of fabricating the same A semiconductor device 100 is configured as having a semiconductor substrate 102 having a first-conductivity-type semiconductor region 104 formed in its surficial portion; an anode 146 of a Schottky barrier diode formed on the first-conductivity-type semiconductor region 104; a second-conductivity-type guard ring 114 formed along the periphery of the anode ... 11/02/06 - 20060244049 - Semiconductor memory device, method for controlling the same, and mobile electronic device A memory cell array employs a memory element as a memory cell. The memory element is constructed of a gate electrode formed via a gate insulation film on a semiconductor layer, a channel region arranged under the gate electrode, diffusion regions that are arranged on both sides of the channel ... 10/26/06 - 20060237779 - Semiconductor device and fabrication method therefor A semiconductor device includes an ONO film (17) formed on a semiconductor substrate (15), a first gate (14), the first gate (14) formed on the ONO film (17), a source (10) and a drain (12) provided at both sides of the first gate (14) to face each other, and a ... 10/26/06 - 20060237778 - Non-volatile semiconductor memory cell and method of manufacturing the same A non-volatile memory cell. The non-volatile memory cell comprises a substrate with a first conductive type, a gate structure, at least two source/drain regions with a second conductive type and a buried channel region with the second conductive type. The gate structure is located on the substrate, and the source/drain ... 10/12/06 - 20060226473 - Gate electrode stack and use of a gate electrode stack A gate electrode stack is disposed on a substrate in a semiconductor device. A gate conductor includes at least one layer of polysilicon and at least one layer of poly-Si1−x,Gex material. The invention is also concerned with a process. This structure can be etched effectively since an end point detection ... 10/05/06 - 20060220106 - Gate structures of a non-volatile memory device and methods of manufacturing the same In a gate structure of a non-volatile memory device is formed, a tunnel insulating layer and a charge trapping layer are formed on a substrate. A composite dielectric layer is formed on the charge trapping layer and has a laminate structure in which first material layers including aluminum oxide and ... 09/28/06 - 20060214220 - Ballistic direct injection nrom cell on strained silicon structures A nitride read only memory cell comprising a silicon-germanium layer with a pair of source/drain regions. A strained silicon layer is formed overlying the silicon-germanium layer such that the pair of source/drain regions is linked by a channel that is generated in the strained silicon layer during operation of the ... 09/21/06 - 20060208312 - Semiconductor storage device and manufacturing method therefor, semiconductor device, portable electronic equipment and ic card A semiconductor storage device includes a field effect transistor which has a gate insulator, a gate electrode and a pair of source/drain diffusion regions on a semiconductor substrate. The device also includes a coating film made of a dielectric having a function of storing electric charge and formed on the ... 09/14/06 - 20060202261 - Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height; ... 08/31/06 - 20060192248 - Memory device and method of manufacturing including deuterated oxynitride charge trapping structure A method for manufacturing a charge storage stack including a bottom dielectric layer, a charge trapping structure on the bottom dielectric layer, and a top dielectric layer, each comprising silicon oxynitride, are formed using reactant gases that comprise hydrogen, where the hydrogen comprises at least 90 percent deuterium isotope. The ... 08/31/06 - 20060192247 - Nitride semiconductor light-emitting device and method for fabrication thereof A nitride semiconductor light-emitting device includes a substrate and a nitride semiconductor layer including a light-emitting layer stacked on the substrate, wherein a normal line relative to a lateral face of the nitride semiconductor layer is not perpendicular to a normal line relative to a principal plane of the substrate. ... 08/17/06 - 20060180853 - Sonos memory device having side gate stacks and method of manufacturing the same In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device and a method of manufacturing the same, a SONOS memory device includes a semiconductor substrate, an insulating layer deposited on the semiconductor substrate, an active layer formed on a predetermined region of the insulating layer and divided into a source region, a drain region, ... 08/03/06 - 20060170034 - Non-volatile memory device and method of manufacturing the same Provided are a non-volatile memory device having an improved electric characteristic and a method of manufacturing the non-volatile memory device, where the non-volatile memory device includes a substrate having a sloped portion formed therein, a first gate electrode pattern having a stacked structure in which an electric charge tunneling layer ... 08/03/06 - 20060170033 - Nonvolatile memory device and method of manufacturing the same A nonvolatile memory device and a method of manufacturing the same are provided. The nonvolatile memory device includes a semiconductor substrate on which a source region, a drain region, and a channel region are formed, a silicon oxide layer formed on the channel region, a transition metal oxide layer having ... 07/20/06 - 20060157777 - Semiconductor device doped with sb,ga or bi and method of manufacturing the same A semiconductor memory device includes a first dopant area and a second dopant area in a semiconductor substrate, the first dopant area and the second dopant area doped with one selected from the group consisting of Sb, Ga, and Bi. The semiconductor memory device includes an insulating layer disposed in ... 07/20/06 - 20060157776 - System and method for contact module processing System and method for improving the process performance of a contact module. A preferred embodiment comprises improving the process performance of a contact module by reducing surface variations of an interlayer dielectric. The interlayer dielectric comprises a plurality of layers, a first layer (for example, a contact etch stop layer ... 06/29/06 - 20060138529 - Method and apparatus for operating a non-volatile memory array A string of memory cells with a charge trapping structure coupled in series is read, by measuring current that flows between the body region of the selected memory cell and the contact region of the selected memory cell. The charge storage state of the charge trapping structure affects the measured ... 06/22/06 - 20060131642 - Semiconductor storage In a semiconductor storage device, a gate insulating film (12) and a gate electrode (13) are laid on a first conductivity type semiconductor substrate (11), and charge holding portions (10A, 10B) are formed on both sides of the gate electrode (13). Second conductivity type first and second diffusion layer regions ... 06/15/06 - 20060124992 - Nrom memory cell, memory array, related devices and methods An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store ... 06/15/06 - 20060124991 - Semiconductor device A semiconductor device includes a semiconductor region having a source region, a drain region, and a channel region provided between the source region and the drain region, a first tunnel insulation film formed on the channel region, a barrier layer formed on the first tunnel insulation film and having an ... 06/08/06 - 20060118859 - Memory cell and method for fabricating same A memory cell and a method for fabricating same. The memory cell comprises a source region and a drain region formed in a semiconductor substrate and a channel region defined between the source and drain regions. Charge storage layers are formed the channel region. A gate insulating layer is formed ... 06/01/06 - 20060113586 - Charge trapping dielectric structure for non-volatile memory An integrated circuit structure comprises a bottom dielectric layer on a substrate, a middle dielectric layer, and a top dielectric layer. The middle dielectric layer has a top surface and a bottom surface, and comprises a plurality of materials. Respective concentration profiles for at least two of the plurality of ... 05/18/06 - 20060102952 - Non-volatile memory devices with charge storage insulators and methods of fabricating such devices A non-volatile memory device comprises a cell region defined at a substrate and a plurality of device isolation layers formed in the cell region to define a plurality of active regions. A charge storage insulator covers substantially the entire top surface of the cell region. A plurality of gate lines ... 04/27/06 - 20060086971 - Semiconductor device and method for fabricating the same A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the ... 04/13/06 - 20060076612 - Semiconductor device and manufacturing method of the same In a manufacturing method of a semiconductor device according to the invention, a silicon oxide film, a polysilicon film, and silicon nitride film are deposited. An opening for forming a LOCOS oxide film is provided in the polysilicon film and the silicon nitride film. Then, using the opening, a P-type ... 03/30/06 - 20060065922 - Semiconductor memory with vertical charge-trapping memory cells and fabrication A semiconductor device is formed by forming a plurality of trenches in a semiconductor body. The trenches alternate between active trenches and isolation trenches with the isolation trenches being deeper than the active trenches. The semiconductor body is doped so that a top surface of the semiconductor body adjacent each ... 03/30/06 - 20060065921 - Non-volatile semiconductor memory device Bitline conductor tracks are arranged parallel to one another and electrically insulated from a substrate provided with a basic doping. A memory layer sequence, especially a charge-trapping layer sequence with a dielectric memory layer between dielectric confinement layers, is provided at least in regions adjacent to the bitline conductor tracks. ... 03/02/06 - 20060043469 - Sonos memory cell and method of forming the same A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell and a method of forming the same are disclosed. The SONOS memory cell includes a substrate in which a recessed region having at least one side wall is arranged and a trap storage pattern with which the recessed region is filled with a first insulating ... 02/02/06 - 20060022260 - Semiconductor device and manufacturing method of semiconductor device Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power ... 01/19/06 - 20060011972 - Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially ... 12/29/05 - 20050285185 - Nrom memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals A high permittivity gate dielectric formed by low temperature metal oxidation is used in an NROM memory cell. The gate dielectric has a dielectric constant greater than silicon dioxide and is comprised of a nanolaminate structure. The NROM memory cell has a substrate with doped source/drain regions. The high-k gate ... 12/29/05 - 20050285184 - Flash memory device and method for programming/erasing the same A flash memory device and a method for programming/erasing a flash memory device are disclosed. An example flash memory device includes a semiconductor substrate, an oxide-nitride-oxide (ONO) layer formed on the semiconductor substrate, a blocking insulating layer having a high dielectric constant and being formed on the ONO layer, first ... 12/15/05 - 20050275012 - Nonvolatile semiconductor memory device and method of manufacturing the same A nonvolatile semiconductor memory device includes a gate electrode portion composed of a floating gate electrode formed above a main surface of a semiconductor substrate of a first conductivity type via a tunnel insulating film, an inter-electrode insulating film formed on the floating gate electrode and formed of a stacked ... 12/08/05 - 20050269627 - Trench corner effect bidirectional flash memory cell A non-volatile memory cell structure that is capable of holding two data bits. The structure includes a trench in a substrate with two sides of the trench being lined with a trapping material. The trench is filled with an oxide dielectric material and a control gate is formed over the ... 11/24/05 - 20050258475 - Memory device having an electron trapping layer in a high-k dielectric gate stack An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric stack formed over a channel region of a semiconductor substrate. The dielectric stack includes a layer of electron trapping material that operates as a charge storage center for ... 11/17/05 - 20050253186 - Trench corner effect bidirectional flash memory cell A non-volatile memory cell structure that is capable of holding two data bits. The structure includes a trench in a substrate with two sides of the trench being lined with a trapping material. The trench is filled with an oxide dielectric material and a control gate is formed over the ... 11/10/05 - 20050247972 - Ballistic direct injection nrom cell on strained silicon structures A nitride read only memory cell comprising a silicon-germanium layer with a pair of source/drain regions. A strained silicon layer is formed overlying the silicon-germanium layer such that the pair of source/drain regions is linked by a channel that is generated in the strained silicon layer during operation of the ... 11/03/05 - 20050242391 - Two bit/four bit sonos flash memory cell Charge migration in a SONOS memory cell is eliminated by physically separating nitride layer storage sites with dielectric material. Increased storage in a cell is realized with a double gate structure for controlling bit storage in line channels between a source and a drain, such as with a FinFET structure ... 10/13/05 - 20050224866 - Semiconductor memory device and manufacturing method thereof After an ONO film in which a silicon nitride film (22) formed by a plasma nitriding method using a plasma processor having a radial line slot antenna is sandwiched by silicon oxide films (21), (23), a bit line diffusion layer (17) is formed in a memory cell array region (11) ... 10/13/05 - 20050224865 - Circuit layout and structure for a non-volatile memory A structure of non-volatile memory contains a substrate. A plurality of bit lines are formed in the substrate along a first direction, wherein each of the bit lines also serve as a source/drain (S/D) region. A first dielectric layer is disposed over the substrate. A plurality of selection gate (SG) ... 09/15/05 - 20050199946 - Semiconductor memory device and manufacturing method thereof A manufacturing method of a semiconductor memory device comprising the steps of: forming plural trenches in stripes in a semiconductor substrate and filling each of the trenches with an element isolation insulating film to form element isolation regions; sequentially forming a tunnel insulating film and a charge-storable film so as ... 09/15/05 - 20050199945 - Nonvolatile memory and nonvolatile memory manufacturing method A nonvolatile memory device includes source and drain regions formed in a semiconductor substrate, and an insulating film formed on a channel region between the source region and the drain region in the semiconductor substrate. The nonvolatile memory device also includes a dielectric film formed above the channel region to ... 09/15/05 - 20050199944 - [non-volatile memory cell] The present invention provides a non-volatile memory cell, comprising a tunnel dielectric layer disposed on the substrate, a barrier dielectric layer disposed over the tunnel dielectric layer, a graded charge trapping layer disposed between the tunnel dielectric layer and the barrier dielectric layer, a gate conductive layer disposed on the ... 09/08/05 - 20050194634 - Semiconductor device, semiconductor laser, their manufacturing methods and etching methods To provide a semiconductor device, such as semiconductor laser, having no need of complicated process, ensuring a high yield and mass-productivity necessary for cost reduction, and exhibiting excellent initial characteristics and reliability, nitride semiconductor layers containing a plurality of group III elements are formed on a base body surface having ... 09/08/05 - 20050194633 - Nonvolatile semiconductor memory device, charge injection method thereof and electronic apparatus A charge injection method for improve efficiency of generating hot carrier, wherein, for example, electrons are injected at writing and holes are injected at erasing to a charge storage layer of a memory transistor. A positive voltage is applied to the drain region by using a voltage of the source ... 09/01/05 - 20050189582 - Charge trapping memory cell and fabrication method A memory cell patterned as a trench transistor is provided with a first gate electrode (4) as auxiliary gate for source-side injection and a second gate electrode (5) electrically insulated therefrom, which are arranged in the trench, and has, at the trench walls, a storage layer sequence (10) provided for ... 08/25/05 - 20050184334 - Non-volatile memory device having a charge storage oxide layer and operation thereof A non-volatile memory device includes a pair of source/drain regions disposed in a semiconductor substrate, having a channel region between them. A charge storage oxide layer is disposed on the channel region and overlaps part of each of the pair of source/drain regions. A gate electrode is disposed on the ... 08/04/05 - 20050167737 - Non-volatile semiconductor memory device and process for fabricating the same A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive ... 08/04/05 - 20050167736 - Non-volatile semiconductor memory device and process for fabricating the same A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive ... 08/04/05 - 20050167735 - Non-volatile semiconductor memory device and process for fabricating the same A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive ... 07/21/05 - 20050156228 - Manufacture method and structure of a nonvolatile memory The manufacturing method of a nonvolatile memory and its structure is achieved by building a gate dielectric layer on a base. The gate dielectric layer contains at least two layers of different material layers. At least one hetero element is planted on the top of the gate dielectric layer so ... 07/07/05 - 20050145928 - Twin insulator charge storage device operation and its fabrication method The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be ... 06/30/05 - 20050139903 - Protection againts in-process charging in silicon-oxide-nitride-oxide-silicon (sonos) memories A pre-metal dielectric structure of a SONOS memory structure includes a UV light-absorbing film, which prevents the ONO structure from being electronically charged in response to UV irradiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer located over the SONOS memory structure, a light-absorbing structure ... 06/30/05 - 20050139902 - Non-volatile memory device A non-volatile memory including a semiconductor substrate, and a SONOS electrode on the semiconductor substrate, where the SONOS electrode has a channel area defined underneath. The memory also includes a first layer in contact with a side of the SONOS electrode, a second layer in contact with another side of ... 06/30/05 - 20050139901 - Non-volatile memory device and fabricating method thereof The present invention provides a non-volatile memory device and fabricating method thereof, by which a cell size can be lowered despite high degree of cell integration and by which the device fabrication is facilitated. The present invention includes at least two trench isolation layers arranged in a device isolation area ... 06/09/05 - 20050121716 - Flash memory device A memory device includes a conductive structure, a number of dielectric layers and a control gate. The dielectric layers are formed around the conductive structure and the control gate is formed over the dielectric layers. A portion of the conductive structure functions as a drain region for the memory device ... 06/02/05 - 20050116281 - Multilayered dual bit memory device with improved write/erase characteristics and method of manufacturing A dual bit ROM multilayered structure with improved write and erase functions and a method of manufacturing is disclosed. The structure includes a pair of floating gates at the middle or nitride layer to better define the two locations of electrons representing the dual data bits collected in the middle ... ### FreshPatents.com Support |