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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Variable Threshold (e.g., Floating Gate Memory Device) > With Floating Gate Electrode > With Additional Contacted Control Electrode > With Thin Insulator Region For Charging Or Discharging Floating Electrode By Quantum Mechanical Tunneling With Thin Insulator Region For Charging Or Discharging Floating Electrode By Quantum Mechanical TunnelingWith Thin Insulator Region For Charging Or Discharging Floating Electrode By Quantum Mechanical Tunneling patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/03/08 - 20080001210 - Self-aligned element isolation film structure in a flash cell and forming method thereof A self-aligned element isolation film structure in a flash memory cell and a forming method thereof are disclosed. An example method of forming a self-aligned element isolation film structure in a flash memory cell forms an insulating layer on a semiconductor substrate and forms a floating gate pattern on the ... 12/13/07 - 20070284649 - Semiconductor device and method of manufacturing same A semiconductor device includes a deposited-type insulating film disposed on a substrate; a coating-type insulating film disposed on a surface of the deposited-type insulating film and having a film density which is lower than a film density of the deposited-type insulating film; and an intermediate insulating film disposed between the ... 11/29/07 - 20070272972 - Semiconductor memory device and manufacturing method thereof A semiconductor device, in which both a reduction in a resistivity of a gate electrode and stabilization of transistor characteristics is achieved, and a manufacturing method thereof are disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising a semiconductor substrate, a plurality of ... 11/22/07 - 20070267688 - Sonos memory device having nano-sized trap elements A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the ... 11/22/07 - 20070267687 - Bandgap engineered split gate memory Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; ... 11/22/07 - 20070267686 - System and method for reducing process-induced charging A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate. ... 08/09/07 - 20070181937 - P-channel non-volatile memory and operating method thereof A P-channel non-volatile memory is described. The P-channel non-volatile memory includes a substrate, a first memory cell, and second memory cell. An N-well is disposed over the substrate, and the first cell and the second cell are disposed over the N-well. The first memory cell includes a first gate, a ... 07/19/07 - 20070164350 - Method and structure for a self-aligned silicided word line and polysilicon plug during the formation of a semiconductor device A method used to form a semiconductor device provides a silicide layer on a plurality of transistor word lines and on a plurality of conductive plugs. In one embodiment, the word lines, one or more sacrificial dielectric layers on the word lines, conductive plugs, and a conductive enhancement layer are ... 06/28/07 - 20070145472 - Flash memory cell including dual tunnel oxide layer and method of manufacturing the same A flash memory cell may include a tunnel oxide layer over a semiconductor substrate with a first tunnel having a first thickness and a second tunnel having a second thickness. A charge storage layer may be formed over a tunnel oxide layer, an insulating layer may be formed over a ... 06/14/07 - 20070132009 - Semiconductor device and method for producing the same A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulation film existing between the ... 05/31/07 - 20070120178 - Electrochemical cell structure and method of fabrication A method of forming a metal oxide layer for an electrochemical cell is provided. The method includes: forming a plurality of adjacent metal oxide cells, spaced from one another; and performing localised heating of the plurality of adjacent metal oxide cells. A method of forming an electrochemical cell is also ... 05/31/07 - 20070120177 - Electrochemical cell structure and method of fabrication A method of forming a metal oxide layer having metal oxide particles and a binder for an electrochemical cell, comprises: depositing a layer of metal oxide; and depositing a polymeric linking agent onto the layer of metal oxide. Additionally, a method of forming an electrochemical cell comprises forming a metal ... 05/24/07 - 20070114595 - Transistor of a semiconductor device Disclosed are a semiconductor device and a method of manufacturing the same. According to the present invention, the transistor of the semiconductor device comprises a stack type gate in which a tunnel oxide film, a floating gate, a dielectric film and a control gate are sequentially stacked on a semiconductor ... 05/03/07 - 20070096201 - Single mask scheme method and structure for integrating pmos and nmos transistors using strained silicon A method for forming a CMOS integrated circuit using strained silicon technology. The method forms a liner layer overlying the first gate structure and the second gate structure and overlying first source/drain regions in the first well region and second source/drain regions in the second well region. In a preferred ... 04/19/07 - 20070085133 - High frequency excitation system A power module is adapted to be connected to a voltage source and to supply power to a load. The power module includes a switching bridge that includes a first power transistor and a second power transistor, a first gate controller for driving the first power transistor and a second ... 04/05/07 - 20070075357 - Semiconductor storage device and manufacturing method thereof A non-volatile semiconductor storage device having a high-dielectric-constant insulator and a manufacturing method thereof suitable for miniaturization are disclosed. According to one aspect of the present invention, it is provided a semiconductor storage device comprising a semiconductor substrate, a plurality of first conductor layers formed on the semiconductor substrate through ... 03/22/07 - 20070063265 - Non-volatile semiconductor memory devices and methods of fabricating the same Nonvolatile memory devices and related methods of fabricating nonvolatile memory devices are disclosed. A nonvolatile memory device includes a tunnel insulation film on a semiconductor substrate, a charge-trapping layer on the tunnel insulation film, a block insulation film on the charge-trapping layer, and a gate electrode on the blocking insulation ... 03/22/07 - 20070063264 - A non-volatile memory array A non-volatile memory array including memory units which are arranged in a row/column array is provided. Source lines are arranged in parallel in the column direction and connect to the source regions of the memory units in the same column. Bit lines are arranged in parallel in the row direction ... 03/15/07 - 20070057316 - Semiconductor device and manufacturing method thereof A semiconductor device, in which both a reduction in a resistivity of a gate electrode and stabilization of transistor characteristics is achieved, and a manufacturing method thereof are disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising a semiconductor substrate, a plurality of ... 02/08/07 - 20070029607 - Dense arrays and charge storage devices There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing. ... 01/04/07 - 20070001217 - Closed loop cesl high performance cmos devices An N-MOS and/or P-MOS device having enhanced performance such as an FET suitable for use in a CMOS circuit. The device comprises both an “L-like” shaped layer or spacer on the side walls of a gate structure as well as a CESL (contact-etch stop layer) that covers the gate structure ... 12/07/06 - 20060273377 - Nonvolatile memory device and method of manufacturing the same Provided are a nonvolatile memory device and a method of manufacturing the same. The device includes a semiconductor substrate; a source region and a drain region disposed in the semiconductor substrate and a channel region interposed between the source and drain regions; a first tunnel oxide layer disposed on the ... 12/07/06 - 20060273376 - Method of manufacturing devices comprising conductive nano-dots, and devices comprising same A method is disclosed that may include forming a first layer of insulating material above a semiconducting substrate, forming an aluminum oxide layer above the first layer of insulating material, forming a plurality of spaced-apart dots of material on the aluminum oxide layer, forming a second layer of insulating material ... 11/30/06 - 20060267078 - Charge-trapping memory device An oxidized region is arranged between a substrate of semiconductor material and a nitride liner, which covers wordline stacks of a memory cell array and intermediate areas of the substrate, and is provided to separate the nitride liner both from the substrate and from a memory layer sequence of dielectric ... 11/09/06 - 20060249781 - Non-volatile semiconductor memory device A non-volatile semiconductor memory device according to the present invention has a semiconductor substrate and a memory cell having a floating gate provided through a tunnel insulating layer on the semiconductor substrate, and a control gate provided through an inter-layer insulting layer on said floating gate. The inter-insulating layer includes ... 11/09/06 - 20060249780 - Non-volatile semiconductor memory device A non-volatile semiconductor memory device according to the present invention has a semiconductor substrate and a memory cell having a floating gate provided through a tunnel insulating layer on the semiconductor substrate, and a control gate provided through an inter-layer insulting layer on said floating gate. The inter-insulating layer includes ... 11/02/06 - 20060244048 - Method for reducing single bit data loss in a memory circuit The present invention includes a method for reducing random bit data loss in a memory circuit. The method comprises a semiconductor layer that has a surface. The semiconductor layer is exposed at an elevated temperature to an atmosphere comprising deuterium thereby forming a film on the semiconductor layer comprising deuterium. ... 10/26/06 - 20060237777 - Multi-bit non-volatile memory device having a dual-gate and method of manufacturing the same, and method of multi-bit cell operation The present invention relates to a multi-bit non-volatile memory device having a dual gate employing local charge trap and method of manufacturing the same, and an operating method for a multi-bit cell operation. ... 09/21/06 - 20060208311 - Quantum circuit and quantum computer The present invention realizes a quantum circuit and a quantum computer capable of performing multi-bit quantum computation. A quantum bit is represented by the polarization directions of light, a sequence of polarized light pulses representing a quantum bit string is sequentially supplied, and the amount of polarization rotation applied to ... 08/17/06 - 20060180852 - Non-volatile semiconductor memory device and its manufacturing method There is provided a high-reliability nano-dots memory by forming the nano dots uniformly. Also, there is provided the high-speed and high-reliability nano-dots memory by employing a silicon-oxide-film alternative material as a tunnel insulating film. The nano-dots memory includes the tunnel insulating film and silicide nano-dots of CoSi2 or NiSi2. Here, ... 08/10/06 - 20060175656 - Non-volatile memory devices Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply ... 06/29/06 - 20060138528 - Charge trap insulator memory device A charge trap insulator memory device comprises a bottom word line, a P-type float channel formed at the bottom word line and kept at a floating state, a charge trap insulator formed on the P-type float channel, a top word line formed on the charge trap insulator in parallel with ... 06/22/06 - 20060131641 - Semiconductor device and method of manufacturing the same A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film having a film thickness periodically and continuously changing in a channel width direction of the non-volatile memory cell, a floating gate electrode provided on ... 06/08/06 - 20060118858 - Non-volatile semiconductor memory device with alternative metal gate material A non-volatile semiconductor memory device comprises a substrate including a source region, a drain region and a channel region provided between the source region and the drain region with a gate stack located above the channel region with a metal gate located above the gate stack. The metal gate is ... 05/11/06 - 20060097310 - Non-volatile memory devices including divided charge storage structures and methods of fabricating the same A semiconductor memory device includes a substrate having first and second source/drain regions therein and a channel region therebetween. The device also includes first and second charge storage layers on the channel region, a first insulating layer on the channel region between the first and second charge storage layers, and ... 04/27/06 - 20060086970 - Non-volatile memory cell structure with charge trapping layers and method of fabricating the same In a non-volatile memory device and a method for forming such a device, at least one edge of the charge trapping layer is recessed. In this manner, the threshold voltage of the device during a programming operation and the threshold voltage of the device during an erase operation are maintained ... 04/20/06 - 20060081916 - Methods of forming gate structures for semiconductor devices and related structures Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the ... 04/20/06 - 20060081915 - Nonvolatile semiconductor memory device and method for fabricating the same The nonvolatile semiconductor memory device comprises a channel region formed in a semiconductor substrate, a gate electrode formed over the channel region with a charge retaining insulating film interposed therebetween, a first pair of source/drain regions arranged in a first direction with the channel region formed therebetween, and a second ... 04/06/06 - 20060071266 - Semiconductor memory and fabrication method for the same A semiconductor memory includes memory cell transistors comprising a tunnel insulating film, a floating gate electrode, a first insulating film, a control gate electrode, and a first metal salicide film; low-voltage transistors comprising a first p-type source region and a first p-type drain region, a first gate insulating film, and ... 03/23/06 - 20060060914 - Semiconductor memory devices and methods of fabricating the same There are provided highly integrated semiconductor memory devices being suitable for storing two bits of data in one unit cell, and methods of fabricating the same. The unit cell of the semiconductor memory device includes a semiconductor substrate and source and drain regions formed in the semiconductor substrate and spaced ... 02/16/06 - 20060033152 - Non-volatile memory device and method of fabricating the same A non-volatile memory device having improved electrical characteristics and a method of fabricating the non-volatile memory device are provided. The non-volatile memory device includes a gate electrode, which is formed on a semiconductor substrate on which source and drain regions are formed, a trapping structure, which is interposed between the ... 02/02/06 - 20060022259 - Nonvolatile semiconductor memory device and manufacturing method thereof The object of the present invention is to provide a new nonvolatile semiconductor memory device and its manufacturing method for the purpose of miniaturizing a virtual grounding type memory cell based on a three-layer polysilicon gate, enhancing the performance, and boosting the yield. In a memory cell according to the ... 08/04/05 - 20050167734 - Flash memory devices using large electron affinity material for charge trapping Disclosed is a novel flash memory device using a high-permittivity dielectric such as HfO2 or TiO2 as a charge trapping layer. Numerical simulation shows that the novel trapping material will enhance the retention time/programming speed ratio by 5 orders of magnitude, compared to the conventional Si3N4 trapping layer. Capacitors with ... 07/21/05 - 20050156227 - Nonvolatile memory with undercut trapping structure The present invention discloses a nonvolatile memory with undercut trapping structure, the nonvolatile memory comprising a semiconductor substrate. A gate oxide is formed on the semiconductor substrate. A gate structure is formed on the gate oxide, wherein the gate structure including a undercut structure formed at lower portion of the ... 07/21/05 - 20050156226 - Mask rom and the method of forming the same and the scheme of reading the device The structure of the nonvolatile memory comprises a substrate having source/drain formed at unselected sides and source/drain with extension source/drain formed at other selected sides. A gate dielectric layer is formed on the substrate and a gate is formed on the gate dielectric layer. An isolation layer is formed along ... 07/07/05 - 20050145927 - Non-volatile memory cell A memory cell includes an N-type well, three P-type doped regions, a first stacked dielectric layer, a first gate, a second stacked dielectric layer, and a second gate. The three P-type doped regions are formed on the N-well. The first dielectric stack layer is formed on the N-type well and ... 06/16/05 - 20050127431 - Quantum structure and forming method of the same A quantum structure and the forming method based on the difference in characteristic of two matters is provided. The forming method includes several steps. At first, providing a first dielectric layer for forming a second dielectric layer thereon. The second dielectric layer has major elements and impurities contained. Treating the ... 06/16/05 - 20050127430 - Non volatile memory device having a gate electrode A nonvolatile memory device having a gate electrode including: a non volatile memory cell configured to store data, and having a first gate electrode, first and second diffusion layers, the first gate electrode having a first top surface and a first side surface; a peripheral transistor having a second gate ... ### FreshPatents.com Support |