REGISTER now for FREE 
|
FREE patent keyword monitoring and additional FREE benefits. REGISTER now for FREE
|
 
|
|
Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Variable Threshold (e.g., Floating Gate Memory Device) Variable Threshold (e.g., Floating Gate Memory Device)Variable Threshold (e.g., Floating Gate Memory Device) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/24/08 - 20080017912 - Non-volatile memory cell with embedded antifuse A nonvolatile memory device includes at least one memory cell which comprises a first diode portion, a second diode portion and an antifuse separating the first diode portion from the second diode portion. ... 01/24/08 - 20080017909 - Semiconductor device and method of manufacturing the same A semiconductor device and a method of manufacturing the same. The semiconductor device includes a first well formed in a predetermined region of a semiconductor substrate, a second well formed in a predetermined region within the first well, and a third well formed within the first well with the third ... 12/27/07 - 20070296017 - Nonvolatile semiconductor memory A nonvolatile semiconductor memory in which the area of each memory cell is small and which can perform high-speed operation with accuracy. A pair of honeycomb-like diffusion layers which are deviated from each other by a quarter-pitch are formed. Memory transistors (MemoryTr) and select transistors (SelectTr) are formed at portions ... 12/27/07 - 20070296016 - Semiconductor device and method of manufacturing the same A semiconductor device including a semiconductor substrate; an element isolation region having a trench filled with an insulating film defined or the semiconductor substrate; a memory cell transistor formed in an element forming region isolated by the element isolating regions of the semiconductor substrate; and the memory cell transistor includes ... 12/20/07 - 20070290250 - Multiple dielectric finfet structure and method Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics covering the fins extending from the substrate. These fins have a central channel region and source and drain regions on opposite sides of the channel region. The thicker gate dielectrics ... 12/13/07 - 20070284645 - Non-volatile memory devices having a multi-layered charge storage layer and methods of forming the same A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-layered charge storage including a tunnel insulation, a trap ... 12/06/07 - 20070278555 - Non volatile semiconductor memory device A non volatile semiconductor memory device wherein it is possible to transfer Vpp without a drop in voltage of the transfer transistor Vth (threshold voltage) in a transfer circuit or decoder circuit for selectively transferring Vpp by using a usual LVP (low voltage P type transistor) to reduce step(s) of ... 11/15/07 - 20070262368 - Non-volatile memory and manufacturing method thereof A non-volatile memory is provided, including a substrate, a control gate, a floating gate, and a select gate. A source region and a drain region are disposed in the substrate. The control gate is disposed on the substrate between the source region and the drain region. The floating gate is ... 11/08/07 - 20070257298 - Memory cell with reduced size and standby current A present invention is a method, and resulting device, for fabricating memory cells with an extremely small area and reduced standby current. The small area is accomplished by a judicious use of spacers which allows a tunnel window of a storage device to be fabricated in close proximity to an ... 11/08/07 - 20070257297 - Memory device having nanocrystals and methods of manufacturing the same The memory device includes a source region and a drain region in a substrate and spaced apart from each other; a memory cell formed on a surface of the substrate, wherein the memory cell connects the source region and the drain region and includes a plurality of nanocrystals; a control ... 11/01/07 - 20070252189 - Flash memory cell and method for manufacturing the same An active region and a trench region are formed on a semiconductor substrate. The trench region is filled with a dielectric material to form an isolation layer. Oxide and polysilicon layers are formed on the semiconductor substrate. A second polysilicon layer, a second oxide layer, and a first polysilicon layer ... 10/25/07 - 20070246767 - Semiconductor device formed on a soi substrate Thresholds of MISFETS of a Full Depletion-type SOI substrate cannot be controlled by changing impurity density as with bulk silicon MISFETs. Therefore, it is difficult to set a suitable threshold for each circuit. According to the semiconductor device of the present invention, gate electrodes of P-channel type MISFETs composing a ... 10/25/07 - 20070246766 - Phase change memory elements using self-aligned phase change material layers and methods of making and using same A phase change memory element and method of forming the same. The memory element includes a substrate supporting a first electrode. An insulating material element is positioned over the first electrode, and a phase change material layer is formed over the first electrode and surrounding the insulating material element such ... 10/25/07 - 20070246765 - Semiconductor memory device and method for production Parallel fins or ridges are arranged on a main surface of a semiconductor substrate. Source/drain regions are provided at top and bottom portions of said fins, and wordlines comprising gate electrodes are arranged in interspaces between neighboring fins. The channels of individual memory cells are directed vertically with respect to ... 10/18/07 - 20070241389 - Semiconductor device A semiconductor device includes a semiconductor substrate, a plurality of nonvolatile memory cells provided on the semiconductor substrate, each of the plurality of nonvolatile memory cells comprising a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a control gate electrode ... 10/18/07 - 20070241388 - Semiconductor device A semiconductor device includes semiconductor substrate, isolation insulating film, nonvolatile memory cells, each of the cells including tunnel insulating film, FG electrode, CG electrode, interelectrode insulating film between the CG and FG electrodes and including a first insulating film and a second insulating film on the first insulating film and ... 10/18/07 - 20070241384 - Methods and apparatus for non-volatile semiconductor memory devices The present invention provides methods and apparatuses for a non-volatile semiconductor memory device. A non-volatile semiconductor memory device having multiple layers to provide a source, a drain, and a floating gate, comprising a plurality of metal layers to provide interconnects to the non-volatile memory wherein at least two of the ... 10/11/07 - 20070235795 - Ferroelectric storage device and manufacturing method thereof According to an aspect of the embodiment, there is provided a ferroelectric storage device including: a plurality of memory cells repeatedly arranged in a predetermined direction, each memory cell including a ferroelectric film divided for each memory cell; and a word line formed on the ferroelectric film and shared by ... 10/11/07 - 20070235792 - Self-aligned, silicided, trench-based dram/edram processes with improved retention A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending beyond ... 10/04/07 - 20070228449 - Nonvolatile semiconductor memory device It is an object of the present invention to provide a nonvolatile semiconductor memory device which has superior writing characteristics and electric charge retention characteristics. In addition, it is an object of the present invention to provide a nonvolatile semiconductor memory device in which a writing voltage can be reduced. ... 09/27/07 - 20070221979 - Method for production of memory devices and semiconductor memory device At least one memory layer is provided on a substrate surface. A plurality of parallel conductor strips is formed from electrically conductive material above the memory layer. Sidewalls of the conductor strips are provided with spacers of an electrically conductive material. ... 09/06/07 - 20070205457 - Semiconductor memory device with bit line of small resistance and manufacturing method thereof A reduction of a resistance of a bit line of a memory cell array and a reduction of a forming area of the memory cell array are planed. Respective bit lines running at right angles to a word line are composed of a diffusion bit line formed in a semiconductor ... 09/06/07 - 20070205455 - Flash memory cells having trenched storage elements An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench. The first trench and the second trench each define a first side ... 09/06/07 - 20070205454 - Dual storage node memory An embodiment of the present invention is directed to a memory cell. The memory cell includes a first charge storage element and a second charge storage element, wherein the first and second charge storage elements include nitrides. The memory cell further includes an insulating layer formed between the first and ... 08/30/07 - 20070200163 - Non-volatile electrically alterable memory cell for storing multiple data and manufacturing thereof A memory cell that includes two control gates disposed laterally between two floating gates where each floating gate is capable of holding data. The memory cell is formed by placing a first polysilicon on a substrate of semiconductor material, on which a well is placed. The control gates are preferably ... 08/30/07 - 20070200162 - Reducing dielectric constant for mim capacitor A memory device having improved sensing speed and reliability and a method of forming the same are provided. The memory device includes a first dielectric layer having a low k value over a semiconductor substrate, a second dielectric layer having a second k value over the first dielectric layer, and ... 08/23/07 - 20070194366 - Single poly non-volatile memory device with inversion diffusion regions and methods for operating the same A non-volatile memory device comprises a substrate with the dielectric layer formed thereon. A control gate and a floating gate are then formed next to each other on top of the dielectric layer separated by a gap. Accordingly, a non-volatile memory device can be constructed using a single poly process ... 08/23/07 - 20070194365 - Dual gate multi-bit semiconductor memory array An array of memory cells is arranged in columns and one or more rows on a semiconductor substrate. Each cell has a source, a drain, a first gate and a second gate. The array includes a plurality of gate control lines, each of which corresponds to one of the columns ... 08/16/07 - 20070187744 - Integrated circuits, memory device, method of producing an integrated circuit, method of producing a memory device, memory module The invention relates to integrated circuits, a memory device, a method of producing an integrated circuit, a method of producing a memory device, and a memory module. ... 08/16/07 - 20070187743 - Semiconductor device and method of manufacturing the same A semiconductor device includes a pair of select gate structures which are opposed to each other and which are formed in a select transistor formation area, each of the select gate structures including a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate ... 08/09/07 - 20070181933 - Non-volatile memory electronic device A non-volatile memory device integrated on semiconductor substrate and having a matrix of non-volatile memory cells organized in rows, called word lines, and columns, called bit lines, the device including a plurality of active areas formed on the semiconductor substrate equidistant from each other, and having at least a first ... 08/09/07 - 20070181932 - Thermal isolation of phase change memory cells A memory includes an array of resistive memory cells, bit lines between rows of the memory cells for accessing the memory cells, and a conductive plate coupled to each of the memory cells. ... 08/02/07 - 20070176223 - Split gate memory cell in a finfet A memory cell is implemented using a semiconductor fin in which the channel region is along a sidewall of the fin between source and drains regions. One portion of the channel region has a select gate adjacent to it and another other portion has the control gate adjacent to it ... 07/26/07 - 20070170489 - Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process A non-volatile memory cell with increased charge retention is fabricated on the same substrate as logic devices using a single-gate conventional logic process. A silicide-blocking dielectric structure is formed over a floating gate of the NVM cell, thereby preventing silicide formation over the floating gate, while allowing silicide formation over ... 07/19/07 - 20070164345 - Semiconductor device and method of manufacturing the same An insulating film provided below a floating gate electrode includes a first insulating film located at both end portions below the floating gate electrode, and a second insulating film sandwiched between the first insulating films and located in a middle portion below the floating gate electrode. The first insulating film ... 07/19/07 - 20070164344 - Nonvolatile semiconductor device and method of fabricating the same A stack-type nonvolatile semiconductor device comprises a memory device formed on a substrate including a semiconductor body elongated in one direction, having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region on the semiconductor body along the circumference, a tunneling insulating layer on the ... 07/19/07 - 20070164343 - Nonvolatile semiconductor memory device having element isolating region of trench type Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer ... 07/12/07 - 20070158732 - Flash memory device having vertical split gate structure and method for manufacturing the same Disclosed are a flash memory device having a vertical split gate structure and a method for manufacturing the same. The flash memory device includes a first trench formed in an active region of a semiconductor substrate and including a pair of opposite sidewalls, a second trench formed in the middle ... 07/12/07 - 20070158730 - Integrated circuit using finfets and having a static random access memory (sram) An integrated circuit includes a logic circuit and a memory cell. The logic circuit includes a P-channel transistor, and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has a portion located along a sidewall of a semiconductor ... 06/28/07 - 20070145464 - Random access memory device utilizing a vertically oriented select transistor A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely ... 06/28/07 - 20070145463 - Pcram device with switching glass layer A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and devices formed using such a method. ... 06/28/07 - 20070145462 - Low tunnel barrier insulators Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. ... 06/28/07 - 20070145461 - Floating gate of flash memory device and method of forming the same Disclosed is a floating gate of a flash memory device, wherein a tunneling oxide layer is formed on a semiconductor substrate, and a floating gate is formed in the shape of a lens having a convex top surface. ... 06/28/07 - 20070145460 - Flash memory device and method of manufacturing the same Disclosed are a flash memory device having a silicon-oxide-nitride-oxide-silicon (SONOS) structure and a method of manufacturing the same. The flash memory device includes source and drain diffusion regions separated from each other on opposite sides of a trench in an active region of a semiconductor substrate, a control gate inside ... 06/28/07 - 20070145459 - Eeprom devices and methods of operating and fabricating the same In one aspect, an electrically erasable and programmable read-only memory (EEPROM) is provided. The EEPROM includes a semiconductor substrate including spaced apart first, second and third active regions, a common floating gate traversing over the first through third active regions, source/drain regions formed in the third active region on opposite ... 06/28/07 - 20070145458 - Semiconductor device and manufacturing method thereof A semiconductor device which is formed in a self-aligned manner without causing a problem of misalignment in forming a control gate electrode and in which a leak between the control gate electrode and a floating gate electrode is not generated, and a manufacturing method of the semiconductor device are provided. ... 06/28/07 - 20070145457 - System and method of forming a split-gate flash memory structure A method for forming a split-gate flash memory structure includes etching a first gate layer to form one or more floating gates and forming an isolation layer over the floating gates. An insulation layer is deposited over the isolation layer and planarized. ... 06/28/07 - 20070145456 - Flash memory device and method of manufacturing the same A non-volatile memory device includes a semiconductor substrate having an active region defined by isolation films that extend along a first direction. A control gate line extends along in a second direction perpendicular to the first direction. First and second floating gates are formed on the active region and below ... 06/28/07 - 20070145455 - Non-volatile semiconductor device and method of fabricating embedded non-volatile semiconductor memory device with sidewall gate A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. ... 06/21/07 - 20070138534 - Deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. ... 06/21/07 - 20070138533 - Substrate solution for back gate controlled sram with coexisting logic devices A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level ... 06/14/07 - 20070131999 - Gated diode nonvolatile memory process A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same. ... 06/07/07 - 20070126048 - Semiconductor device and method of forming the same There is provided a semiconductor device and a method of forming the same. The semiconductor device includes a memory device and a self-aligned selection device. A floating junction is formed between the self-aligned selection device and the memory device. ... 06/07/07 - 20070126047 - Non-volatile semiconductor memory device and method for manufacturing the same In a non-volatile semiconductor memory device having a MONOS structure, a memory cell section for storing information, and a periphery circuitry section for writing and reading the information with respect to the memory cell section are formed in the surface region of a silicon substrate. A plurality of memory cells ... 06/07/07 - 20070126046 - Nonvolatile semiconductor memory and method of fabricating the same According to the invention, there is provided a nonvolatile semiconductor memory having: a floating gate electrode formed on a gate insulating film on an element region isolated by an element isolation region on a semiconductor substrate; an inter-gate insulating film formed to cover a portion from an upper surface to ... 05/17/07 - 20070108496 - Nonvolatile semiconductor storage device and method of manufacture thereof In a nonvolatile semiconductor storage device, memory cell units of two-transistor structure are arranged in rows and columns and adjacent rows of memory cell units are isolated by a trench-type device isolation region. The spacing between the control gate electrode of a cell transistor and the gate electrode of a ... 05/17/07 - 20070108495 - Mnos memory devices and methods for operating an mnos memory devices A split-gate MNOS memory device comprises a thin dielectric layer between the memory gate and the silicon nitride trapping layer. The thin dielectric layer can block charge loss at low electric field and can allow hole injection at high electric fields. P-type polysilicon gates can be used to increase hole ... 05/10/07 - 20070102750 - Charge trap flash memory device, fabrication method thereof, and write/read operation control method thereof In one aspect, a charge trap flash memory device is provided which includes a semiconductor substrate, source and drain regions which are spaced apart in an active region of the semiconductor substrate to define a channel region therebetween, a tunneling dielectric layer located on the channel region, an organic polymer ... 05/10/07 - 20070102749 - Semiconductor memory device and method of fabricating the same A semiconductor memory device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and a NAND cell unit formed on the semiconductor layer ... 05/10/07 - 20070102748 - Gate electrode and mos transistor including gate and method of fabricating the same A gate electrode. The gate electrode includes a substrate, a gate dielectric layer formed thereon, and a gate conductive layer comprising a stack of polysilicon grains formed on the gate dielectric layer, wherein the average size of the polysilicon grains decreases gradually in a direction away from the substrate. The ... 05/10/07 - 20070102747 - Complementary carbon nanotube triple gate technology Disclosed is a CNT technology that overcomes the intrinsic ambipolar properties of CNTFETs. One embodiment of the invention provides either a stable p-type CNTFET or a stable n-type CNTFET. Another embodiment of the invention provides a complementary CNT device. In order to overcome the ambipolar properties of a CNTFET, source/drain ... 04/26/07 - 20070090444 - Nonvolatile memory device including nano dot and method of fabricating the same A nonvolatile memory device including a nano dot and a method of fabricating the same are provided. The nonvolatile memory device may include a lower electrode, an oxide layer on the lower electrode, a nano dot in the oxide layer and an upper electrode on the oxide layer. In example ... 04/26/07 - 20070090443 - Method of fabricating a semiconductor device having self-aligned floating gate and related device A semiconductor device such as a flash memory device having a self-aligned floating gate and a method of fabricating the same is provided. An embodiment of the device includes an isolation layer defining a fin body is formed in a semiconductor substrate. The fin body has a portion protruding above ... 04/26/07 - 20070090442 - Asymmetric floating gate nand flash memory A NAND-type flash memory device includes asymmetric floating gates overlying respective wordlines. A given floating gate is sufficiently coupled to its respective wordline such that a large gate (i.e., wordline) bias voltage will couple the floating gate with a voltage which can invert the channel under the floating gate. The ... 04/19/07 - 20070085130 - Tungsten-containing nanocrystal, an array thereof, a memory comprising such an array, and methods of making and operating the foregoing A nanocrystal (or quantum dot) memory cell includes a tier of separated tungsten or tungsten-containing nanocrystals on an insulative tunneling layer. The nanocrystals are formed by low pressure chemical vapor deposition. The remainder of the cell may be fabricated pursuant to conventional MOS protocols. Generally, Fowler-Nordheim tunneling occurs during write ... 04/19/07 - 20070085129 - Nitride read only memory device with buried diffusion spacers and method for making the same A method for making a nitride read only memory device with buried diffusion spacers is disclosed. An oxide-nitride-oxide (ONO) layer is formed on top of a silicon substrate, and a polysilicon gate is formed over the ONO layer. The polysilicon gate is formed less than a length of the ONO ... 04/05/07 - 20070075352 - Non-volatile semiconductor memory device, fabricating method of the same, and semiconductor memory system In a non-volatile semiconductor memory device typically of a MONOS type storing data by trapping charge in a multilayer film composed of a plurality of insulating films, which includes: source and drain regions of a second conductivity type disposed apart from each other in a semiconductor substrate of a first ... 04/05/07 - 20070075351 - Semiconductor devices and methods of manufacture thereof Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having at least two first gate electrodes comprising a first parameter, and an NMOS transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter ... 03/29/07 - 20070069276 - Multi-use memory cell and memory array A multi-use memory cell and memory array are disclosed. In one preferred embodiment, a memory cell is operable as a one-time programmable memory cell or a rewritable memory cell. The memory cell comprises a memory element comprising a semiconductor material configurable to one of at least three resistivity states, wherein ... 03/29/07 - 20070069275 - Bi-directional read/program non-volatile floating gate memory array, and method of formation A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is ... 03/22/07 - 20070063248 - High write and erase efficiency embedded flash cell An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating ... 03/15/07 - 20070057310 - Nonvolatile semiconductor memory device having element isolating region of trench type Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer ... 03/15/07 - 20070057309 - Nonvolatile semiconductor memory devices and methods of forming the same A nonvolatile semiconductor memory device includes a plurality of pillars protruding upward from a semiconductor substrate and having respective top surfaces and opposing sidewalls, a bit line on the top surfaces of the pillars and connecting a row of the pillars along a first direction, a pair of word lines ... 03/15/07 - 20070057308 - Electrode structure and method of manufacturing the same, phase-change memory device having the electrode structure and method of manufacturing the same Example embodiments of the present invention relate to an electrode structure, a method of manufacturing the electrode structure, a phase-change memory device having the electrode structure and a method of manufacturing the phase-change memory device. The electrode structure may include a pad, a first insulation layer pattern, a second insulation ... 03/15/07 - 20070057307 - Embedded flash memory devices on soi substrates and methods of manufacture thereof Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer ... 03/08/07 - 20070052001 - Nonvolatile semiconductor memory device and method of fabricating the same A nonvolatile semiconductor memory device and a method of fabricating the same are provided. The nonvolatile memory device may include a switching device and a storage node connected to the switching device. The storage node may comprise a lower electrode, a data storing layer, and an upper electrode. The data ... 03/08/07 - 20070052000 - Nonvolatile memory device and method for fabricating the same A nonvolatile memory device and method for fabricating the same are provided. The nonvolatile memory device includes an active region; a source region formed in the active region; a source line formed on the source region and electrically connected with the source region, to cross over the active region; word ... 03/01/07 - 20070045708 - Stacked bit line dual word line nonvolatile memory An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines ... 03/01/07 - 20070045707 - Memory device and manufacturing method thereof A memory device comprising a substrate, a first insulation layer, a charge storage layer, a second insulation layer, a gate electrode layer and source/drain regions is provided. The forbidden gap of the substrate is larger than the forbidden gap of silicon. The first insulation layer is disposed over the substrate. ... 03/01/07 - 20070045706 - Combined volatile and non-volatile memory device with graded composition insulator stack A memory device is fabricated with a graded composition tunnel insulator layer. This layer is formed over a substrate with a drain and a source region. The tunnel insulator is comprised of a graded SiC—GeC—SiC composition. A charge blocking layer is formed over the tunnel insulator. A trapping layer of ... 03/01/07 - 20070045705 - Floating-gate non-volatile memory and method of fabricating the same A floating gate non-volatile memory is composed of a semiconductor substrate within which active regions and isolation dielectrics are alternately arranged in a first direction; a word line extending in the first direction to intersect with the active regions and the isolation dielectrics; a plurality of floating gates disposed between ... 03/01/07 - 20070045704 - Non-volatile, resistive memory cell based on metal oxide nanoparticles, process for manufacturing the same and memory cell arrangement of the same Disclosed is a non-volatile memory cell including a first conductive electrode region, a second conductive electrode region and a memory region disposed therebetween. The memory region includes one or a plurality of metal oxide nanoparticles, which contact and electrically connect the first and the second electrode region via contact locations ... 02/22/07 - 20070040208 - Fabrication method and structure of semiconductor non-volatile memory device A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon ... 02/15/07 - 20070034935 - Nonvolatile semiconductor memory device and a method of the same A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which ... 02/15/07 - 20070034934 - Semiconductor memory device with a stacked gate including a floating gate and a control gate and method of manufacturing the same A semiconductor memory device includes first and second MOS transistors. The first MOS transistor is formed on a region enclosed by a first element isolating region and includes a first gate insulating film and a first gate electrode. The second MOS transistor is formed on a region enclosed by a ... 02/15/07 - 20070034933 - Flash memory device utilizing nanocrystals embedded in polymer A flash memory device with a nanoscale floating gate and a method of manufacturing thereof are disclosed. At least one embodiment of the present invention provides a much simpler and easier method of manufacturing nanocrystals (or nanocrystallines) for the flash memory device than the conventional method. Since the nanocrystals are ... 02/15/07 - 20070034932 - Nor flash memory devices and methods of fabricating the same A flash memory device includes active regions formed in a semiconductor substrate. The active regions include a cell array region, a high voltage transistor region and a low voltage transistor region. Gate structures are formed across the active regions, source and drain regions are formed at both sides of the ... 02/15/07 - 20070034931 - Systems and methods for memory structure comprising a pprom and an embedded flash memory A memory structure that combines embedded flash memory and PPROM. The PPROM can be used as a memory structure. The flash memory can be used, e.g., as air replacement cells or back up memory, or additional memory cells. The PPROM cells are stacked on top of the flash memory cells ... 02/15/07 - 20070034930 - Discrete trap non-volatile multi-functional memory device A multiple layer tunnel insulator is fabricated between a substrate and a discrete trap layer. The properties of the multiple layers determines the volatility of the memory device. The composition of each layer and/or the quantity of layers is adjusted to fabricate either a DRAM device, a non-volatile memory device, ... 02/15/07 - 20070034929 - Flash memory device and method of manufacturing the same A flash memory device and method of manufacturing the same includes a string structure having source select lines, a number of word lines and drain select lines, a first insulating film is filled between the word lines, between the word lines and the source select lines and between the word ... 02/01/07 - 20070023815 - Non-volatile memory device and associated method of manufacture A non-volatile memory device comprises a floating gate formed across an active region of a semiconductor substrate, and a control gate electrode formed over the floating gate. An insulation pattern is formed between the floating gate and the active region such that the insulation pattern makes contact with a bottom ... 02/01/07 - 20070023814 - Nonvolatile memory semiconductor device and method for manufacturing same A nonvolatile memory semiconductor device and a method for manufacturing thereof are provided to avoid deterioration of the tunnel insulating film to increase frequency of writing data on the nonvolatile memory semiconductor device and erasing thereof. Concentration of atomic nitrogen in a tunnel insulating film 151 of a nonvolatile memory ... 01/25/07 - 20070018227 - Three-gate transistor structure A transistor structure comprises a semiconductor element extending between a source zone and a drain zone, as well as three portions of gates disposed on different sides of the semiconductor element. Such a structure is especially compact and may be used as two or three transistors having independent respective functions. ... 01/18/07 - 20070012988 - High density nand non-volatile memory device Non-volatile memory devices and arrays are described that utilize dual gate (or back-side gate) non-volatile memory cells with band engineered gate-stacks that are placed above or below the channel region in front-side or back-side charge trapping gate-stack configurations in NAND memory array architectures. The band-gap engineered gate-stacks with asymmetric or ... 01/11/07 - 20070007576 - Multi-bit storageable non-volatile memory device A non-volatile memory device includes a channel region defined between a source region and a drain region, a charge storage film disposed on the channel region to store a charge, and a tunnel insulating film interposed between the channel region and the charge storage film to tunnel the charge, the ... 01/11/07 - 20070007575 - Nonvolatile memory cell with multiple floating gates formed after the select gate In a memory cell (110) having multiple floating gates (160), the select gate (140) is formed before the floating gates. In some embodiments, the memory cell also has control gates (170) formed after the select gate. Substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation ... 01/11/07 - 20070007574 - Semiconductor memory device and driving method of the same A semiconductor memory device includes a semiconductor substrate including a semiconductor layer on a first insulation film; a memory cell including a source and a drain formed in the semiconductor layer, and a floating body region provided between the source and the drain, the memory cell storing data according to ... 01/04/07 - 20070001210 - Non-volatile memory and operating method thereof A non-volatile memory having a gate structure, a pair of storage units and two assist gates is provided. The gate structure is disposed on the substrate. The storage units are disposed on the sidewalls of the gate structure. The assist gates are disposed on the respective sides of the gate ... 12/28/06 - 20060289922 - Non-volatile semiconductor memory device To achieve a high-speed and reliable read operation. A unit cell is constituted by a select gate 3 provided in a first region and on a substrate 1 with an insulating film 2 interposed inbetween, a floating gate 6a provided in a second region adjacent to the first region with ... 12/21/06 - 20060284237 - Phase change memory cells having a cell diode and a bottom electrode self-aligned with each other and methods of fabricating the same Integrated circuit devices are provided having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in a lower region of the contact hole and a bottom electrode in ... 12/21/06 - 20060284236 - Back-side trapped non-volatile memory device Non-volatile memory devices and arrays are described that utilize back-side trapped floating node memory cells with band-gap engineered gate stacks with asymmetric tunnel barriers. Embodiments of the present invention allow for direct tunneling programming and efficient erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier ... 12/21/06 - 20060284235 - Low power flash memory devices A buried bipolar junction is provided in a floating gate transistor flash memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors. These electrons are accelerated in a vertical electric field and injected over a barrier to a floating gate of ... 12/21/06 - 20060284234 - Structure of a non-volatile memory device and operation method A nonvolatile memory device, including composite gate structures formed on a substrate in series along a bit line (BL) direction. Each of the composite gate structures has a first storage gate, a second storage gate, and a selection gate between the two storage gates. Each of the composite gate structures ... 12/14/06 - 20060278914 - Semiconductor device A semiconductor device including a nonvolatile memory element, the nonvolatile memory element, including: a first region, a second region formed adjacent to the first region, and a third region formed adjacent to the second region; the nonvolatile memory element further including a semiconductor layer, a separating insulation layer which is ... 12/14/06 - 20060278913 - Non-volatile memory cells without diffusion junctions A plurality of memory cell stacks are formed over a substrate. The substrate does not have diffusion regions between each memory cell stack to link the memory cells. The cells are formed close enough such that the memory cells are linked serially by the electric fields generated by each floating ... 11/30/06 - 20060267070 - Gate coupling in floating-gate memory cells Methods and apparatus utilizing a stepped floating gate structure to facilitate reduced spacing between adjacent cells without significantly impacting parasitic capacitance. The stepped structure results in a reduced surface area of a first floating gate in close proximity to an adjacent floating gate with substantially no reduction in coupling area, ... 11/30/06 - 20060267069 - Nonvolatile semiconductor memory A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the ... 11/30/06 - 20060267068 - Semiconductor device and method for manufacturing semiconductor device When an electrode is formed over an organic layer, a temperature is limited because the organic layer can be influenced depending on a temperature in forming the electrode. Therefore, there are problems that an expected electrode cannot be formed, and miniaturization of an element is inhibited. The present invention provides ... 11/30/06 - 20060267067 - Semiconductor memory device and method of manufacturing the same A semiconductor memory device includes a memory cell which includes a first gate insulation film provided on the semiconductor substrate; a floating gate electrode provided on the first gate insulation film; a second gate insulation film provided on the floating gate electrode; a control gate electrode provided on the second ... 11/23/06 - 20060261398 - Nonvolatile memory device Disclosed is a nonvolatile memory device with cell and peripheral circuit regions confined on a substrate. Cell gate electrodes are arranged in the cell region while peripheral gate electrodes are arranged in the peripheral-circuit region. Each cell gate electrode includes stacked conductive and semiconductor layers, but the peripheral gate electrode ... 11/16/06 - 20060255394 - Flash memory device and method of manufacturing the same A flash memory device and method of manufacturing the same. The flash memory device includes a semiconductor substrate in which a first region where a cell region is formed, a second region where a peripheral region is formed, and a third region formed in the peripheral region at the boundary ... 11/16/06 - 20060255393 - N well implants to separate blocks in a flash memory device A semiconductor memory device that has an isolated area comprised of one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are comprised of the second conductivity and extend ... 11/02/06 - 20060244039 - Metal-poly integrated capacitor structure A metal-poly integrated capacitor structure that may be used in a charge pump circuit of a non-volatile memory. In one embodiment, the capacitor comprises a poly silicon layer, a first metal layer and a second metal layer. The first metal layer is positioned between the poly silicon layer and the ... 11/02/06 - 20060244038 - Split gate flash memory cell with ballistic injection A split floating gate flash memory cell is comprised of source/drain regions in a substrate. The split floating gate is insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The sections of the floating gate are ... 11/02/06 - 20060244037 - Semiconductor device and fabrication method thereof A semiconductor device includes a semiconductor substrate, an ONO (oxide/nitride/oxide) film provided on the semiconductor substrate, a control gate provided on the ONO film, a first low-resistance layer, and a second low-resistance layer in contact with the first low-resistance layer, the second low-resistance layer having a sheet resistance lower than ... 11/02/06 - 20060244036 - One time programmable eprom fabrication in sti cmos technology The formation of a one time programmable (OTP) transistor based electrically programmable read only memory (EPROM) cell (100) is disclosed. The cell (100) includes multiple concentric rings (108, 110) out of which gate structures are formed. An inner transistor based cell (130) formed from the inner ring (108) is shielded ... 11/02/06 - 20060244035 - Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for cmos The present invention provides a metal stack structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a Si-containing conductor and a Hf-based dielectric. This present invention stabilizes the flatband voltages and the threshold voltages by introducing a rare earth metal-containing layer into the material stack ... 10/26/06 - 20060237768 - Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which has a first source/drain region and a second source/drain region separated by a p-type channel ... 10/26/06 - 20060237767 - Semiconductor device with double barrier film A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has ... 10/26/06 - 20060237766 - Semiconductor device using solid phase epitaxy and method for fabricating the same A semiconductor device includes an epitaxial layer using a solid phase epitaxy (SPE) process; a first metal layer on the epitaxial layer; a nitride-based barrier metal layer on the first metal layer; a second metal layer on the barrier metal layer; and a metal silicide layer formed between the epitaxial ... 10/26/06 - 20060237765 - Eeprom and method of manufacturing the same An EEPROM includes a substrate, a first semiconductor layer and a second semiconductor layer formed on the substrate. The first semiconductor layer is isolated from the second semiconductor layer by a trench. A first source and a first drain are located at two opposing sides of the first semiconductor layer. ... 10/19/06 - 20060231886 - Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which has a first source/drain region and a second source/drain region separated by a p-type channel ... 10/19/06 - 20060231885 - Semiconductor device and method of fabricating the same The present invention provides a semiconductor device in which the gate is self-aligned to the device isolation film and a fabricating method thereof. A device isolation film restricting an active region is disposed on a portion of a semiconductor substrate, and a word line is across over the device isolation ... 10/19/06 - 20060231884 - Nonvolatile semiconductor device and method of manufacturing nonvolatile semiconductor device A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, ... 10/19/06 - 20060231883 - Semiconductor device A semiconductor memory device, firstly, has both the thickness of a tunnel film and that of a top film provided thereon and configured to be in the FN tunneling region (4 nm or more). The data retention characteristics can be improved by configuring both the thickness of a tunnel film ... 09/28/06 - 20060214215 - Semiconductor device The present invention provides a semiconductor device in which the gate is self-aligned to the device isolation film and a fabricating method thereof. A device isolation film restricting an active region is disposed on a portion of a semiconductor substrate, and a word line is across over the device isolation ... 09/28/06 - 20060214214 - Scalable spilt-gate flash memory cell with high source-coupling ratio A system and method provides an improved source-coupling ratio in flash memories. In one embodiment, a flash memory cell system with high source-coupling ratio includes at least a conventional floating gate device having a floating gate, a drain and a source. The floating gate is formed over a first junction ... 09/21/06 - 20060208305 - In-service reconfigurable dram and flash memory device A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical floating body transistor with dual gates, one on either side of a vertical pillar of ... 09/21/06 - 20060208304 - Three-dimensional memory devices Memory devices are disclosed. One example of a memory device may include two layers of memory arrays each containing at least four memory cells. In particular, the memory device includes two word lines commonly shared by the two layers of the memory arrays, with the word lines coupled with the ... 09/21/06 - 20060208303 - Semiconductor device with floating trap type nonvolatile memory cell and method for manufacturing the same The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, ... 09/21/06 - 20060208302 - Non-volatile memory device having charge trap layer and method of fabricating the same A non-volatile memory device having a charge trap layer and a method of fabricating the same are provided. The non-volatile memory device includes a semiconductor substrate having an active region and a field region in contact with the active region. A trench isolation layer is formed within the semiconductor substrate ... 09/21/06 - 20060208301 - Semiconductor memory device and method of driving a semiconductor memory device A semiconductor memory device includes a semiconductor layer; a source layer provided in the semiconductor layer; a drain layer provided in the semiconductor layer; a body region provided in the semiconductor layer between the source layer and the drain layer; a gate insulation film provided on the body region; and ... 09/14/06 - 20060202253 - Flash memory cell transistor and method for fabricating the same A flash memory cell transistor and a method for fabricating the same compensates a work function difference of a pMOS and a nMOS with a triple gate insulating film by using electron density trapped in a pMOS gate insulating film. The flash memory cell transistor comprises a p-well region and ... 09/14/06 - 20060202252 - Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height; ... 09/14/06 - 20060202251 - Scalable high performance non-volatile memory cells using multi-mechanism carrier transport The device comprises a plurality of select gates that are formed over a substrate. In one embodiment, the select gates are formed vertically on the sidewalls of trenches. The substrate includes a plurality of diffusion regions that are each formed between a pair of planar select gates. In a vertical ... 09/07/06 - 20060197138 - Use of selective epitaxial silicon growth in formation of floating gates Apparatus utilizing epitaxial silicon growth on a base structure of a floating gate of a floating-gate memory cell to increase the available coupling area of the floating gate while reducing the spacing between adjacent memory cells. The epitaxial silicon growth facilitates a reduction in spacing between adjacent cells beyond the ... 09/07/06 - 20060197137 - Memory devices, transistors, memory cells, and methods of making same A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel ... 09/07/06 - 20060197136 - Semiconductor memory device According to this invention, the NAND type flash memory of high reliability is realized. It provides a semiconductor memory device comprising: a plurality of memory cells; a plurality of word lines formed by a first gate wiring layer; a plurality of first transistors for providing voltages to said word lines; ... 08/31/06 - 20060192242 - Low power memory subsystem with progressive non-volatility The memory system is comprised of a plurality of memory arrays that are coupled to a processor. The memory arrays are comprised of non-volatile memory cells that have read/write speeds and charge retention times that are different from the other memory arrays of the system. Each of the memory cells ... 08/31/06 - 20060192241 - Non-volatile memory and manufacturing method thereof A non-volatile memory comprising a substrate, a stacked gate structure, a conductive spacer, an oxide/nitride/oxide layer, buried doping regions, a control gate and an insulating layer. The stacked gate structure is disposed on the substrate. The stacked gate structure comprises a gate dielectric layer, a select gate and a cap ... 08/31/06 - 20060192240 - Low power memory subsystem with progressive non-volatility The memory system is comprised of a plurality of memory arrays that are coupled to a processor. The memory arrays are comprised of non-volatile memory cells that have read/write speeds and charge retention times that are different from the other memory arrays of the system. Each of the memory cells ... 08/24/06 - 20060186454 - Semiconductor device and fabricating method thereof A method of fabricating a semiconductor device is described. A substrate having a memory cell region and a high voltage circuit region are provided. First and second source/drain regions are formed in the substrate within these two regions. A silicon oxide layer, a first conductive layer and a top layer ... 08/17/06 - 20060180848 - Wing gate transistor for integrated circuits A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the ... 08/17/06 - 20060180847 - Two-bit non-volatile memory devices including independently-controllable gate electrodes and methods for fabricating the same A non-volatile integrated circuit memory device includes a substrate including first and second source/drain regions therein and a channel region therebetween, a first memory cell on the channel region adjacent the first source/drain region, and a second memory cell on the channel region adjacent the second source/drain region. The first ... 08/17/06 - 20060180846 - Semiconductor memory device In a cell contact pad method, a consecutive dummy cell contact pad intersecting with a cell gate electrode is formed at an outer peripheral portion of the memory cell array. The dummy cell contact pad blocks liquid and gas to intrude through a void, and prevents the cell contact pad ... 08/17/06 - 20060180845 - Memory device with silicon rich silicon oxide layer and method of manufacturing the same A memory device with a silicon rich oxide layer and a method of manufacturing the same are provided. The memory device with a silicon rich oxide layer may include a semiconductor substrate, source/drain regions formed on the semiconductor substrate, and a gate structure formed on the semiconductor substrate. The gate ... 08/10/06 - 20060175653 - Nonvolatile nanochannel memory device using mesoporous material A nonvolatile nanochannel memory device using a mesoporous material. Specifically, a memory device is composed of a mesoporous material that is able to form nanochannels, in which a memory layer having metal nanoparticles or metal ions fed into the nanochannels is disposed between an upper electrode and a lower electrode. ... 08/10/06 - 20060175652 - Non-volatile memory and operating method thereof A non-volatile memory having memory cell columns is provided. Each memory cell column includes many memory cells having a charge-trapping layer and a column select unit. There are no gaps between the memory cells and between the column select unit and the memory cells. A source region and a drain ... 08/03/06 - 20060170028 - Non-volatile memory device, methods of fabricating and operating the same A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through ... 08/03/06 - 20060170027 - Nonvolatile memory device made of resistance material and method of fabricating the same A nonvolatile memory device using a resistance material and a method of fabricating the same are provided. The nonvolatile memory device includes a switching element, and a data storage part electrically connected to the switching element. In the data storage part, a lower electrode is connected to the switching element, ... 08/03/06 - 20060170026 - Non-volatile memory and fabricating method and operating method thereof A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are ... 07/27/06 - 20060163641 - Insulation film semiconductor device and method A semiconductor device and method of its manufacturing method are provided for realizing smaller low voltage transistors while maintaining the characteristics of high voltage transistors. A first transistor formation region is separated by selectively leaving first element-separating insulator film. A second transistor formation region is separated by selectively oxidized second ... 07/20/06 - 20060157773 - Non-volatile electrically alterable memory cell for storing multiple data and manufacturing thereof A memory cell that includes two control gates disposed laterally between two floating gates where each floating gate is capable of holding data. The memory cell is formed by placing a first polysilicon on a substrate of semiconductor material, on which a well is placed. The control gates are preferably ... 07/20/06 - 20060157772 - Nonvolatile memory device Provided is a nonvolatile memory device including: a storage element; a switching element electrically connected to the storage element; and a plurality of lead wirings electrically connected to the switching element, all of which are arranged on a substrate having an insulating surface, wherein the switching element includes an organic ... 07/06/06 - 20060145237 - Non-volatile memory device and method of manufacturing the same Provided are a non-volatile memory device and a method of manufacturing the same. The non-volatile memory device includes a gate insulating layer having a tunneling window formed therein. The tunneling window has a predetermined width parallel to a channel length direction and has a predetermined length perpendicular to the channel ... 07/06/06 - 20060145236 - Flash memory device and fabricating method thereof A flash memory device includes a floating gate formed on a substrate, sidewall gates formed on sidewalls of the floating gate, an interlayer insulating layer formed the floating gate and the sidewall gates, and a control gate formed on the interlayer insulating layer. The fabricating method of a flash memory ... 07/06/06 - 20060145235 - Erasable nonvolatile memory with sidewall storage A nonvolatile storage cell, integrated circuit (IC) including the cells and method of manufacturing the cells. A layered spacer (ONO) is formed at least at one sidewall of cell gates. Source/drain diffusions at each layered spacer underlap the adjacent gate. Charge may be stored at a layer (an imbedded nitride ... 06/29/06 - 20060138520 - Nonvolatile ferroelectric memory device A nonvolatile ferroelectric memory device is provided so as to control read/write operations of a nonvolatile memory cell using a channel resistance of the memory cell which is differentiated by polarity states of a ferroelectric material. In the memory device, an insulating layer is formed on a bottom word line, ... 06/29/06 - 20060138519 - Float gate memory device A float gate memory device comprises a bottom word line, a float channel layer formed on the bottom word line and kept at a floating state, a float gate, and a top word line formed on the float gate in parallel with the bottom word line. In the float gate ... 06/22/06 - 20060131633 - Integrated two device non-volatile memory The non-volatile memory cell is comprised of the series integration of a fixed threshold element and a bistable element. The fixed threshold element is formed over a substrate with a gate insulator layer and an access gate having a nitride layer. The bistable element is formed adjacent to the fixed ... 06/08/06 - 20060118853 - Nonvolatile semiconductor memory device having excellent charge retention and manufacturing process of the same There has been a problem in conventional Si-type floating-gate type nonvolatile semiconductor memory devices that the charge retention characteristic is low due to insufficiently large electron affinity of Si, therefore improvement of the memory performances, such as scaling down of a memory cell and increasing operation speed, have been difficult ... 05/25/06 - 20060108627 - Nand flash memory devices including multi-layer memory cell transistor structures and methods of fabricating the same An integrated circuit memory device on a multi-layer substrate includes first and second selection transistors, a first plurality of serially connected memory cell transistors on a first substrate layer, and a second plurality of serially connected memory cell transistors on a second substrate layer. The first plurality of serially connected ... 05/04/06 - 20060091447 - Semiconductor device and its manufacture method A semiconductor device includes: a first insulating layer with a flat surface formed over a semiconductor substrate structure in which a plurality of semiconductor elements are formed; column-like conductive plugs formed to penetrate the first insulating layer in the thickness direction; elongated wall-like conductive plugs formed through the first insulating ... 05/04/06 - 20060091446 - Non-volatile semiconductor memory device and its manufacturing method In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon ... 05/04/06 - 20060091445 - Semiconductor device and method for fabricating thereof A silicon nitride film, which is a second hard mask, is dry etched to be removed completely. The silicon nitride film, which is formed on a sidewall of a silicon nitride film used as a first hard mask, has a relatively low etching rate. Therefore, if the silicon nitride film ... 05/04/06 - 20060091444 - Double word line memory structure and manufacturing method thereof A memory structure comprises two bit lines, a first gate dielectric, a second gate dielectric, at least one first gate, a second gate and a third gate, a first dielectric spacer and a second dielectric spacer, where the two bit lines are formed in the semiconductor substrate, the first gate ... 04/27/06 - 20060086967 - Nonvolatile memory device and method for fabricating the same A structure of non-volatile memory has a plurality of buried bit lines in a substrate, extending along a first direction. Selection gate structure lines are located between the buried bit lines. A plurality of stack dielectric films on the both sides of the selection gate structure lines serving as a ... 04/27/06 - 20060086966 - Memory device comprising single transistor having functions of ram and rom and methods for operating and manufacturing the same A memory device including a single transistor having functions of RAM and ROM and methods for operating and manufacturing the same are provided. The memory device includes a single transistor formed on a substrate. The transistor may be a memory transistor having a gate with a nonvolatile memory element, or ... 04/20/06 - 20060081907 - Nonvolatile semiconductor memory device having grooves isolating the floating electrodes of memory cells and method of manufacturing the nonvolatile semiconductor memory device A plurality of nonvolatile memory elements formed on element regions respectively isolated by element isolation regions on a main surface of a first conductive type semiconductor substrate, the nonvolatile semiconductor memory elements comprising a gate insulating film formed on the main surface of the semiconductor substrate, a plurality of floating ... 04/20/06 - 20060081906 - Semiconductor device and method of manufacturing the same Disclosed herein is a semiconductor device and method of manufacturing the same. A step between a memory cell formed in a cell region and a transistor formed in a peripheral circuit region is minimized, and the height of a gate in the memory cell is minimized. Accordingly, subsequent processes are ... 04/13/06 - 20060076605 - Improved flash forward tunneling voltage (ftv) flash memory device A FLASH memory device comprising a substrate having a gate conductor formed thereover is provided. The gate conductor comprises a gate with a floating gate oxide layer formed thereon, the floating gate oxide layer including respective lateral tip portions, whereby the forward tunneling voltage of the FLASH memory is improved. ... 03/23/06 - 20060060910 - Nonvolatile memory and manufacturing method and operating method thereof A nonvolatile memory is provided. The memory includes a select transistor and a trench transistor. The select transistor is formed on the substrate. The select transistor includes a first gate formed on the substrate and first and second source/drain regions formed in the substrate next to the first gate. The ... 03/16/06 - 20060054964 - Semiconductor device and method for fabricating a region thereon A semiconductor device comprises a transistor body of boron doped semiconductor substrate and a conterminous isolating area formed of insulating material, wherein an oxy-nitride layer is between the transistor body and the isolating area. This invention can be used in a transistor body for example in an NROM cell. ... 03/16/06 - 20060054963 - Non-volatile and non-uniform trapped-charge memory cell structure and method of fabrication A memory cell having a charge-trapping structure in the form of a layer of conductive clusters disposed between upper and lower insulator layers is disclosed. The memory cell can otherwise be constructed and operated similarly to a nitride read-only memory cell. ... 03/09/06 - 20060049447 - Antimony precursor, phase-change memory device using the antimony precursor, and method of manufacturing the phase-change memory device An antimony precursor including antimony, nitrogen and silicon, a phase-change memory device using the same, and a method of making the phase-change memory device. The phase-change memory device may have a phase-change film of a Ge2—Sb2—Te5 material including nitrogen and silicon. ... 03/02/06 - 20060043457 - Nonvolatile semiconductor memory device having a recessed gate and a charge trapping layer and methods of forming the same, and methods of operating the same A nonvolatile semiconductor memory device includes a substrate having a trench therein, a gate electrode in the trench, and a plurality of source/drain regions in the substrate adjacent the gate electrode. A pair of channel regions extends along sidewalls of the trench between respective pairs of adjacent source/drain regions. A ... 03/02/06 - 20060043456 - Protection of tunnel dielectric using epitaxial silicon Layers of epitaxial silicon are used to protect the tunnel dielectric layer of a floating-gate memory cell from excessive oxidation or removal during the formation of shallow trench isolation (STI) regions. Following trench formation, the layers of epitaxial silicon are grown from silicon-containing layers on opposing sides of the tunnel ... 03/02/06 - 20060043455 - Multiple-depth sti trenches in integrated circuit fabrication Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a ... 02/23/06 - 20060038218 - Semiconductor integrated circuit device A semiconductor integrated circuit device includes first, second gate electrodes, first, second diffusion layers, contact electrodes electrically connected to the first diffusion layers, a first insulating film which has concave portions between the first and second gate electrodes and does not contain nitrogen as a main component, a second insulating ... 02/16/06 - 20060033142 - Non-volatile memory device and method for manufacturing the same An increase of charge storing capacity, prevention of an over-erase, and a reduction of ΔVth may be achieved when a 2-bit/cell non-volatile memory device includes a gate of a predetermined width above a semiconductor substrate, an insulating layer between the gate and the semiconductor substrate and at lateral sides of ... 02/09/06 - 20060027854 - Non-volatile memory device and method of fabricating the same A non-volatile memory device having an asymmetric channel structure is provided. The non-volatile memory device includes a semiconductor substrate, a source region and a drain region which are formed in the semiconductor substrate and doped with n-type impurities, a trapping structure which includes a tunneling layer, which is disposed on ... 02/09/06 - 20060027853 - Semiconductor storage device and method of manufacturing same Disclosed is a semiconductor storage device having a trench around a bit-line diffusion region in an area of a p-well, which constitutes a memory cell area, that is not covered by a word line and a select gate that intersects the word line. An insulating film is buried in the ... 02/02/06 - 20060022252 - Nonvolatile memory device and method of fabricating the same There are provided a nonvolatile memory device and a method of fabricating the same. A gate region of the nonvolatile memory device is formed as a stack structure including a tunnel oxide layer, a trapping layer, a blocking layer and a control gate electrode. The trapping layer is formed of ... 01/26/06 - 20060017092 - Method for simultaneously fabricating ono-type memory cell, and gate dielectrics for associated high voltage write transistors and gate dielectrics for low voltage logic transistors by using issg Conventional fabrication of top oxide in an ONO-type memory cell stack usually produces Bird's Beak. Certain materials in the stack such as silicon nitrides are relatively difficult to oxidize. As a result oxidation does not proceed uniformly along the multi-layered height of the ONO-type stack. The present disclosure shows how ... 01/19/06 - 20060011965 - Non-volatile flash memory device having at least two different channel concentrations and method of fabricating the same In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding ... 01/12/06 - 20060006455 - Memory cell with polysilicon local interconnects Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, ... 01/12/06 - 20060006454 - Electrically alterable memory cell A nonvolatile memory cell is provided. The cell has a charge filter, a tunneling gate, a ballistic gate, a charge storage layer, a source, and a drain with a channel defined between the source and drain. The charge filter permits transporting of charge carriers of one polarity type from the ... 01/12/06 - 20060006453 - Nonvolatile semiconductor memory device and method of fabricating the same In a nonvolatile semiconductor memory device, and a method of fabricating the same, the nonvolatile semiconductor memory device includes a cell doping region and source/drain regions in a semiconductor substrate, the cell doping region being doped as a first conductive type, a channel region disposed between the source/drain regions in ... 01/12/06 - 20060006452 - Eeprom device and manufacturing method thereof Provided is an EEPROM device and a method of manufacturing the same. The EEPROM device is composed of one cell including a memory transistor and a selection transistor located in series on a semiconductor substrate, and includes a source region located on a side region of a memory transistor, a ... 01/12/06 - 20060006451 - Use of selective epitaxial silicon growth in formation of floating gates Methods and apparatus utilizing epitaxial silicon growth on a base structure of a floating gate of a floating-gate memory cell to increase the available coupling area of the floating gate while reducing the spacing between adjacent memory cells. The epitaxial silicon growth facilitates a reduction in spacing between adjacent cells ... 01/05/06 - 20060001074 - Three dimensional flash cell A floating gate memory cell includes isolation regions between adjacent cells, and a staggered pattern of columns of cells. Word lines are formed parallel to control gate structures. ... 01/05/06 - 20060001073 - Use of voids between elements in semiconductor structures for isolation A flash EEPROM or other type of memory cell array having adjacent charge storage elements is formed with a gas filled void between them in order to reduce the level of capacitive coupling between storage elements, thus reducing cross-coupling between charge storage elements and resulting errors occurring in the data ... 12/22/05 - 20050280072 - Test mode decoder in a flash memory Embodiments of the present invention include an interface circuit to put an integrated circuit into a test mode and a decoder to decode one or more commands provided to the integrated circuit. The decoder includes sub-circuits, and each sub-circuit has a number of transistors coupled in series. The transistors coupled ... 12/22/05 - 20050280071 - Three dimensional flash cell A floating gate memory cell includes isolation regions between adjacent cells, and a staggered pattern of columns of cells. Word lines are formed parallel to control gate structures. ... 12/22/05 - 20050280070 - Semiconductor memory device and method of manufacturing the same A semiconductor memory device includes: a semiconductor layer which is formed on an insulating layer; a plurality of transistors which are formed on the semiconductor layer and arranged in a matrix form, each of the transistors having a gate electrode, a source region and a drain region, the electrodes in ... 12/22/05 - 20050280069 - Semiconductor device and method of manufacturing the same A semiconductor device using a high dielectric constant insulator having reduced leak current as an interelectrode insulator is provided by comprising a first insulator formed on a semiconductor substrate, a first gate electrode formed on the first insulator, a second gate electrode formed above the first gate electrode, and a ... 12/22/05 - 20050280068 - Flash memory cell and manufacturing method thereof A flash memory cell includes a first conductive type substrate, a stacked gate structure, a first conductive type source/drain region, a metal silicide layer, an inter-layer dielectric layer and a contact plug. The first conductive type substrate has a second conductive type shallow well already formed thereon. The metal silicide ... 12/15/05 - 20050275009 - Nonvolatile memory device A nonvolatile memory device includes: a semiconductor layer of a first conductivity type in which a first region, a second region, and a third region are partitioned by an isolation insulating layer; a semiconductor section of a second conductivity type provided in the first region and functioning as a control ... 12/15/05 - 20050275008 - [non-volatile memory and fabrication thereof] A method for fabricating a non-volatile memory having two bits per cell is described. In the method, a substrate having a gate dielectric layer and a linear conductor thereon is provided, and a trapping layer is formed on the substrate and two sidewalls of the linear conductor. Two conductive spacers ... 12/08/05 - 20050269620 - Capacitor structures, and dram arrays A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second ... 11/24/05 - 20050258469 - Magnetic memory with self-aligned magnetic keeper structure A magnetic tunneling junction (MTJ) memory cell is formed with a keeper structure on its upper conductor (write line). The keeper structure is formed by a self aligned process as three pieces: two vertical soft magnetic side pieces contacting an upper soft magnetic layer. The structure so formed completely surrounds ... 11/24/05 - 20050258468 - Dual work function metal gate integration in semiconductor devices The present invention provides, in one embodiment, a process for forming a dual work function metal gate semiconductor device (100). The process includes providing a semiconductor substrate (105) having a gate dielectric layer (110) thereon and a metal layer (205) on the gate dielectric layer. A work function of the ... 11/24/05 - 20050258467 - Nano-crystal non-volatile memory device employing oxidation inhibiting and charge storage enhancing layer A non-volatile memory device and a method for fabricating the non-volatile memory device employ at least one charge storage dot formed upon a substrate. At least one of an oxidation inhibiting layer and a charge storage enhancing layer is formed upon the charge storage dot. A silicon nitride material layer ... 11/10/05 - 20050247971 - Nonvolatile memory device and method for fabricating the same A nonvolatile memory device and a method for fabricating the same is disclosed, to prevent a “smiling” phenomenon in an ONO layer, thereby improving the programming and erasing characteristics, reliability and yield. The device generally includes a semiconductor substrate; a gate insulating layer, a selection gate and a first insulating ... 11/10/05 - 20050247970 - Memory device including a dielectric multilayer structure and method of fabricating the same In a memory device including a dielectric multilayer structure, and a method of fabricating the same, the memory device includes a semiconductor substrate, a first impurity region and a second impurity region spaced apart from each other in the semiconductor substrate, and a gate structure formed on the semiconductor substrate ... 11/10/05 - 20050247969 - Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device includes a plurality of memory cells. A couple of bits of data can be stored in the memory cell, the stored data being controlled according to resistance values of first and second variable resistance regions. One of the plurality of memory cells shares its first ... 11/03/05 - 20050242389 - Crossbar array microelectronic electrochemical cells The present invention provides microelectronic electrochemical structures and related fabrication methods. A composite microelectronic structure is provided that includes first and second conductors dielectrically isolated from one another at a crossing thereof, the crossing surrounded by a dielectric material. A portion of the dielectric material around the crossing of the ... 11/03/05 - 20050242388 - Flash memory cell, flash memory device and manufacturing method thereof The present invention relates to a flash memory cell comprising a silicon substrate having an active region comprising a channel region and source-/drain-regions, the active region comprising a projecting portion, which projecting portion at least comprising said channel region; a tunneling dielectric layer formed on the surface of said active ... 11/03/05 - 20050242387 - Flash memory device having a graded composition, high dielectric constant gate insulator A graded composition, high dielectric constant gate insulator is deposited between a substrate and floating gate in a flash memory cell transistor. If the composition of the gate insulator is closer to the high-k material near the substrate, the electron barrier for hot electron injection will be lower. If the ... 10/27/05 - 20050236659 - Non-volatile memory cell and method of forming the same A non-volatile memory cell comprising a transistor and two plane capacitors. In the memory cell, a switching device is disposed on a substrate, a first plane capacitor having a first doped region and a second plane capacitor having a second doped region. The switching device and the first and second ... 10/20/05 - 20050230736 - Nonvolatile semiconductor memory device In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the ... 10/13/05 - 20050224858 - [non-volatile memory structure and manufacturing method thereof] A non-volatile memory including a substrate, a plurality of gate structures, a plurality of select gate structures, spacers and source region/drain region is provided. Each gate structure on the substrate further includes a bottom dielectric layer, an electron trapping layer, an upper dielectric layer, a control gate and a cap ... 09/29/05 - 20050212032 - Fabrication of conductive lines interconnecting first conductive gates in nonvolatile memories having second conductive gates provided by conductive gate lines, wherein the adjacent conductive gate lines for the adjacent columns are spaced from each other In a nonvolatile memory, the select gates (144S) are formed from one conductive layer (e.g. polysilicon or polyside), and the wordlines (144) interconnecting the select gates are made from a different conductive layer (e.g. metal). The wordlines overlie an dielectric (302, 304, 310) formed over control gate lines (134). Each ... 09/22/05 - 20050205921 - Gain cell type non-volatile memory having charge accumulating region charges or discharged by channel current from a thin film channel path A very thin semiconductor film is used for channels of semiconductor memory elements such that leak currents are reduced by the quantum-mechanical containment effect in the direction of film thickness. The amount of electrical charge accumulated in each charge accumulating region is used to change conductance between a source and ... 09/15/05 - 20050199938 - Nonvolatile semiconductor memory and a fabrication method for the same A nonvolatile semiconductor memory includes a plurality of memory cell transistors configured with a first floating gate, a first control gate, and a first inter-gate insulating film each arranged between the first floating gate and the first control gate, respectively, and which are aligned along a bit line direction; device ... 09/15/05 - 20050199937 - 3d flash eeprom cell and methods of implementing the same A 3 Dimensional EEPROM cell layout, process control, and device model means are proposed. This cell construct uses the pointing shapes of the intrinsic conducting electrodes, thin and high dielectric insulators to customize signal coupling capacitors between intrinsic terminals, and therefore to optimize cell efficiency and operating voltages. Array of ... 09/15/05 - 20050199936 - Nonvolatile memory solution using single-poly pflash technology A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly ... 09/01/05 - 20050189580 - Method of forming a low voltage gate oxide layer and tunnel oxide layer in an eeprom cell A method of fabricating a non-volatile memory embedded logic circuit having a low voltage logic gate oxide layer and tunnel oxide layer is described. Both the low voltage logic gate oxide and the tunnel oxide layers are formed in a single step, thereby reducing the number of overall processing steps ... 09/01/05 - 20050189579 - Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, ... 08/25/05 - 20050184330 - Nonvolatile memories and methods of fabrication In a nonvolatile memory, substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions are dielectric regions protruding above the substrate. Then select gate lines (140) are formed. Then a floating gate layer (160) is deposited. The floating gate layer is etched until the substrate ... 08/25/05 - 20050184329 - Multi-layer memory arrays Multi-layer memory arrays and methods are provided. A memory array has two or more layers of memory material, each layer of memory material having an array of memory cells. A first contact penetrates through each layer of memory material in a first plane and is electrically connected to each layer ... 08/18/05 - 20050179078 - Non-volatile memory devices including high-voltage transistors and methods of fabricating the same Non-volatile memory devices are provided including a cell array having a word line and a bit line. A row decoder is coupled to the word line and configured to apply word line voltages to the word line. A first high voltage transistor is coupled to the row decoder and is ... 08/11/05 - 20050173751 - Semiconductor memory device A nonvolatile semiconductor memory device that uses inversion layers formed on a surface of its semiconductor substrate as data lines, which is capable of satisfying the requirements of suppressing both characteristic variation among memory cells and bit cost. In order to achieve the above object, in the memory device, a ... 08/04/05 - 20050167730 - Cell structure of nonvolatile memory device The invention is directed to a nonvolatile memory device. Each memory cell is formed to have the depletion mode operation by doped opposite conductive-type dopants to the substrate at the surface region under the gate electrode, so that the depletion memory cell is formed. The charge-storing structure layer is, for ... 08/04/05 - 20050167729 - Self-aligned split-gate nonvolatile memory structure and a method of making the same Provided are non-volatile split-gate memory cells having self-aligned floating gate and the control gate structures and exemplary processes for manufacturing such memory cells that provide improved dimensional control over the relative lengths and separation of the split-gate elements. Each control gate includes a projecting portion that extends over at least ... 08/04/05 - 20050167728 - Single-poly 2-transistor based fuse element An electrically programmable transistor fuse having a double-gate arrangement disposed in a single layer of polysilicon in which a first gate is disposed overlapping a portion of a source region and a second gate is insulated from the first gate and disposed overlapping a portion of a drain region. The ... 07/14/05 - 20050151184 - Dielectric layer for semiconductor device and method of manufacturing the same A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides. ... 07/07/05 - 20050145919 - [multi-level memory cell] A multi-level memory cell including a substrate, a tunneling dielectric layer, a charge-trapping layer, a top dielectric layer, a gate and a pair of source/drain regions is provided. The tunneling dielectric layer, the charge-trapping layer and the top dielectric layer are sequentially formed between the substrate and the gate. The ... 06/30/05 - 20050139895 - Non-volatile memory device and method for fabricating the same Non-volatile memory device, and method for fabricating the same are disclosed. By forming floating gate trenches in memory regions and filling the trenches with floating gate material, a step height of a with the floating gate/ONO/control gate structure is reduced to the level of a gate in a logic block, ... 06/30/05 - 20050139894 - Nonvolatile memory device and methods of fabricating the same A method of fabricating a nonvolatile memory device including forming a plurality of device isolation layers in a semiconductor substrate to define a plurality of active regions, sequentially depositing an insulating layer and a first conductive layer on the semiconductor substrate, and forming a hard mask pattern on the first ... 06/30/05 - 20050139893 - Non-volatile flash semiconductor memory and fabrication method In a semiconductor memory, a plurality of FinFET arrangements with trapping layers or floating gate electrodes as storage mediums are present on respective top sides of fins made from semiconductor material. The material of the gate electrodes is also present on two side walls of the fins, in order to ... 06/23/05 - 20050133850 - Method for forming a box shaped polygate A method for forming an improved etching hardmask oxide layer in a polysilicon etching process including providing a planarized semiconductor wafer process surface including adjacent first exposed polysilicon portions and exposed oxide portions; selectively etching through a thickness portion of the exposed oxide portions; thermally growing an oxide hardmask layer ... 06/23/05 - 20050133849 - Semiconductor memory device having self-aligned charge trapping layer and method of manufacturing the same A semiconductor memory device having a self-aligned charge trapping layer and a method of manufacturing the same in which a consistent length of an ONO layer is ensured. Here, an insulating stacked structure is self-aligned to a bottom surface of conductive spacers. ... 06/16/05 - 20050127427 - Method and structure to improve the gate coupling ratio (gcr) for manufacturing a flash memory device Method and structure to improve the gate coupling ratio (GCR) for manufacturing a flash memory device are provided. The method and structure include the following steps. A gate oxide layer, a first semiconductor layer, and an insulating layer are formed sequentially over a provided semiconductor substrate. An etching process is ... 06/09/05 - 20050121715 - Nonvolatile memory with spacer trapping structure The present invention discloses a nonvolatile memory with spacer trapping structure, the nonvolatile memory comprising a semiconductor substrate. A gate oxide is formed on the semiconductor substrate. A gate structure is formed on the gate oxide. An isolation layer is formed over the sidewall of the gate structure. First spacers ... 06/09/05 - 20050121714 - Non-volatile two-transistor semiconductor memory cell and method for producing the same The invention relates to a nonvolatile semiconductor memory cell and to an associated fabrication method, a source region (7), a drain region (8) and a channel region lying in between being formed in a substrate (1). In order to realize locally delimited memory locations (LB, RB), an electrically non-conductive charge ... 06/02/05 - 20050116279 - Flash memory devices and methods of fabricating the same Flash memory devices and methods of fabricating the same are disclosed. A disclosed method comprises doping at least one active region of a substrate, and forming an etching mask layer on the active region. The etching mask layer defines an opening exposing a portion of the active region. The disclosed ... ### FreshPatents.com Support - Terms & Conditions |