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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Insulated Gate Capacitor Or Insulated Gate Transistor Combined With Capacitor (e.g., Dynamic Memory Cell) > Capacitor Coupled To, Or Forms Gate Of, Insulated Gate Field Effect Transistor (e.g., Non-destructive Readout Dynamic Memory Cell Structure) Capacitor Coupled To, Or Forms Gate Of, Insulated Gate Field Effect Transistor (e.g., Non-destructive Readout Dynamic Memory Cell Structure)Capacitor Coupled To, Or Forms Gate Of, Insulated Gate Field Effect Transistor (e.g., Non-destructive Readout Dynamic Memory Cell Structure) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/03/08 - 20080001199 - Semiconductor storage device A semiconductor storage device floats the gate of a conventional transistor between two capacitors to store a logic state which can be utilized to store the condition of a circuit such as a latching type circuit such as a flip-flop or register prior to a power down operation to save ... 12/06/07 - 20070278548 - Semiconductor device and method of manufacturing the same A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and ... 11/29/07 - 20070272961 - Capacitor below the buried oxide of soi cmos technologies for protection against soft errors Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and ... 11/08/07 - 20070257292 - Wireless chip An ID tag capable of communicating data wirelessly, the size of which is reduced, and where the size of an IC chip is reduced, a limited area of the chip is effectively used, current consumption is reduced, and communication distance is prevented from decreasing. The ID tag of the invention ... 10/18/07 - 20070241382 - Semiconductor integrated circuit device and process for manufacturing the same A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of ... 10/04/07 - 20070228441 - Display device including thin film transistor A flat panel display includes a gate line, a data line, and a power supply line and a plurality of pixels connected to the lines, wherein each of the pixels includes a first thin film transistor that includes an active layer having a channel region, a source region, and a ... 06/21/07 - 20070138528 - Memory structure for reduced floating body effect Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion region and the accompanying electrostatic potential created. In a preferred embodiment, a word line is recessed into ... 05/31/07 - 20070120168 - Metal semiconductor field effect transistors (mesfets) having channels of varying thicknesses and related methods A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The unit cell includes a MESFET having a source, a drain and a gate. The gate is between the source and the drain and on a channel layer of the MESFET. The channel layer has a first thickness on ... 05/03/07 - 20070096184 - Semiconductor device and method for fabricating the same A gate insulating film and a gate electrode are formed on an active region of a semiconductor substrate. A sidewall forming an L shape in cross section is formed on the sides of the gate electrode. Source/drain regions are formed in regions of the semiconductor substrate located outside an area ... 05/03/07 - 20070096183 - Semiconductor device and method for fabricating the same In a semiconductor device including a MIS transistor with a FUSI gate electrode and a polysilicon resistor, a portion of the polysilicon resistor provided in a contact formation region is silicided simultaneously with the gate electrode or an impurity diffusion region. ... 01/18/07 - 20070012982 - Multipurpose metal fill The present invention adds a plurality of substrate barriers for reducing substrate noise. The barriers, consisting of a plurality of equally sized n-well regions formed within the p-substrate, are formed between the analog and digital portions and on at least one side of sensitive analog circuits. A MOSFET transistor configured ... 10/26/06 - 20060237759 - Semiconductor device manufacturing method and semiconductor device A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers (82) are provided in ... 09/28/06 - 20060214212 - Semiconductor device and method of manufacturing semiconductor device First active region and second and third active regions are defined in a semiconductor substrate within a memory cell area and a logic circuit area, respectively. First to third MOS transistors are formed in the first to third active regions, respectively. As viewed from above, the length of the first ... 09/07/06 - 20060197133 - Mim capacitor including ground shield layer An MIM capacitor includes a substrate, a capacitor part having a structure in which a bottom electrode, a dielectric layer and a top electrode are laminated in order, and a ground shield layer formed between the bottom electrode of the capacitor part and the substrate and connected to a predetermined ... 08/24/06 - 20060186449 - Semiconductor device and manufacturing method therof A semiconductor device and a manufacturing method thereof which enable to secure high yield and increase the capacity of a capacitor are provided. The semiconductor device according to the present invention includes: a plurality of capacitor layers laminated, each capacitor layer including a plurality of storage electrodes, a capacity insulating ... 08/17/06 - 20060180842 - Capacitor, method of making the same, filter using the same, and dielectric thin film used for the same The capacitor (10) in accordance with the present invention comprises a lower electrode (14A), a dielectric layer (16) including an SiO2 layer (20) formed on the lower electrode (14A) and an Si3N4 layer (22) formed on the SiO2 layer (20), and an upper electrode (14B) formed on the dielectric layer ... 08/10/06 - 20060175650 - Memory cells with vertical transistor and capacitor and fabrication methods thereof Memory cells with vertical transistor and capacitor and fabrication methods thereof. The memory cell comprises a substrate with a trench. A capacitor is disposed at the bottom of the trench. A first conductive layer is electrically coupled to the capacitor. The first conductive layer is isolated the substrate by a ... 07/27/06 - 20060163635 - Capacitor below the buried oxide of soi cmos technologies for protection against soft errors Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and ... 07/20/06 - 20060157768 - Semiconductor device and method for fabricating the same In a method for fabricating a semiconductor device according to the present invention, gate injection for an n-type MIS transistor region is performed with an n-type decoupling capacitor region covered. Thus, compared to a known method, an n-type impurity concentration in a capacitor electrode in the n-type decoupling capacitor region. ... 07/13/06 - 20060151822 - Dram with high k dielectric storage capacitor and method of making the same A dynamic random access memory cell that includes a transistor formed in a semiconductor body. A capacitor is coupled to the transistor and includes a first capacitor plate formed from silicon. A metal layer is adjacent to and electrically coupled to the first capacitor plate. A capacitor dielectric layer is ... 06/29/06 - 20060138513 - Capacitors for semiconductor memory devices and methods of forming the same A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, ... 06/29/06 - 20060138512 - Semiconductor storage device A semiconductor storage device is provided, which inhibits shorts between cells to improve operational reliability and contributes to high-speed operation. An active region (7) where DRAM cells are formed is defined by an isolation trench (40) formed in a silicon substrate (1). The isolation trench (40) has an isolation insulating ... 06/22/06 - 20060131632 - Dram device having capacitor and method thereof In a DRAM device having a capacitor and a method thereof, the capacitor included in the device is characterized to have a lower electrode that passes through a plurality of interlayer insulating layers. A first interlayer insulating layer is formed on a semiconductor substrate. A first contact plug layer is ... 06/15/06 - 20060124981 - Dram technology compatible processor/memory chips The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A number of non-volatile ... 06/15/06 - 20060124980 - Stacked capacitor-type semiconductor storage device and manufacturing method thereof First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film ... 01/12/06 - 20060006444 - Selective epitaxy vertical integrated circuit components and methods Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are vertically oriented. These structures have regions that are doped in situ during selective epitaxial growth of the component body. These components are grown directly in electrical communication lines. Moreover, ... 12/15/05 - 20050275005 - Metal-insulator-metal (mim) capacitor and method of fabricating the same In a MIM capacitor, and method of fabricating the same, the MIM capacitor includes an interlayer insulating layer on a semiconductor substrate, a lower metal interconnection and a lower metal electrode in the interlayer insulating layer, an intermetal dielectric layer covering the lower metal interconnection, the lower metal electrode, and ... 08/25/05 - 20050184325 - Integrated dynamic random access memory element, array and process for fabricating such elements An integrated dynamic random access memory element includes two cells for the storage of two respective bits. A source region and a drain region are included. Each cell comprises a field-effect transistor having a gate and an intermediate portion which extend between the source and drain regions. A channel is ... 07/28/05 - 20050161722 - Memory circuitry with oxygen diffusion barrier layer received over a well base A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semiconductor substrate. A portion of the well forming layer ... 07/21/05 - 20050156219 - Bias-independent capacitor based on superposition of nonlinear capacitors for analog/rf circuit applications A first MOS-on-NWELL device is formed on a substrate and has its pickup terminals optionally connected together. A second MOS-on-NWELL device is formed on the substrate and has its pickup terminals optionally connected together. A gate of the first MOS-on-NWELL device is connected to the pickup terminals of the second ... 06/23/05 - 20050133843 - Semiconductor device and method of manufacturing a semiconductor device A semiconductor device comprises a semiconductor substrate; a first insulation layer formed on the semiconductor substrate; a semiconductor layer insulated from the semiconductor substrate by the insulation layer; a source region of a first conduction type and a drain region of the first conduction type formed in the semiconductor layer; ... 06/16/05 - 20050127421 - Semiconductor module having an insulation layer and method for fabricating a semiconductor module having an insulation layer A semiconductor module is described which is essentially constructed from a silicon material and has an insulation layer for example in the form of a gate insulation layer or a MOS transistor or in the form of an insulation layer of a memory cell for a dynamic memory module. The ... 06/02/05 - 20050116274 - Semiconductor device having isolation pattern in interlayer insulating layer between capacitor contact plugs and methods of fabricating the same A semiconductor device having an isolation pattern inside an interlayer insulating layer between capacitor contact plugs and methods of fabrication the same: The semiconductor device includes an interlayer insulating layer covering a semiconductor substrate. At least two contact plugs passing the interlayer insulating layer and connected to the semiconductor substrate. ... ### FreshPatents.com Support |