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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > Insulated Gate Capacitor Or Insulated Gate Transistor Combined With Capacitor (e.g., Dynamic Memory Cell) Insulated Gate Capacitor Or Insulated Gate Transistor Combined With Capacitor (e.g., Dynamic Memory Cell)Insulated Gate Capacitor Or Insulated Gate Transistor Combined With Capacitor (e.g., Dynamic Memory Cell) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/31/08 - 20080023743 - Semiconductor memory device and manufacturing method of the same In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body ... 01/17/08 - 20080012057 - Semiconductor device using fuse/anti-fuse system and method of manufacturing the same A first concave portion for the element isolation, a second concave portion for an aligning mark, and a third concave portion for an anti-fuse portion are formed simultaneously within a silicon substrate. After a silicon oxide film is formed on the entire surface, the silicon oxide film positioned within the ... 01/10/08 - 20080006865 - Thin film transistor array substrate structures and fabrication method thereof A thin film transistor array substrate structure. The array substrate structure includes a thin film transistor array substrate, an organic material layer formed thereon, and a plurality of black matrices and color filter patterns disposed on the organic material layer. The invention also provides a method of fabricating the thin ... 12/27/07 - 20070296009 - Semiconductor device including a capacitance It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer ... 12/20/07 - 20070290247 - Method of forming gate insulating film, semiconductor device and computer recording medium In the present invention, when a gate insulation film in a DRAM is formed, an oxide film constituting a base of the gate insulation film is plasma-nitrided. The plasma nitridation is performed with microwave plasma generated by using a plane antenna having a large number of through holes. Nitrogen concentration ... 12/13/07 - 20070284639 - Transistor and method for manufacturing the same A transistor including a semiconductor substrate defined with an active region and a device isolation region, a gate formed on the semiconductor substrate, an insulating spacers formed on respective side walls of the gate, and source/drain junctions formed in the semiconductor substrate at opposite sides of the gate, the source/drain ... 12/13/07 - 20070284638 - Conductive container structures having a dielectric cap Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures ... 11/08/07 - 20070257290 - Memory structure and memory device A memory structure, a memory device and a manufacturing method thereof are provided. First, a substrate is provided and a dielectric layer is formed over the substrate. Then, a pattern is formed in the dielectric layer. An amorphous silicon layer is formed in the pattern and over the dielectric layer. ... 10/25/07 - 20070246762 - Semiconductor device including a tcam having a storage element formed In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact ... 10/18/07 - 20070241381 - Methods for fabricating semiconductor devices Semiconductor devices and methods for fabricating a semiconductor devices are disclosed. A disclosed method comprises: forming a first gate electrode functioning as a flash memory; forming first spacers on sidewalls of the first gate electrode; forming a second gate electrode functioning as a normal gate electrode; forming a source/drain region ... 10/11/07 - 20070235784 - Three-terminal cascade switch for controlling static power consumption in integrated circuits A switching circuit configured for controlling static power consumption in integrated circuits includes a plurality of three-terminal, phase change material (PCM) switching devices connected between a voltage supply terminal and a corresponding sub-block of integrated circuit logic. Each of the PCM switching devices further includes a PCM disposed in contact ... 10/11/07 - 20070235783 - Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The bottom portions can ... 10/04/07 - 20070228440 - Structure and fabrication method for capacitors integratible with vertical replacement gate transistors A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second ... 10/04/07 - 20070228439 - Large-area nanoenabled macroelectronic substrates and uses therefor A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor ... 10/04/07 - 20070228438 - Technique to control tunneling currents in dram capacitors, cells, and devices Structures and methods are provided for the use with PMOS devices. Materials with large electron affinities or work functions are provided for structures such as gates. A memory cell is provided that utilizes materials with work functions larger than n-type doped polysilicon (4.1 eV) or aluminum metal (4.1 eV) for ... 10/04/07 - 20070228437 - Dram arrays, vertical transistor structures, and methods of forming transistor structures and dram arrays The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The substrate is etched to form a plurality of trenches and cross-trenches which define a plurality of pillars. After the etching, dopant is implanted within the trenches to ... 10/04/07 - 20070228436 - Arrangement of semiconductor memory devices and semiconductor memory module comprising an arrangement of semiconductor memory devices An arrangement of semiconductor memory devices includes a first semiconductor memory device and a second semiconductor memory device. The arrangement of semiconductor memory devices also has a flexible substrate. A first electrically conductive conductor track is arranged in the flexible substrate. At least one first contact of the flexible substrate ... 10/04/07 - 20070228435 - Semiconductor device and fabrication thereof A method for forming a semiconductor device is disclosed, in which a substrate comprising a recessed gate is provided, and a protrusion of the recessed gate protrudes a surface of the substrate. A spacer is formed on a sidewall of the protrusion of the recessed gate. A conductive structure is ... 10/04/07 - 20070228434 - Semiconductor memory device A semiconductor memory device including a capacitor array having an effective size smaller than a minimum feature size of lithography is disclosed. According to one aspect of the present invention, it is provided a semiconductor memory device comprising a transistor including a gate electrode formed on a gate insulator on ... 10/04/07 - 20070228433 - Dram with nanofin transistors One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a ... 09/20/07 - 20070215924 - Nonvolatile semiconductor memory device and method of manufacturing the same A memory cell in a nonvolatile semiconductor memory device includes a tunneling insulating film, a floating gate electrode made of a Si containing conductive material, an inter-electrode insulating film made of rare-earth oxide, rare-earth nitride or rare-earth oxynitride, a control gate electrode, and a metal silicide film formed between the ... 09/13/07 - 20070210364 - Mos capacitor and semiconductor device A capacitor capable of functioning as a capacitor even when an AC voltage is applied thereto is provided without increasing the manufacturing steps of a semiconductor device. A transistor is used as a MOS capacitor where a pair of impurity regions formed on opposite sides of a channel formation region ... 09/13/07 - 20070210363 - Vertical soi transistor memory cell and method of forming the same The present invention relates to a semiconductor device that contains at least one trench capacitor and at least one vertical transistor, and methods for forming such a semiconductor device. Specifically, the trench capacitor is located in a semiconductor substrate and comprises an outer electrode, an inner electrode, and a node ... 09/06/07 - 20070205450 - Semiconductor device and method of manufacturing the same A plurality of origin patterns (3) containing a metal catalyst are formed over a semiconductor substrate (1). Next, an insulating film (4) covering the origin patterns (3) is formed. Next, a trench allowing at the both ends thereof the side faces of the origin patterns (3) to expose is formed. ... 08/30/07 - 20070200157 - Semiconductor memory device and manufacturing method thereof This disclosure concerns a semiconductor memory device comprising a supporting substrate including semiconductor materials; an insulation film provided above the supporting substrate; a first diffusion layer provided on the insulation film; a second diffusion layer provided on the insulation film; a body region provided between the first diffusion layer and ... 08/30/07 - 20070200155 - Method of fabricating an integrated electronic circuit with programmable resistance cells Method of fabricating an integrated electronic circuit with programmable resistance cells, which comprises providing a substrate; forming an inert electrode; forming a solid electrolyte on the inert electrode; forming an interlayer on the solid electrolyte, the interlayer comprising an active electrode material and nitrogen; and forming an active electrode on ... 08/23/07 - 20070194362 - Semiconductor device and process for production thereof Disclosed herein is a semiconductor device with high reliability which has TFT of adequate structure arranged according to the circuit performance required. The semiconductor has the driving circuit and the pixel portion on the same substrate. It is characterized in that the storage capacitance is formed between the first electrode ... 08/16/07 - 20070187736 - Semiconductor memory device A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and ... 08/09/07 - 20070181924 - Integrated capacitor structure A semiconductor component includes an integrated capacitor structure embodied at least partly in an electrically conductive plane and which is patterned such that a multiplicity of strip elements are present. A first group of strip elements constitutes a first electrode of the capacitor structure and a second group of strip ... 07/26/07 - 20070170485 - Semiconductor memory device and method for fabricating the same A semiconductor memory device includes a plurality of memory cells. Each memory cell includes a capacitor which is composed of a first electrode, at least one particle made of ferroelectric or high dielectric constant material and selectively arranged on the first electrode, and a second electrode formed on the particle. ... 07/26/07 - 20070170483 - Capacitor of dynamic random access memory and method of manufacturing the capacitor A transistor formed on a semiconductor substrate has a gate electrode formed via a gate insulating film and first and second diffusion layers formed in the semiconductor substrate, the first and second diffusion layers being positioned at both sides of the gate electrode. A first electrode is connected to the ... 07/26/07 - 20070170482 - Semiconductor storage device and manufacturing method thereof A semiconductor storage device including a capacitor whose stored signal quantity is large with respect to its area share ratio, and a manufacturing method thereof are disclosed. According to one aspect of the present invention, it is provided a semiconductor storage device comprising a transistor formed on a semiconductor substrate, ... 07/19/07 - 20070164340 - Semiconductor memory device A semiconductor memory device excellent in data holding characteristics even when a cell area is reduced is disclosed. According to one aspect of the present invention, a semiconductor memory device comprises a transistor including a source, a drain and a channel region disposed in a semiconductor substrate, and including a ... 07/19/07 - 20070164339 - Semiconductor device and manufacturing method thereof A channel stop region is formed immediately under an STI, and thereafter, an ion implantation is performed with conditions in which an impurity is doped into an upper layer portion of an active region, and at the same time, the impurity is also doped into immediately under another STI, and ... 07/12/07 - 20070158722 - Vertical gain cell A vertical cell is realized. The cell includes a first vertical metal oxide semiconductor (MOS) transistor having a body between a drain region and a source region and a second vertical MOS transistor including at least a portion of the body of the first vertical MOS transistor. ... 07/12/07 - 20070158720 - Semiconductor device with cells each having a trench capacitor and a switching transistor thereon A semiconductor device includes a semiconductor substrate, at least one trench capacitor which is buried into the surface area of the semiconductor substrate, and a first insulation film which is formed on the trench capacitor. The semiconductor device further includes at least one switching transistor provided on the surface of ... 07/12/07 - 20070158719 - Dynamic random access memory structure and method for preparing the same A dynamic random access memory structure having a vertical floating body cell includes a semiconductor substrate having a plurality of cylindrical pillars, an upper conductive region positioned on a top portion of the cylindrical pillar, a body positioned below the upper conductive portion in the cylindrical pillar, a bottom conductive ... 07/12/07 - 20070158718 - Dynamic random access memory and method of fabricating the same A method of fabricating a dynamic random access memory is provided. A trench capacitor is formed in a substrate and an isolation structure is formed on the trench capacitor. A gate structure and a passing gate structure are formed on the substrate. The gate structure is on one side of ... 06/28/07 - 20070145450 - Dram cell design with folded digitline sense amplifier The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6F2 is disclosed which has a plurality of dual bit active areas, each of the active ... 06/21/07 - 20070138527 - Access transistor for memory device An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second source/drain regions and a channel region vertically stacked over the substrate. The access transistor is associated with at least one resistance variable memory element. ... 06/21/07 - 20070138526 - Pitch reduced patterns relative to photolithography features Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the ... 06/21/07 - 20070138525 - Mechanical memory device and method of manufacturing the same A memory device that performs writing and reading operations using a mechanical movement of a nanowire, and a method of manufacturing the memory device are provided. The memory device includes a source electrode, a drain electrode, and a gate electrode, each of which is formed on an insulating substrate. A ... 06/21/07 - 20070138524 - Semiconductor memory device and methods thereof A semiconductor memory device and methods thereof. The example semiconductor memory device may include a semiconductor substrate, a first source line and a second source line oriented in a first direction, the first and second source lines not in contact with each other, at least one bit line oriented in ... 06/21/07 - 20070138523 - Transistor, memory cell, memory cell array and method of forming a memory cell array One embodiment of the present invention relates to a transistor that is at least partially formed in a semiconductor substrate having a surface. In particular, the transistor includes a first source/drain region, a second source/drain region, a channel region connecting said first and second source/drain regions. Said channel region is ... 06/14/07 - 20070131996 - Non-volatile memory device and fabricating method thereof The present invention provides a non-volatile memory device and fabricating method thereof, by which a cell size can be lowered despite high degree of cell integration and by which the device fabrication is facilitated. The present invention includes at least two trench isolation layers arranged in a device isolation area ... 06/14/07 - 20070131995 - Reduced cell-to-cell shorting for memory arrays Bottom electrodes of memory cell capacitors are recessed to prevent electrical shorts between neighboring memory cells. A partially fabricated memory cell capacitor has a bottom electrode comprising titanium nitride (TiN) and hemispherical grained (HSG) silicon. The container housing the capacitor is filled with photoresist and then planarized. The TiN layer ... 05/31/07 - 20070120167 - Large-area nanoenabled macroelectronic substrates and uses therefor A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor ... 05/31/07 - 20070120166 - Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device includes a semiconductor substrate. Active regions are formed on the surface of the substrate, separated from one another by element separating regions and extend in a first direction. A first word line and a second word line extend in a second direction crossing the first ... 05/31/07 - 20070120165 - Semiconductor device with ferroelectric capacitor and fabrication method thereof A semiconductor device fabrication method includes the steps of forming a conductive plug in an insulating layer on a semiconductor substrate so as to be connected to an element on the substrate; forming a titanium aluminum nitride (TiAlN) oxygen barrier film over the conductive plug; forming a titanium (Ti) film ... 05/24/07 - 20070114586 - Electrical contact for high dielectric constant capacitors and method for fabricating the same An electrical contact includes a non-conductive spacer surrounding conductive plug material along the full height of the contact. The spacer inhibits oxide and other diffusion through the contact. In the illustrated embodiment, the contact includes metals or metal oxides which are resistant to oxidation, and additional conductive barrier layers. The ... 05/17/07 - 20070108491 - Semiconductor memory device having high electrical performance and mask and photolithography friendliness A semiconductor memory device includes a plurality of rows, each row comprising a plurality of active regions arranged at a pitch wherein the active regions in adjacent rows are shifted with respect to each other by one half of the pitch, wherein a distance between each active region in a ... 05/17/07 - 20070108490 - Film capacitors with improved dielectric properties A film capacitor including a first electrode is provided. The film capacitor also includes a first dielectric layer having a first dielectric constant disposed upon a first electrode and a second dielectric layer having a second dielectric constant disposed upon the first dielectric layer, wherein the second dielectric constant is ... 05/03/07 - 20070096182 - Transistor, meomory cell array and method of manufacturing a transistor A transistor, memory cell array and method of manufacturing a transistor are disclosed. In one embodiment, the invention refers to a transistor, which is formed at least partially in a semiconductor substrate, comprising a first and a second source/drain regions, a channel region connecting said first and second source/drain regions, ... 05/03/07 - 20070096181 - Flexible memory module A flexible memory module includes a substrate formed of a printed circuit board and electrically connectable to a insertion slot of a connector, a flexible board extension, which is fixedly provided at the rear side of the substrate and turned backwards and covered over the substrate to reduce surface space ... 04/26/07 - 20070090430 - Semiconductor memory device semiconductor memory device comprising: a semiconductor layer; a gate electrode formed on the semiconductor layer through a gate insulating film; a channel region provided beneath the gate electrode; source/drain diffusion regions having a conductivity type opposite to that of the channel region and provided on both sides of the channel ... 04/26/07 - 20070090429 - Capacitor structure A capacitor structure is provided. The capacitor structure is configured in a substrate. The capacitor structure includes a plurality of electrode sets, at least a first conductive plug and at least a second conductive plug. The electrode sets correspond with each other and are disposed in different layers of the ... 04/26/07 - 20070090428 - Integrated semiconductor structure for sram cells A semiconductor structure includes a semiconductor substrate having a first device area and a second device area. A gate layer is formed across the first device area and the second device area on the semiconductor substrate, wherein a first portion of the gate layer running across the first device area ... 04/19/07 - 20070085122 - Semiconductor memory device having metal-insulator transition film resistor A semiconductor memory device may have a lower leakage current and/or higher reliability, e.g., a longer retention time and/or a shorter refresh time. The device may include a switching device and a capacitor. A source of the switching device may be connected to a first end of a metal-insulator transition ... 04/12/07 - 20070080385 - Semiconductor device having vertical transistor and method of fabricating the same There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on ... 04/05/07 - 20070075347 - Phase change memory devices with reduced programming current A phase change memory device and a method of forming the same are provided. The phase change memory device includes a conducting electrode in a dielectric layer, a bottom electrode over the conducting electrode, a phase change layer over the bottom electrode, and a top electrode over the phase change ... 04/05/07 - 20070075346 - Light emitting diode and the package structure thereof A light emitting diode (LED) is disclosed. The LED includes a substrate, a patterned semiconductor layer, two contact pads, a dielectric layer and a fluorescence thin film. Wherein, the patterned semiconductor layer is disposed on the substrate and suitable for emitting a first light, while the contact pads are disposed ... 03/29/07 - 20070069266 - Memory device Conventionally, the layer of the insulator between a cathode and an anode is formed by a droplet discharge method, vapor deposition, or the like separately from an interlayer insulating film formed over a thin film transistor, which creates problems of increase in cost and the number of manufacturing steps. A ... 03/29/07 - 20070069265 - Recess transistor (tr) gate to obtain large self-aligned contact (sac) open margin A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the ... 03/22/07 - 20070063242 - High density semiconductor memory and method of making A memory cell, array and device include cross-shaped active areas and polysilicon gate areas disposed over arm portions of adjacent cross-shaped active areas. The polysilicon gate areas couple word lines with capacitors associated with each arm portion of the cross-shaped active areas. Buried digit lines are coupled to body portions ... 03/22/07 - 20070063241 - Semiconductor device and method for fabricating the same The semiconductor device comprises a capacitor formed over a semiconductor substrate 10 and including a lower electrode 32, a dielectric film 34 formed over the lower electrode and an upper electrode 36 formed over the dielectric film, a first insulation film 42 formed over the semiconductor substrate and the capacitor, ... 03/22/07 - 20070063240 - Integrated electronic circuit incorporating a capacitor An integrated electronic circuit includes electrical connections located in metallization layers superposed on top of a substrate. The circuit further incorporates a capacitor having two plates that are placed in two adjacent metallization layers. Each of the metallization layers containing a capacitor plate further contains electrical connections. The capacitor is ... 03/15/07 - 20070057301 - Method of manufacturing a transistor, a method of manufacturing a memory device and transistor A method of manufacturing a transistor is disclosed. The method includes forming a first and a second source/drain regions, a channel connecting the first and the second source/drain regions and a gate electrode for controlling the conductivity of the channel. The gate electrode is formed by defining a gate groove ... 03/08/07 - 20070051996 - Method of forming a mosfet with dual work function materials A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell ... 03/08/07 - 20070051995 - Mos transistor cell and semiconductor device A MOS transistor cell having a salicide structure has a plurality of gate wires each formed as a straight line with a constant width. Each of the gate wires includes a P-channel gate terminal and an N-channel gate terminal. The P-side ends and the N-side ends of the gate wires ... 03/08/07 - 20070051994 - Dual-gate dynamic random access memory device having vertical channel transistors and method of fabricating the same A dynamic random access memory (DRAM) device has dual-gate vertical channel transistors. The device is comprised of pillar-shaped active patterns including source regions contacting with a semiconductor substrate, drain regions formed over the drain regions, and channel regions formed between the source and drain regions. The active patterns are disposed ... 03/08/07 - 20070051993 - Method of forming thin film transistor and poly silicon layer of low-temperature poly silicon thin film transistor A method of forming a thin film transistor is provided. First, an amorphous silicon layer is formed on a substrate. Next, a first gate insulating layer is formed on the amorphous silicon layer. Then, an annealing process is performed so that the amorphous silicon layer is melted and re-crystallized to ... 03/01/07 - 20070045696 - Solid electrolytic capacitor element, manufacturing method of solid electrolytic capacitor element and solid electrolytic capacitor A solid electrolytic capacitor element includes a first oxide layer formed on an anode, a second oxide layer formed on the first oxide layer, and a cathode formed on the second oxide layer. The first oxide layer includes Nb2O5 and the second oxide layer includes NbOx (1≦x≦2). ... 03/01/07 - 20070045695 - Method for fabricating semiconductor device and semiconductor device A Ni film is deposited over the entire surface of a substrate including a silicon gate. Then, the silicon gate is partially removed by, for example, CMP, thereby leaving a Ni layer having a flat upper surface and a uniform thickness directly on the silicon gate. Subsequently, silicidation is performed, ... 03/01/07 - 20070045694 - Method of selecting a rram memory material and electrode material A method of determining a memory material and an associated electrode material for use in a RRAM device includes selecting a memory material having an inner orbital having less than a full quota of electrons and a narrow, outer conductive orbital; and selecting an associated electrode material for injecting a ... 03/01/07 - 20070045693 - Semiconductor constructions, and methods of forming capacitor devices The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some ... 02/22/07 - 20070040200 - Trench buried bit line memory devices and methods thereof A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit ... 02/22/07 - 20070040199 - Semiconductor device and method for manufacturing the same In a semiconductor device, a transistor in an N-type logic region NL is covered with a tensile stress applying film and a transistor in a P-type logic region PL is covered with a compressive stress applying film. Transistors in a P-type SRAM region PS and an N-type SRAM region NS ... 02/22/07 - 20070040198 - Semiconductor device and manufacturing method thereof, and thin film device A manufacturing method of a semiconductor device is disclosed. The manufacturing method includes the steps of forming a contact plug in an insulation film so as to be connected to an element on a semiconductor substrate, applying a PLA process to the insulation film in an NH3 atmosphere, forming a ... 02/22/07 - 20070040197 - Non-volatile memory, manufacturing method and operating method thereof A non-volatile memory including a memory unit, a first bit line and a second bit line is provided. The memory unit includes a first doped region, a second doped region, a first memory cell, a select gate structure, and a second memory cell. The first doped region and the second ... 02/15/07 - 20070034926 - Asymmetric field effect transistor A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region formed with the first dopant doping ... 02/15/07 - 20070034925 - Fin-field effect transistors (fin-fets) having protection layers Fin-Field Effect Transistors (Fin-FETs) are provided. A fin is provided on an integrated circuit substrate. The fin defines a trench on the integrated circuit substrate. A first insulation layer is provided in the trench such that a surface of the first insulation layer is recessed beneath a surface of the ... 02/15/07 - 20070034924 - Semiconductor device and method of manufacturing the same The semiconductor device 1 includes an insulating interlayer 10, interconnects 12a to 12c, an insulating interlayer 20, and a capacitor element 30. On the insulating interlayer 10 and the interconnects 12a to 12d, the insulating interlayer 20 is provided via a diffusion barrier 40. On the insulating interlayer 20, the ... 02/15/07 - 20070034923 - Devices with different electrical gate dielectric thicknesses but with substantially similar physical configurations An integrated circuit is disclosed having one or more devices having substantially similar physical gate electric thicknesses but different electrical gate electric thicknesses for accommodating various operation needs. One or more devices are manufactured with a same mask set using multiple doping processes to generate substantially similar physical gate dielectric ... 02/15/07 - 20070034922 - Integrated surround gate multifunctional memory device Vertical surround gate memory cells are formed around pillars on a substrate. Each memory cell is comprised of a gate stack formed around each pillar and a gate formed around each gate stack. The substrate can have multiple integrated memory types by varying the effective oxide thickness of the tunnel ... 02/15/07 - 20070034921 - Access transistor for memory device An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second source/drain regions and a channel region vertically stacked over the substrate. The access transistor is associated with at least one resistance variable memory element. ... 02/08/07 - 20070029596 - Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same A semiconductor device comprises a first transistor having a composite gate structure containing a lamination of a first polycrystalline silicon film, an interlayer insulating film, and a second polycrystalline silicon film; and a second transistor having a single gate structure containing a lamination of a third polycrystalline silicon film and ... 02/01/07 - 20070023810 - Capacitor, semiconductor device having the same, and method of manufacturing the semiconductor device A semiconductor device with a stack type capacitor having a lower electrode formed of an aluminum-doped metal, and a manufacturing method thereof are provided. The semiconductor device includes: a semiconductor substrate having a gate structure and an active region; an interlayer dielectric film formed on the active region; a lower ... 02/01/07 - 20070023809 - Memory cell comprising one mos transistor with an isolated body having an improved read sensitivity A memory cell with one MOS transistor formed in a floating body region isolated on its lower surface by a junction. A region of the same conductivity type as the floating body region but more heavily doped than said region is arranged under the drain region of the MOS transistor. ... 02/01/07 - 20070023808 - Semiconductor memory, the fabrication thereof and a method for operating the semiconductor memory A semiconductor memory having a multitude of memory cells (21-1), the semiconductor memory having a substrate (1), at least one wordline (5-1), a first (15-1) and a second line (15-2; 16-1), wherein each of the multitude of memory cells (21-1) comprises a first doping region (6) disposed in the substrate ... 01/25/07 - 20070018220 - Semiconductor device, gate electrode and method of fabricating the same Example embodiments of the present invention provide a semiconductor device, a gate electrode and method of manufacturing the same. Other example embodiments of the present invention provide a gate electrode with a refractory metal layer having decreased sheet resistance and increased reliability, a semiconductor device and a method of manufacturing ... 01/25/07 - 20070018219 - Unit cell structure, method of manufacturing the same, non-volatile semiconductor device having the unit cell structure and method of manufacturing the non-volatile semiconductor device A unit cell structure in a non-volatile semiconductor device includes a lower electrode. The variable resistor is formed on the lower electrode and includes a first insulation thin film, a third insulation thin film, and a second insulation thin film located between the first and third insulation thin films. A ... 01/25/07 - 20070018218 - Fin field effect transistor memory cell, fin field effect transistor memory cell arrangement and method for producing the fin field effect transistor memory cell The invention relates to a bridge field-effect transistor storage cell comprising first and second source/drain areas and a channel area arranged therebetween, which are formed in a semiconductor bridge. The inventive storage cell also comprises a charge-coupled layer that is disposed at least partially on the semiconductor bridge and a ... 01/25/07 - 20070018217 - Semiconductor device and manufacturing method of the same According to the present invention, a semiconductor device manufacturing method includes the steps of: forming a capacitor formation groove in a silicon (semiconductor) substrate; and forming a second insulating film by thermally oxidizing at least the upper surface of the silicon substrate and the bottom and the side surfaces of ... 01/25/07 - 20070018216 - Electronic device including discontinuous storage elements An electronic device can include discontinuous storage elements that lie within a trench. The electronic device can include a substrate including a trench that includes a wall and a bottom and extends from a primary surface of the substrate. The electronic device can also include discontinuous storage elements, wherein a ... 01/25/07 - 20070018215 - Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The bottom portions can ... 01/18/07 - 20070012981 - Semiconductor memory device including multi-layer gate structure A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent ... 01/18/07 - 20070012980 - Large-area nanoenabled macroelectronic substrates and uses therefor A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor ... 01/18/07 - 20070012979 - Nand flash memory device and method of fabricating the same A NAND type flash memory device includes a semiconductor substrate, word lines, first and second selection lines, tunnel insulation layers, and selection gate insulation layers. The semiconductor substrate includes a memory transistor region and a selection transistor region. The word lines are arranged in the memory transistor region of the ... 01/04/07 - 20070001206 - Capacitors having a capacitor dielectric layer comprising a metal oxide having multiple different metals bonded with oxygen The invention comprises capacitors having a capacitor dielectric layer comprising a metal oxide having multiple different metals bonded with oxygen. In one embodiment, a capacitor includes first and second conductive electrodes having a high k capacitor dielectric region positioned therebetween. The high k capacitor dielectric region includes a layer of ... 01/04/07 - 20070001205 - Semiconductor device, display device, and electronic appliance In case the size of the transistor is enlarged, power consumption of the transistor is increased. Thus, the present invention provides a display device capable of preventing a current from flowing to a display element in signal writing operation without varying potentials of power source lines for supplying a current ... 01/04/07 - 20070001204 - Capacitor with single crystal tantalum oxide layer and method for fabricating the same A capacitor and a method for fabricating the same are provided. The capacitor includes: a substrate; an inter-layer insulation layer formed over the substrate and including a contact hole; a storage node formed over the inter-layer insulation layer and filled into the contact hole; a tantalum oxide layer of single ... 01/04/07 - 20070001203 - Semiconductor device including a vertical decoupling capacitor A vertical or three-dimensional non-planar configuration for a decoupling capacitor is provided, which significantly reduces the required die area for capacitors of high charge carrier storage capacity. The non-planar configuration of the decoupling capacitors also provides enhanced pattern uniformity during the highly critical gate patterning process. ... 01/04/07 - 20070001202 - Structure having a dielectric layer sandwiched between two conductors for providing enhanced cracking resistance to the dielectric layer A structure having a dielectric layer sandwiched between two conductors for providing enhanced cracking resistance to the dielectric layer is disclosed, which comprises a bottom electrode layer, a dielectric layer and a top electrode layer. The structure of the invention is designed with a specific layout that prevents the dielectric ... 12/28/06 - 20060289918 - Low resistance peripheral local interconnect contacts with selective wet strip of titanium Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided. ... 12/28/06 - 20060289917 - Semiconductor device, rf-ic and manufacturing method of the same Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode, ... 12/28/06 - 20060289916 - Power trench mosfets having sige/si channel structure Devices, methods, and processes that improve immunity to transient voltages and reduce parasitic impedances. Immunity to unclamped inductive switching events is improved. For example, a trench-gated power MOSFET device having a SiGe source is provided, where the SiGe source reduces parasitic npn transistor gain by reducing hole current in the ... 12/28/06 - 20060289915 - Semiconductor device A semiconductor device comprises a semiconductor portion including first semiconductor layers of a first conduction type and second semiconductor layers of a second conduction type alternately arranged on the surface of a semiconductor substrate to form a striped shape. A main region is formed to arrange a main cell in ... 12/28/06 - 20060289914 - Semiconductor constructions, memory cells, dram arrays, electronic systems; methods of forming semiconductor constructions; and methods of forming dram arrays The invention includes a semiconductor construction including rows of contact plugs, and rows of parallel bottom plates. The plug pitch is approximately double the plate pitch. The invention includes a method of forming a semiconductor construction. A plurality of conductive layers is formed over the substrate, the plurality of layers ... 12/21/06 - 20060284227 - Capacitor device having low dependency of capacitance value change upon voltage Capacitors are formed on an insulating film covering the surface of a semiconductor substrate. Each capacitor is constituted of a lower electrode layer of doped silicon, a dielectric film of silicon oxide formed on the lower electrode and an upper electrode layer of polycide formed on the dielectric film. Capacitors ... 12/21/06 - 20060284226 - Semiconductor devices including a topmost metal layer with at least one opening and their methods of fabrication In one embodiment, a semiconductor device has a topmost or highest conductive layer with at least one opening. The semiconductor device includes a semiconductor substrate having a cell array region and an interlayer insulating layer covering the substrate having the cell array region. The topmost conductive layer is disposed on ... 12/21/06 - 20060284225 - Memory cell array and method of forming the same A memory cell array includes memory cells with storage capacitor and an access transistor. The access transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second ... 12/14/06 - 20060278912 - Selective polysilicon stud growth A memory cell having a bit line contact and a method of manufacturing the memory cell is provided The memory cell may be a 6F2 or smaller memory cell. The bit line contact may have a contact hole bounded by insulating side walls, the contact hole may have a selective, ... 12/14/06 - 20060278911 - Relaxed-pitch method of aligning active area to digit line According to one aspect of the invention, a memory device is disclosed. The memory device comprises a substantially linear active area comprising a source and at least two drains defining a first axis. The memory device further comprises at least two substantially parallel word lines, at least a portion of ... 12/14/06 - 20060278910 - Vertical transistor, memory cell, device, system and method of forming same A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate. A first source/drain region is formed in the substrate and a body region and a second source/drain region are formed within the pillar. A first ... 12/14/06 - 20060278909 - Mis transistor and cmos transistor A MIS transistor, formed on a semiconductor substrate, assumed to comprise a semiconductor substrate (702, 910) comprising a projecting part (704, 910B) with at least two different crystal planes on the surface on a principal plane, a gate insulator (708, 920B) for covering at least a part of each of ... 12/07/06 - 20060273368 - Semiconductor device having capacitor with upper electrode of conductive oxide and its manufacture method A ferroelectric capacitor is formed above a substrate and made of a lamination of a lower electrode, a capacitor ferroelectric film and an upper electrode stacked in this order. The upper electrode is made of conductive oxide and has such an oxygen concentration distribution as an oxygen concentration in a ... 11/30/06 - 20060267063 - Catheter grip A catheter grip adapted to couple with an introducer or sheath holds a catheter in position while in use in a patient's body. The grip has a hub defining a channel through which the catheter extends, a pair of grip members that work with each other to hold the catheter ... 11/30/06 - 20060267062 - Double sided container process used during the manufacture of a semiconductor device A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact pads and capacitor storage cell contact pads which contact a semiconductor wafer. A dielectric layer is provided over the wafer substrate assembly and etched to expose ... 11/30/06 - 20060267061 - Mosfet having channel in bulk semiconductor and source/drain on insulator, and method of fabrication A MOSFET device (100) in a mono-crystalline semiconductor material (101) of a first conductivity type, which comprises a source and a drain of the opposite conductivity type, each having regions of polycrystalline semiconductor (110, 120) and respective junctions (112a, 122a) in monocrystalline semiconductor. Localized buried insulator regions (113, 123) are ... 11/30/06 - 20060267060 - Semiconductor memory device and method for fabricating the same A semiconductor memory device comprises: a first interlayer insulating film formed on a semiconductor substrate; a capacitor formed above the first interlayer insulating film and composed of a lower electrode, a capacitor insulating film of a high dielectric film or a ferroelectric film, and an upper electrode; a second interlayer ... 11/30/06 - 20060267059 - Peripheral circuit architecture for array memory A wordline driver cell, coupled to at least one wordline, includes at least one diffusion region and at least one wordline driver semiconductor switching device formed in the at least one diffusion region. The at least one wordline driver semiconductor switching device has a channel width that is arranged perpendicular ... 11/23/06 - 20060261393 - Semiconductor constructions and transistors, and methods of forming semiconductor constructions and transistors The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate ... 11/23/06 - 20060261392 - Semiconductor device and method of manufacturing the same Disclosed herein are a semiconductor device and a method of manufacturing the same that increases the reliability of these devices as size design limitations decrease. Generally, a first insulating film, and wiring, including conductive film patterns and second insulating film patterns are formed on a substrate. Third insulating film patterns ... 11/23/06 - 20060261391 - Semiconductor device and manufacturing method of the same In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and ... 11/23/06 - 20060261390 - Dynamic random access memory integrated element A dynamic random access memory integrated element includes a transistor and a region for the storage of electrical charges. The surface area of an electrical junction between a source region of the transistor and the storage region is smaller than the surface area of an electrical junction between a drain ... 11/16/06 - 20060255387 - Integrated circuit having laterally dielectrically isolated active regions above an electrically contacted buried material, and method for producing the same An integrated circuit is disclosed that includes a first layer made of active semiconductor material and extending along a first side of a buried layer, and trench structures, which cut through the layer made of active semiconductor material and have dielectric wall regions, whereby the dielectric wall regions isolate electrically ... 11/16/06 - 20060255386 - Method for manufacturing a semiconductor device having a hard mask coupled to a discharge plug A method for manufacturing a semiconductor device includes the steps of forming a conductive hard mask coupled to the semiconductor substrate via discharge plugs on a thick insulating film, selectively etching the thick insulating film by using the conductive hard mask to form cylindrical holes in the thick insulating film. ... 11/16/06 - 20060255385 - Memory device of the one-time-programmable type, and programming method for same A memory cell includes a bipolar transistor buried in a first part of the substrate and a dielectric region formed from a dielectric material capable of being subject to irreversible breakdown in the presence of a breakdown voltage difference applied thereto. This dielectric region is disposed on top of the ... 11/16/06 - 20060255384 - Memory device and method of manufacturing the same A memory device includes an array of memory cells and a storage capacitor for storing information. Each memory cell includes an access transistor. The access transistor includes first and second source/drain regions, a channel disposed between the first and the second source/drain regions, and a gate electrode electrically insulated from ... 11/09/06 - 20060249772 - Memory circuitry The invention includes memory circuitry. In one implementation, memory circuitry includes a memory array comprising a plurality of memory cell capacitors. Individual of the capacitors include a storage node electrode, a capacitor dielectric region, and a cell electrode. The cell electrode is commonly shared among at least some of the ... 11/09/06 - 20060249771 - Non-volatile semiconductor memory and method of manufacturing the same A proposed non-volatile semiconductor memory and a method of manufacturing the same are directed to performing stable and highly reliable operations. First, grooves are formed in a p-type silicon semiconductor substrate, and impurity diffusion layers are formed on the bottom surfaces of the grooves. A gate insulating film is then ... 11/09/06 - 20060249770 - Single transistor floating-body dram devices having vertical channel transistor structures and methods of fabricating the same Single transistor floating-body DRAM devices have a vertical channel transistor structure. The DRAM devices include a substrate, and first and second floating bodies disposed on the substrate and isolated from each other. A source region and a drain region are disposed under and above each of the first and second ... 11/09/06 - 20060249769 - Semiconductor memory device and method for fabricating a semiconductor memory device A semiconductor memory device and method for fabricating a semiconductor memory device is disclosed. In one embodiment, the semiconductor memory device using at least one ferroelectric layer which has at least one electrically non-conductive polymer and ferroelectric nanoparticles distributed in the polymer. In another embodiment, the present invention provides a ... 11/02/06 - 20060244028 - Conductive niobium oxide gate mosfet MOSFET gate structures are provided comprising a niobium monoxide gate, overlying a gate dielectric. The niobium monoxide gate may have a low work function suitable for use as an NMOS gate. ... 11/02/06 - 20060244027 - Mis capacitor and method of formation An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a nitridization or anneal process. A dielectric layer of aluminum oxide ... 11/02/06 - 20060244026 - Semiconductor substrate cleaning Methods for removing titanium-containing layers from a substrate surface where those titanium-containing layers are formed by chemical vapor deposition (CVD) techniques. Titanium-containing layers, such as titanium or titanium nitride, formed by CVD are removed from a substrate surface using a sulfuric acid (H2SO4) solution. The H2SO4 solution permits selective and ... 11/02/06 - 20060244025 - Semiconductor memory device and method for manufacturing the same A semiconductor memory device includes a first word-line, a first non-inverted bit-line, a first inverted bit-line, a first global interconnection layer, a first memory capacitor having a first storage electrode, a first counter electrode, and a first oxide dielectric film, a second memory capacitor having a second storage electrode, a ... 11/02/06 - 20060244024 - Memory cell array and method of manufacturing the same A memory cell array includes a plurality of active areas in which a plurality of memory cells are formed. A memory cell includes a storage capacitor, a transistor at least partially formed in a semiconductor substrate with a substrate surface, the transistor including a first source/drain region. A second source/drain ... 10/26/06 - 20060237758 - Semiconductor device A semiconductor device includes a plurality of first active areas arranged in a first area including a first sub area, a second sub area located adjacent to the first sub area in a first direction, and a third sub area adjacent to the first sub area in a second direction ... 10/26/06 - 20060237757 - Semiconductor device and method for manufacturing the same A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a plurality of bit line insulating films formed on the bit line diffusion layers; a plurality of gate insulting films ... 10/26/06 - 20060237756 - Phase change memory devices and their methods of fabrication In an embodiment, a phase change memory device includes a semiconductor substrate of a first conductivity type and a first interlayer insulating layer disposed on the semiconductor substrate. A hole penetrates the first interlayer insulating layer. A first and a second semiconductor pattern are sequentially stacked in a lower region ... 10/19/06 - 20060231877 - Semiconductor device A semiconductor device comprises a semiconductor substrate having a surface of a plane orientation {100}, and a plurality of memory cells formed on the semiconductor substrate. The memory cells each include a capacitor formed in a trench extending from the surface into the semiconductor substrate, and a transistor. The transistor ... 10/12/06 - 20060226461 - Semiconductor device and semiconductor device manufacturing method A semiconductor technique is provided which can achieve both of lowered resistance in a logic formation region and reduced leakage current of the capacitor of a memory device. Source/drain regions (4) are formed in the upper surface of a semiconductor substrate (1) in a memory formation region and cobalt silicide ... 10/12/06 - 20060226460 - High density integrated read-only memory (rom) with reduced access time An integrated circuit memory of the read-only memory type includes at least one memory cell. Each memory cell includes a storage transistor realized in a semiconductor substrate and presenting a source connected to a reference potential, a gate connected to an electrically conductive word line, and a drain connected to ... 10/12/06 - 20060226459 - Layout structure in semiconductor memory device and layout method therefor A line layout structure and method in a semiconductor memory device having a hierarchical structure are provided. In a semiconductor memory device having a global word line and a local word line, and a global bit line and a local bit line, and individually disposing all of the global word ... 10/05/06 - 20060220087 - Method of forming a contact structure including a vertical barrier structure and two barrier layers This invention relates to contact structures for use in integrated circuits and methods of fabricating contact structures. In one embodiment, a contact structure includes a conductive layer, one or more barrier layers formed above the conductive layer, and a barrier structure encircling the polysilicon layer and the one or more ... 10/05/06 - 20060220086 - Imos transistor A vertical IMOS-type transistor including: a stack of a first semiconductor portion doped with dopant elements of a first type, of a second substantially undoped intrinsic semiconductor portion, and of a third semiconductor portion doped with dopant elements of a second type forming a PIN-type diode; and a conductive gate ... 10/05/06 - 20060220085 - Single transistor floating body dram cell having recess channel transistor structure and method of fabricating the same Single transistor floating body dynamic random access memory (DRAM) cells include a semiconductor substrate and a barrier layer on the semiconductor substrate and a recess channel transistor on the barrier layer. The recess channel transistor includes a source region of a first conductivity type, a drain region of the first ... 10/05/06 - 20060220084 - Magnetoresistive effect element and method for fabricating the same The magnetoresistive effect element comprises a first ferromagnetic layer 50, a nonmagnetic layer 52 formed on the first ferromagnetic layer 50, a second ferromagnetic layer 54 formed on the nonmagnetic layer 52, and a sidewall insulating film 64 formed on the side wall of the second ferromagnetic layer 54. The ... 09/28/06 - 20060214211 - Semiconductor device and method for manufacturing the same A semiconductor device includes a memory cell gate structure having a first gate insulating film, a first gate electrode, a second gate insulating film, and a second gate electrode, a select gate structure having a third gate insulating film and a third gate electrode including a first electrode portion, a ... 09/28/06 - 20060214210 - Semiconductor device A semiconductor device according to an aspect of the invention comprises a semiconductor substrate, a conductive plug which is connected to an active region of a transistor formed on the semiconductor substrate, a metal silicide film which covers a bottom surface portion and side surface portion of the conductive plug, ... 09/28/06 - 20060214209 - High density semiconductor memory and method of making A memory cell, array and device include cross-shaped active areas and polysilicon gate areas disposed over arm portions of adjacent cross-shaped active areas. The polysilicon gate areas couple word lines with capacitors associated with each arm portion of the cross-shaped active areas. Buried digit lines are coupled to body portions ... 09/14/06 - 20060202248 - Sram cell structure and manufacturing method thereof A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over ... 09/14/06 - 20060202247 - Sram cell structure and manufacturing method thereof A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over ... 09/14/06 - 20060202246 - Semiconductor device and manufacturing method thereof A semiconductor device includes: an channel layer formed on a semiconductor substrate; a drain electrode and a source electrode both formed on the channel layer apart from each other; a surface passivation film formed on the channel layer so as to cover the channel layer except for the drain electrode ... 09/14/06 - 20060202245 - Phase-change memory device and manufacturing process thereof A phase-change memory device, wherein memory cells form a memory array arranged in rows and columns. The memory cells are formed by a MOS selection device and a phase-change region connected to the selection device. The selection device is formed by first and second conductive regions which extend in a ... 09/07/06 - 20060197132 - Sram cell structure and manufacturing method thereof A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over ... 09/07/06 - 20060197131 - Dram device and method of manufacturing the same In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation ... 09/07/06 - 20060197130 - Phase change memory devices and fabrication methods thereof In a memory device, a transistor may be formed on a substrate, and a first electrode may be electrically connected thereto. A phase change material film may be vertically formed on the first electrode, and a second electrode may be formed on the phase change material film. ... 09/07/06 - 20060197129 - Buried and bulk channel finfet and method of making the same One embodiment of a fin-field effect transistor includes a material stack including a non-inverting su surface channel, a fin of semiconductor material positioned on the material stack, the fin including first and second opposing side surfaces, and a gate electrode positioned on the first and second opposing side surfaces of ... 08/31/06 - 20060192237 - Magnetic elements with ballistic magnetoresistance utilizing spin-transfer and an mram device using such magnetic elements A method and system for providing a magnetic element is disclosed. The method and system include providing a pinned layer, a magnetic current confined layer, and a free layer. The pinned layer is ferromagnetic and has a first pinned layer magnetization. The magnetic current confined layer has at least one ... 08/31/06 - 20060192236 - Semiconductor device The present invention provides a semiconductor device comprising: a semiconductor substrate having a DRAM portion and a Logic portion; a first transistor in said DRAM portion; a second transistor in said Logic portion; a first insulating layer covering said DRAM portion and said Logic portion; a first contact plug formed ... 08/24/06 - 20060186448 - Semiconductor device memory cell A circuit provides an inhibition to the short circuit between the bit line and the capacitance contact, without employing a self alignment contact (SAC) process. A hard mask is formed on the bit line upper surface and a side wall formed on the side surface of the bit line by ... 08/24/06 - 20060186447 - Semiconductor memory and method for fabricating the same A semiconductor memory includes: a semiconductor substrate having a protrusion; a gate insulating film formed on an upper surface of the protrusion; a gate electrode formed on the gate insulating film; diffusion regions formed in portions of the substrate on both sides of the protrusion, the diffusion regions being disposed ... 08/24/06 - 20060186446 - 3-dimensional flash memory device and method of fabricating the same In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on ... 08/17/06 - 20060180841 - Edram-type semiconductor device including logic circuit section featuring large capacitance capacitor, and capacitor dram section featuring small capacitance capacitor In an eDRAM-type semiconductor device, a dynamic random access memory (DRAM) section and a logic circuit section are formed on a semiconductor substrate, and an insulating layer is formed on the semiconductor substrate. A first capacitor is formed in the insulating layer at the DRAM section, the first capacitor defining ... 08/17/06 - 20060180840 - Switched capacitor circuit and semiconductor integrated circuit thereof A rectangular parallelepiped projecting portion (21) having a height of HB and a width of WB is formed on a silicon substrate, and a gate oxide film is formed on a part of the top surface and the side surface of the projecting portion (21), thereby generating a MOS transistor. ... 08/10/06 - 20060175649 - Sram devices, and electronic systems comprising sram devices The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region within the crystalline layer is within a single crystal of the crystalline layer, and in particular aspects an entirety of the active ... 08/10/06 - 20060175648 - Memory device and manufacturing method thereof As for a memory element implemented in a semiconductor device typified by an RFID, it is an object of the present invention to reduce manufacturing steps and to provide a memory element and a memory circuit having the element with reduced cost. It is a feature of the present invention ... 08/10/06 - 20060175647 - Semiconductor product having a semiconductor substrate and a test structure and method A semiconductor product having a test structure, in which a contact connection short-circuits that source/drain region of a transistor which is connected to an inner capacitor electrode of a trench capacitor by a dopant diffusion region with an interconnect is disclosed. Methods are disclosed for making an electrical measurement, to ... 08/10/06 - 20060175646 - Memory element using active layer of blended materials The present memory device has first and second electrodes, a passive layer between the first and second electrodes and on and in contact with the first electrode, and an active layer between the first and second electrodes and on and in contact with the passive layer and second electrode, for ... 08/03/06 - 20060170023 - Semiconductor integrated circuit device To provide a semiconductor integrated circuit device capable of increasing a capacitor capacitance. A semiconductor integrated circuit device according to an embodiment of the present invention includes: a circuit element formed on a semiconductor substrate; and capacitors formed on the semiconductor substrate and including: a lower capacitance electrode formed of ... 08/03/06 - 20060170022 - Silicon molecular hybrid storage cell and whereby n is an integer in the range from 1-4. ... 07/27/06 - 20060163634 - Semiconductor storage device A semiconductor storage device comprises a semiconductor substrate; an insulating layer formed on the semiconductor substrate; a first semiconductor layer formed on the insulating layer and insulated from the semiconductor substrate; memory cells each having a source region of a first conduction type and a drain region of the first ... 07/27/06 - 20060163633 - Dielectric relaxation memory A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as ... 07/27/06 - 20060163632 - Dielectric relaxation memory A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as ... 07/27/06 - 20060163631 - Vertical mosfet with dual work function materials A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell ... 07/20/06 - 20060157767 - Dynamic random assess memory circuitry and integrated circuitry A method of forming a conductive contact to a conductive structure includes forming a conductive structure received within and projecting outwardly from a first insulative material. A second different insulative material is deposited. The second insulative material is anisotropically etched effective to form a sidewall etch stop for the conductive ... 07/20/06 - 20060157766 - Metal-insulator-metal capacitor and method of fabricating the same In a metal-insulator-metal (MIM) capacitor and a method of fabricating the MIM capacitor, a metal-insulator-metal (MIM) capacitor comprises: a lower electrode pattern which is formed on a substrate and includes a conductive layer having a portion as a lower interconnect; a dielectric layer on the lower electrode pattern; a first ... 07/13/06 - 20060151820 - Large-area nanoenabled macroelectronic substrates and uses therefor A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor ... 07/06/06 - 20060145227 - Method for producing semiconductor memory devices and integrated memory device The invention provides an integration scheme for a memory cell array, especially a charge-trapping memory cell array, comprising an architecture of local interconnects, which enables to avoid nitride insulations of wordline stacks and to produce CMOS devices of different structures and dimensions in standard technology along with the tinier memory ... 06/29/06 - 20060138511 - Methods of manufacturing a capacitor including a cavity containing a buried layer Capacitors include an integrated circuit (semiconductor) substrate and an interlayer dielectric disposed on the integrated circuit substrate and including a metal plug therein. A lower electrode is disposed on the interlayer dielectric and contacting the metal plug. The lower electrode includes a cavity therein and a buried layer in the ... 06/29/06 - 20060138510 - Method for forming a stroage cell capacitor compatible with high dielectric constant materials An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed between a conductive plug and an oxidation resistant layer. An insulative layer protects sidewalls of the barrier layer during deposition and anneal of a ... 06/29/06 - 20060138509 - Magnetic random access memory with lower switching field through indirect exchange coupling A magnetic random access memory with lower switching field through indirect exchange coupling. The memory includes a first antiferromagnetic layer, a pinned layer formed on the first antiferromagnetic layer, a tunnel barrier layer formed on the pinned layer, a ferromagnetic free layer formed on the tunnel barrier layer, a metal ... 06/22/06 - 20060131630 - Method for forming storage node of capacitor in semiconductor device A method for forming a capacitor in a semiconductor device comprises forming an inter-layer layer on a semi-finished substrate; etching the inter-layer insulation layer to form a plurality of first contact holes; forming a first insulation layer on sidewalls of the first contact holes; forming a plurality of storage-node contact ... 06/15/06 - 20060124979 - Dram memory cell and method of manufacturing the same A DRAM memory cell includes a semiconductor substrate, an interlayer dielectric having storage node contact plugs that is formed on the semiconductor substrate, and storage node electrodes that are formed on the interlayer dielectric to contact the storage node contact plugs. The storage node contact plugs are formed such that ... 06/08/06 - 20060118849 - Semiconductor memory device including an soi A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain ... 06/08/06 - 20060118848 - Microelectronic programmable device and methods of forming and programming the same A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally include an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying a bias across the electrodes, and thus information may be stored using the ... 06/08/06 - 20060118847 - Semiconductor device and fabricating method thereof An upper electrode layer is processed into plural electrode shapes with lithography and subsequent dry etching to pattern plural upper electrodes, followed by conducting an RTA treatment at a treatment temperature of a value in a range from 400° C. to 1000° C. and at an oxygen flow volume of ... 06/08/06 - 20060118846 - Annular gate and technique for fabricating an annular gate A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around ... 06/01/06 - 20060113575 - Storage electrode of a capacitor and a method of forming the same In an embodiment, a storage electrode of a capacitor in a semiconductor device is resistant to inadvertent etching during its manufacturing processes. A method of forming the storage electrode of the capacitor is described. The storage electrode of the capacitor may include a first metal layer electrically connected with a ... 05/11/06 - 20060097301 - High density memory devices having improved channel widths and cell size A memory device having decreased cell size and having transistors with increased channel widths. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a conductive layer to form a channel through the pillars. The current path through the channel is ... 05/11/06 - 20060097300 - Semiconductor device and method of manufacturing the same A semiconductor device includes a semiconductor substrate, at least two gate electrode sections formed adjacent to each other on the surface of the semiconductor substrate, a first diffusion region formed in the surface area of the semiconductor substrate, except in the gate electrode sections, a substrate contact layer formed between ... 05/04/06 - 20060091440 - Memory device having molecular adsorption layer Provided is a memory device comprising a molecular adsorption layer. The memory device includes: a substrate; a source electrode and a drain electrode formed on the substrate and separated from each other; a carbon nanotube (CNT) layer electrically connected to the source electrode and the drain electrode; a memory cell ... 05/04/06 - 20060091439 - System and method for protecting semiconductor devices A semiconductor memory device includes a group of word lines and a structure that is configured to dissipate current from the group of word lines during fabrication of the semiconductor memory device. ... 04/13/06 - 20060076599 - Semiconductor memory devices including offset active regions A semiconductor memory device may include a substrate having a plurality of active regions and a field isolation layer on the substrate surrounding the active regions of the substrate. Each of the plurality of active regions may have a length in a direction of a first axis and a width ... 04/13/06 - 20060076598 - Semiconductor device and method of fabrication A semiconductor memory device employs a SONOS type memory architecture and includes a bit line diffusion layer in a shallow trench groove in which a conductive film is buried. This makes it possible to decrease the resistivity of the bit line diffusion layer without enlarging the area on the main ... 04/13/06 - 20060076597 - Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and ... 04/13/06 - 20060076596 - Semiconductor device A capacity element with a simple configuration exhibits excellent production reliability. A semiconductor device 100 includes a capacity element consisting of a lower electrode 102, an SiCN film 107 and an upper electrode 113. In an insulating film 101 on a semiconductor substrate is formed a groove, in which the ... 04/13/06 - 20060076595 - Dynamic random access memory cell and fabricating method thereof A method of fabricating a dynamic random access memory cell is provided. A substrate having a patterned mask layer thereon and a deep trench therein is provided. The patterned mask layer exposes the deep trench. A deep trench capacitor is formed inside the deep trench. Thereafter, a trench is formed ... 04/13/06 - 20060076594 - Semiconductor memory device The present invention provides a semiconductor memory device which comprises an interlayer insulating film formed on a semiconductor substrate, a contact plug formed in the interlayer insulating film and having one end electrically connected to the semiconductor substrate, a ferroelectric capacitor formed on the interlayer insulating film and comprising a ... 04/06/06 - 20060071258 - Semiconductor device Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a dielectric film provided on the bottom electrode, and a top electrode provided on the dielectric film, a mask film provided on the top electrode and used as a ... 03/30/06 - 20060065918 - Semiconductor device and method of fabricating the same A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first ... 03/23/06 - 20060060903 - Semiconductor device including a tcam having a storage element formed with a dram In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact ... 03/16/06 - 20060054957 - Nonvolatile semiconductor memory and manufacturing method for the same The memory cell matrix encompasses (a) a plurality device isolation films running along column direction, (b) first conductive layers arranged along row and column-directions, adjacent groups of the first conductive layers are isolated from each other by the device isolation film disposed between the adjacent groups, (c) lower inter-electrode dielectrics ... 03/16/06 - 20060054956 - Technique to control tunneling currents in dram capacitors, cells, and devices Structures and methods are provided for the use with PMOS devices. Materials with large electron affinities or work functions are provided for structures such as gates. A memory cell is provided that utilizes materials with work functions larger than n-type doped polysilicon (4.1 eV) or aluminum metal (4.1 eV) for ... 03/16/06 - 20060054955 - Dram cell having mos capacitor A DRAM cell having a MOS capacitor and a method for manufacturing the same are disclosed. The DRAM cell includes: an active region of a semiconductor substrate; a MOS capacitor consisting of a plate node electrode which is a part of the active region, a storage node electrode having a ... 03/16/06 - 20060054954 - Lateral mos device with minimization of parasitic elements A lateral MOS device is formed in a body having a surface and is formed by a semiconductor layer of a first conductivity type; a drain region of a second conductivity type, formed in the semiconductor layer and facing the surface; a source region of the second conductivity type, formed ... 03/16/06 - 20060054953 - Memory devices having a resistance pattern and methods of forming the same Memory devices include a semiconductor substrate and a device isolation layer in the substrate and defining a cell region and a resistance region. A resistance pattern is disposed on the device isolation layer in the resistance region. An interlayer insulating layer is on the resistance pattern and a resistance contact ... 03/16/06 - 20060054952 - One-time programmable memory device A one-time programmable, dual-bit memory device comprises one MOS storage transistor having a semiconductor substrate, first and second active regions formed under the surface of the substrate being separated by a part of the substrate forming a channel region, a gate formed on the surface of the said substrate in ... 03/09/06 - 20060049445 - Dram having at least three layered impurity regions between channel holes and method of fabricating same Disclosed is a dynamic random access memory (DRAM) comprising a transistor having channel holes formed in the channel region thereof and cell gate structures formed in the channel holes. At least three layered impurity regions are formed in a semiconductor substrate between the channel holes and the at least three ... 03/09/06 - 20060049444 - Semiconductor device and method of fabricating the same According to the present invention, there is provided a semiconductor device comprising: a plurality of transistors each having a semiconductor substrate, a first-conductivity-type semiconductor layer formed on said semiconductor substrate via a first insulating film, and having a single-crystal structure, a second-conductivity-type source region and second-conductivity-type drain region formed in ... 03/02/06 - 20060043449 - Semiconductor constructions and transistors, and methods of forming semiconductor constructions and transistors The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate ... 03/02/06 - 20060043448 - Dielectric relaxation memory A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as ... 02/23/06 - 20060038216 - Formation of capacitor having a fin structure Device designs and methods are described for incorporating capacitors commonly used in planar CMOS technology into a FinFET based technology. A capacitor includes at least one single-crystal Fin structure having a top surface and a first side surface opposite a second side surface. Adjacent the top surface of the at ... 02/16/06 - 20060033139 - Semiconductor device and method of manufacturing the same The present invention provides a semiconductor device comprising a capacitive element with a very uniform capacitive value as well as a method of manufacturing the semiconductor device. In a capacitive element formation region 20 of a semiconductor device 1, an N-type well 22 as a conductive layer is formed in ... 02/16/06 - 20060033138 - Method for manufacturing semiconductor device, and semiconductor device A manufacturing method for a semiconductor device that has a first region for memory elements and a second region for elements other than memory elements on a substrate, includes forming a first interlayer dielectric film on the substrate. A first opening section, which is made to reach the substrate, is ... 02/16/06 - 20060033137 - Methods of forming capacitors for semiconductor memory devices and resulting semiconductor memory devices Methods of forming capacitors include forming a first mold layer and a second mold layer on a substrate, forming storage electrodes through the mold layers, the storage electrodes arranged in rows extending in a first direction and spaced apart from adjacent storage electrodes along the first direction by a first ... 02/16/06 - 20060033136 - Mram over sloped pillar An apparatus including a pillar located over a substrate and having at least one sloped surface oriented at an acute angle relative to the substrate. The apparatus also includes an MRAM stack substantially conforming to the sloped surface, the MRAM stack thereby also oriented at the acute angle relative to ... 02/09/06 - 20060027850 - Polymer device with a nanocomposite barrier layer According to one aspect of the invention, a polymer device and a method of constructing a polymer device are provided. The polymer device includes a first conductor, a second conductor, and a polymeric body between the first and second conductors. The polymeric body includes a polymer material and a phyllosilicate ... 02/02/06 - 20060022247 - Transparent amorphous carbon structure in semiconductor devices A transparent amorphous carbon layer is formed. The transparent amorphous carbon layer has a low absorption coefficient such that the amorphous carbon is transparent in visible light. The transparent amorphous carbon layer may be used in semiconductor devices for different purposes. The transparent amorphous carbon layer may be included in ... 02/02/06 - 20060022246 - Capacitor element and semiconductor device An object of the present invention is that the capacitance of MOS capacitors is changed without varying the kind of an impurity (a donor or an acceptor) in a channel formation region, and an n-type MOS capacitor and a p-type MOS capacitor are formed over a same substrate. By changing ... 02/02/06 - 20060022245 - Analog capacitor and method of manufacturing the same An analog capacitor capable of reducing the influence of an applied voltage on a capacitance and a method of manufacturing the analog capacitor are provided. The analog capacitor includes a lower electrode which is formed on a substrate, a multi-layered dielectric layer which includes at least one oxide layer and ... 02/02/06 - 20060022244 - High density non-volatile memory devices The present invention provides methods to arrange non-volatile memory transistor array by rotating the word line and bit line directions 90 degrees relative to that of prior art NOR FLASH devices. These methods effectively reduce the areas of non-volatile memory devices. Additional changes in control mechanism are required to support ... 02/02/06 - 20060022243 - Semiconductor memory device and method for fabricating the same A semiconductor memory device has a memory region which is formed on a semiconductor substrate and in which a plurality of memory cells each including a memory transistor are arranged as a matrix using a plurality of impurity diffusion layers (bit lines) and a plurality of gate electrodes (word lines) ... 02/02/06 - 20060022242 - Semiconductor device and method for fabricating the same The semiconductor device comprises a semiconductor substrate 10 with a trench 16a and a trench 16b formed in; a device isolation film 32a buried in the trench 16a and including a liner film including a silicon nitride film 20 and an insulating film 28 of a silicon oxide-based insulating material; ... 02/02/06 - 20060022241 - Semiconductor memory device having capacitor using dielectric film, and method of fabricating the same A transistor is formed in a surface region of a semiconductor substrate. A capacitor is formed above the transistor, and has a first electrode, a second electrode, and a dielectric film formed between the first and second electrodes. A first contact is formed on a side surface portion of the ... 02/02/06 - 20060022240 - Single transistor dram cell with reduced current leakage and method of manufacture A single transistor planar DRAM memory cell with improved charge retention and reduced current leakage and a method for forming the same, the method including providing a semiconductor substrate; forming a gate dielectric on the semiconductor substrate; forming a pass transistor structure adjacent a storage capacitor structure on the gate ... 02/02/06 - 20060022239 - Memory devices, transistors, memory cells, and methods of making same A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel ... 01/26/06 - 20060017086 - Semiconductor device and method for manufacturing the same There is provided a semiconductor device having a ferroelectric capacitor formed on a semiconductor substrate covered with an insulator film, wherein the ferroelectric capacitor comprises: a bottom electrode formed on the insulator film; a ferroelectric film formed on the bottom electrode; and a top electrode formed on the ferroelectric film. ... 01/26/06 - 20060017085 - Nand flash memory with densely packed memory gates and fabrication process NAND flash memory cell array and fabrication process in which cells having memory gates and charge storage layers are densely packed, with the memory gates in adjacent cells either overlapping or self-aligned with each other. The memory cells are arranged in rows between bit line diffusions and a common source ... 01/26/06 - 20060017084 - Integrated semiconductor metal-insulator-semiconductor capacitor An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and ... 01/19/06 - 20060011960 - Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of floating offset voltage A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and ... 01/12/06 - 20060006443 - Electrically programmable memory element with reduced area of contact A programmable resistance memory element having a conductive layer as an electrode. The conductive layer and memory material may have a small area of contact. In one embodiment, the conductive layer may be cup-shaped. In one embodiment, the memory element may include a chalcogenide material. ... 01/12/06 - 20060006442 - Process for making a silicon-on-insulator ledge and structures achieved thereby A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region ... 01/12/06 - 20060006441 - Semiconductor device including a trench-type metal-insulator-metal (mim) capacitor and method of fabricating the same In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a bottom electrode and a first interconnection layer on a semiconductor substrate, an upper surface of the bottom electrode and an upper surface of the first interconnection layer being level, an interlayer insulating layer having ... 01/12/06 - 20060006440 - Devices with different electrical gate dielectric thicknesses but with substantially similar physical configurations An integrated circuit is disclosed having one or more devices having substantially similar physical gate electric thicknesses but different electrical gate electric thicknesses for accommodating various operation needs. One or more devices are manufactured with a same mask set using multiple doping processes to generate substantially similar physical gate dielectric ... 01/05/06 - 20060001066 - Semiconductor constructions The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass comprises silicon oxide. A sacrificial layer is formed over the first mass. While the sacrificial layer is ... 01/05/06 - 20060001065 - Alignment key structures in semiconductor devices including protected electrode structures and methods of fabricating the same An integrated circuit device includes a storage cell including an upper electrode and a lower electrode on a substrate, and a conductive hard mask pattern directly on the upper electrode of the storage cell opposite the lower electrode. The upper electrode is formed of a metal softer than the conductive ... 12/29/05 - 20050285174 - Stacked semiconductor memory device The stacked semiconductor memory device of the present invention has the object of reducing the cost of developing a wide variety of memory devices and includes: a memory cell array chip that is equipped with memory cell arrays, an interface chip that is stacked with the memory cell array chip ... 12/29/05 - 20050285173 - Semiconductor device and method for fabricating the same The semiconductor device comprises a first insulation film 26 formed over a semiconductor substrate 10, first conductor plug 32 buried in a first contact hole 28a formed down to a source/drain diffused layer 22, a capacitor 44 formed over the first insulation film 26, a first hydrogen diffusion preventing film ... 12/29/05 - 20050285172 - Methods of forming vias in multilayer substrates Exemplary embodiments of the present invention illustrate methods to electrically connect multiple layers of a substrate. A first and second layer each has at least one electrical trace on a surface thereof. The substrate includes an interposer structure attached to the second layer and separating the first and second layers ... 12/22/05 - 20050280062 - Semiconductor device and method of manufacturing the same A semiconductor device includes a semiconductor substrate having a first conductivity type. A pair of source/drain areas having a second conductivity type is formed on a surface of the semiconductor substrate. A gate insulating film is provided on a channel area between the source/drain areas. A gate electrode having the ... 12/22/05 - 20050280061 - Vertical memory device structures Vertically oriented semiconductor memory cells are added to a separately fabricated substrate that includes electrical devices and/or interconnect. The plurality of vertically oriented semiconductor memory cells are physically separated from each other, and are not disposed within the same semiconductor body. The plurality of vertically oriented semiconductor memory cells can ... 12/22/05 - 20050280060 - Concentric or nested container capacitor structure for integrated cicuits Disclosed are embodiments for a container capacitor structure in which at least two container capacitors, e.g., an inner and outer container capacitor, are made concentric and nested with respect to one another. The nested capacitors are formed in one embodiment by defining a hole in a dielectric layer for the ... 12/15/05 - 20050275004 - Semiconductor integrated circuit, booster circuitry, and non-volatile semiconductor memory device In a capacitor-containing semiconductor integrated circuit, a portion in which a plurality of capacitors are serially connected together is arranged so that at least part of the capacitors is formed as a well capacitor. ... 12/15/05 - 20050275003 - Crosspoint structure semiconductor memory device, and manufacturing method thereof A crosspoint structure semiconductor memory device includes a plurality of upper electrode interconnectings extending in the same direction and a plurality of lower electrode interconnectings extending in a direction orthogonal to the extension direction of the upper electrode interconnectings. A storage material member that stores data is formed between the ... 12/15/05 - 20050275002 - Vertical split gate memory cell and manufacturing method thereof A vertical split gate memory formed in a trench of a semiconductor substrate comprises a first doping region, a second doping region, a conductive line, a conductive spacer and a conductive plug, wherein the conductive line, conductive spacer and conductive plug serve as a select gate, a floating gate and ... 12/15/05 - 20050275001 - Integrated circuit and method of manufacturing same The integrated circuit (1) according to the invention comprises a set of cells (10), each of the cells 11, 13, 15, 19) comprises an electrical device (20) with a device parameter whose parameter value is a function of random parametric variations. The set of cells (10) comprises a first subset ... 12/08/05 - 20050269616 - Nano-porous metal oxide semiconductor spectrally sensitized with metal oxide chalcogenide nano-particles A nano-porous metal oxide semiconductor with a band-gap of greater than 2.9 eV in-situ spectrally sensitized on its internal and external surface with metal chalcogenide nano-particles with a band-gap of less than 2.9 eV containing at least one metal chalcogenide, wherein the nano-porous metal oxide further contains a phosphoric acid ... 12/08/05 - 20050269615 - Dram devices having an increased density layout DRAM devices include a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction and intersecting the word lines. A plurality of active regions is provided that are electrically coupled to the word lines and the bit lines. Each of ... 12/08/05 - 20050269614 - Non-junction-leakage 1t-ram cell Systems and methods for providing a one-transistor random access memory cell include a substrate, a well of a first conductivity type formed in the substrate and coupled to receive a first voltage, a first gate formed on the substrate and coupled to a word line, a doped region of a ... 12/01/05 - 20050263812 - Semiconductor memory device A semiconductor memory device having a transistor formed on a semiconductor substrate and a capacitor formed on the upper layer of the transistor and electrically connected to the transistor, includes: a cell contact which is formed on a first interlayer insulation film covering the transistor and is electrically connected to ... 12/01/05 - 20050263811 - Semiconductor device There is provided a large capacity memory such as a DRAM and an SDRAM n which bonding pads PS and PD are not located at the center, but are displaced from the center between memeory array regions UL and UR, disposed on the upper side of a four-bank structure of ... 12/01/05 - 20050263810 - Inspection substrate for display device In order to make it possible to easily detect an electrical defect by using an array tester, the present inspection substrate includes: plural scan lines and plural signal lines; plural storage capacitor lines arranged in parallel to the scan lines; storage capacitor elements, each of which uses a part of ... 11/24/05 - 20050258465 - Semiconductor memory device including multi-layer gate structure A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent ... 11/24/05 - 20050258464 - Field effect power transistor A power transistor is disclosed. In one embodiment, the power transistor has a cell array including a semiconductor body having a plurality of transistor cells with gate electrodes and with body and source electrode regions and at least one temperature sensing device integrated in the semiconductor body. The temperature sensing ... 11/24/05 - 20050258463 - Non-volatile semiconductor memory device and process of manufacturing the same In device isolation trenches, a first device-isolation insulator film is formed to have recesses thereon and a second device-isolation insulator film is formed in the recesses. The uppermost portions at both ends of the first device-isolation insulator film are located higher than the uppermost portions at both ends of the ... 11/03/05 - 20050242384 - Mram and method of manufacturing the same A magnetic memory device comprising, a magneto-resistance effect element that is provided at an intersection between a first write line and a second write line. And the magneto-resistance effect element having, an easy axis that extends in a direction of extension of the first write line, and a first conductive ... 10/27/05 - 20050236657 - Method of stress-testing an isolation gate in a dynamic random access memory The present invention includes a DRAM array. The DRAM array includes a first memory cell, a second memory cell and an isolation gate formed between the first and second memory cells. The isolation gate is configured to provide electrical isolation between the first and second memory cells. The DRAM also ... 10/27/05 - 20050236656 - Methods of forming memory arrays; and methods of forming contacts to bitlines The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact locations. An insulative material can be formed over the ... 10/20/05 - 20050230733 - Semiconductor device having landing pad and fabrication method thereof A semiconductor device can be provided comprising a semiconductor substrate having an upper surface. A plurality of adjacent line patterns are formed on the upper surface of the semiconductor substrate. Each line pattern includes a line having a capping layer pattern stacked thereon. A material layer covers the upper surface ... 10/20/05 - 20050230732 - Semiconductor memory device having capacitor and method of forming the same A semiconductor memory device having a capacitor is disclosed. The capacitor includes a bottom capacitor surface formed of a silicon-germanium crystalline layer or a dual layer in which a silicon-germanium crystalline layer covers a silicon crystalline layer. The bottom capacitor surface is uneven and is conventionally formed by an epitaxial ... 10/20/05 - 20050230731 - Metal thin film and method of manufacturing the same, dielectric capacitor and method of manufacturing the same, and semiconductor device A metal thin film provided on a substrate and having a metal with a face-centered cubic crystal structure, wherein the metal thin film is preferentially oriented in a (111) plane, and a (100) plane which is not parallel to a surface of the substrate is present on a surface of ... 10/20/05 - 20050230730 - Semiconductor integrated circuit device and frequency modulation device An N-type well region is formed in a P-type semiconductor substrate. In the N-type well region, a P-type well region is formed. The P-type well region is used as a back gate of a transistor. The back gate of the transistor is separated from other elements by the N-type well ... 10/20/05 - 20050230729 - Capacitor having metal electrode and method of fabricating the same In a method of fabricating a capacitor, an interlayer insulating layer is formed on a semiconductor substrate. A contact plug penetrating the interlayer insulating layer is formed. An oxidation barrier layer and a molding layer are sequentially formed on the semiconductor substrate having the contact plug and the interlayer insulating ... 10/13/05 - 20050224854 - Semiconductor memory device and method of manufacturing the same In one embodiment, a plurality of contact holes are formed using an self-aligned contact (SAC) process to expose active regions. When storage node contact or BC pads are formed in the contact holes, a conductive layer is partially filled in the contact holes to expose the sidewall of an interlayer ... 10/13/05 - 20050224853 - Semiconductor device, manufacturing process thereof and imaging device A semiconductor device including a pixel region in which one or more pixels are formed and a DRAM cell region in which one or more DRAM cells for storing output signals from the pixels are formed, characterized in that the layers constituting the pixel region and the DRAM cell region ... 10/13/05 - 20050224852 - Offset vertical device The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor and a first underlying capacitor that are in electrical ... 10/06/05 - 20050218439 - Semiconductor device and method of manufacturing the same Bit lines having first conductive patterns and bit line mask patterns are formed on a first insulating layer between capacitor contact regions of a substrate. An oxide second insulating layer is formed on the bit lines and contact patterns are formed to open storage node contact hole regions corresponding to ... 10/06/05 - 20050218438 - Bulk non-planar transistor having strained enhanced mobility and methods of fabrication A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed on a semiconductor substrate wherein the semiconductor body has a ... 09/29/05 - 20050212024 - Memory device with an active material embedded in an insulating material The invention relates to a method for producing a memory device, and to a memory device having an active material adapted to be placed in a more or less conductive state by means of appropriate switching processes, the active material is embedded in electrically insulating material. ... 09/29/05 - 20050212023 - Semiconductor memory device, and fabrication method thereof A semiconductor memory device of the invention comprises a plurality of bit lines formed by implanting a second conductive-type impurity in a first conductive-type semiconductor substrate; a thick insulating film on the bit lines; a thin insulating film between the neighboring bit lines; and a plurality of word lines formed ... 09/29/05 - 20050212022 - Memory cell having an electric field programmable storage element, and method of operating same Disclosed is a memory cell having an access transistor and an electric field programmable bi-stable element. The access transistor may be a (N-channel or P-channel) MOSFET transistor having a gate, source or drain region coupled to the electric field programmable bi-stable or multi-stable element (hereinafter collectively, “bi-stable element” unless expressly ... 09/29/05 - 20050212021 - Metal-insulator-metal capacitors A metal-insulator-metal (MIM) capacitor is provided. The bottom electrode of the MIM capacitor is electrically connected to a connection node. The connection node may be, for example, a contact formed in an interlayer dielectric, a polysilicon connection node, a doped polysilicon or silicon region, or the like. A contact provides ... 09/22/05 - 20050205915 - Method of fabricating storage capacitor in semiconductor memory device, and storage capacitor structure A storage capacitor has a double cylinder type structure, with a small cylinder in a lower part thereof and a cylindrical lower electrode structure disposed on the cylindrical contact plug. A method of fabricating the storage capacitor includes: forming a contact hole for exposing an activation region of a transistor; ... 09/22/05 - 20050205914 - Semiconductor device and method of manufacturing the same A semiconductor device has the following construction. A first metal layer consisting of a buried metal layer is connected to a diffusion layer within a substrate or to a lower-layer wiring. Further, a first metal wiring layer, a second metal layer consisting of a buried metal layer, and a second ... 09/22/05 - 20050205913 - Semiconductor substrate and method of fabricating semiconductor device A semiconductor substrate includes a wafer including an element area and a non-element area delineating the element area, a first layered structure situated in the element area, a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to an etching recipe, a second ... 09/15/05 - 20050199930 - Transistor of a semiconductor device having a punchthrough protection layer and methods of forming the same According to some embodiments of the invention, transistors of a semiconductor device have a punchthrough protection layer, and methods of forming the same are provided. A channel-portion hole extends downward from a main surface of a semiconductor substrate. A punchthrough protection layer and a channel-portion layer are sequentially formed at ... 09/15/05 - 20050199929 - Capacitor device and semiconductor device having the same, and capacitor device manufacturing method In a capacitor device of the present invention, a capacitor parts that has a pair of terminals on both end sides respectively is embedded in an insulating film in a state that a lower surface of the capacitor parts is not covered with the insulating film, then upper wiring patterns ... 09/08/05 - 20050194628 - Capacitor with conducting nanostructure The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including ... 09/08/05 - 20050194627 - Non-volatile semiconductor memory device and process for fabricating the same A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive ... 09/01/05 - 20050189576 - Semiconductor storage device A semiconductor storage device comprises a semiconductor substrate; an insulating layer formed on the semiconductor substrate; a first semiconductor layer formed on the insulating layer and insulated from the semiconductor substrate; memory cells each having a source region of a first conduction type and a drain region of the first ... 09/01/05 - 20050189575 - Semiconductor fabrication that includes surface tension control In one embodiment, a method includes providing a semiconductor substrate that includes a memory container having a double-sided capacitor. The method also includes vapor phase etching a layer adjacent to the side wall of the memory container with a vapor having a surface tension lowering agent. ... 08/25/05 - 20050184324 - Storage capacitor structure and liquid crystal display device having the same A storage capacitor structure comprising a first capacitor electrode on a substrate, a capacitor dielectric layer on the first capacitor electrode and a second capacitor electrode on the capacitor dielectric layer, a passivation layer on the second capacitor electrode and a pixel electrode layer on the passivation layer. The second ... 08/25/05 - 20050184323 - Semiconductor memory with trench capacitor and method of fabricating the same A semiconductor device includes semiconductor substrate, a trench capacitor formed in the semiconductor substrate, a cell transistor adjacently formed to the trench capacitor and having a gate electrode formed on the semiconductor substrate and a source/drain region formed in a surface of the semiconductor substrate, an impurity diffusion region formed ... 08/18/05 - 20050179075 - Transistors having a channel region between channel-portion holes and methods of forming the same According to some embodiments of the invention, transistors have channel regions between channel-portion holes. Methods of forming the same include at least two channel-portion holes disposed in a semiconductor substrate. Line patterns are formed in parallel to be spaced apart from each other on a main surface of the semiconductor ... 08/18/05 - 20050179074 - Semiconductor device and manufacturing method thereof A semiconductor device comprises a semiconductor substrate having a first conductivity type, a trench capacitor, provided in the semiconductor substrate, having a charge storage region, a gate electrode provided on the semiconductor substrate via a gate insulating film, first and second impurity regions, provided at both ends of the gate ... 08/18/05 - 20050179073 - Integrated circuit devices having buried insulation layers and methods of forming the same An integrated circuit device includes a gate electrode formed on an active region of an integrated circuit device and on a field isolation layer adjacent to the active region. A source region and a drain region are in the active region on alternate sides of the gate electrode. At least ... 08/11/05 - 20050173747 - Methods for making semiconductor structures having high-speed areas and high-density areas Methods for making a semiconductor structure are discussed. The methods include forming openings in a high-density area and a high-speed area, and forming a metallization layer simultaneously into the high-density area and the high-speed area. The metallization layer includes a combination of substances and compounds that reduce vertical resistance, reduce ... 08/11/05 - 20050173746 - Use of gate electrode workfunction to improve dram refresh This invention relates to a method and resulting structure, wherein a DRAM may be fabricated by using silicon midgap materials for transistor gate electrodes, thereby improving refresh characteristics of access transistors. The threshold voltage may be set with reduced substrate doping requirements. Current leakage is improved by this process as ... 08/11/05 - 20050173745 - Capacitor structures, dram cell structures, and integrated circuitry, and methods of forming capacitor structures, integrated circuitry and dram cell structures The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a) a first layer is formed; b) a semiconductive material masking layer is formed over the first layer; c) an ... 08/11/05 - 20050173744 - Recessed-type field effect transistor with reduced body effect For fabricating a field effect transistor, an extra-doped channel region is formed below a surface of a semiconductor substrate. An opening is formed in the semiconductor substrate into the extra-doped channel region. A gate insulator is formed at walls of the opening such that the extra-doped channel region abuts the ... 08/11/05 - 20050173743 - Cell arrays of memory devices having extended source strapping regions A cell array of a flash memory device includes extended source strapping regions. The cell array includes a device isolation layer and active regions. The device isolation layer is formed in a semiconductor substrate, and the active regions are defined by the device isolation layer. Word lines cross over the ... 08/04/05 - 20050167717 - Semiconductor memory device and method for manufacturing the same A conductive portion connects a lower conductive layer formed on a semiconductor substrate provided in a first interlayer insulating layer to an upper conductive layer formed on the lower conductive layer, and provided in a second interlayer insulating layer. This portion is divided into at least one plug and a ... 08/04/05 - 20050167716 - Ferro-electric memory device and method of manufacturing the same A ferro-electric memory device includes a semiconductor substrate, a first transistor formed on the semiconductor substrate, and a first ferro-electric capacitor electrically connected to the first transistor and formed of a first capacitor material layer having a first lower electrode, a first ferro- electric film, and a first upper electrode, ... 07/28/05 - 20050161721 - Word lines for memory cells Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an ... 07/28/05 - 20050161720 - Semiconductor device and method of manufacturing the semiconductor device A semiconductor device has a stabilizing member that encloses an upper portion of a storage electrode to improve structural stability. A dielectric layer and a plate electrode are successively formed on the storage electrode including a stabilizing member. Since the stabilizing member includes a protruding portion to support the storage ... 07/28/05 - 20050161719 - Semiconductor memory device having a shallow trench isolation structure A semiconductor memory device includes a cell array having matrix-like arrayed plural SRAMs on a semiconductor substrate having an N-well and P-well. The N-well and the P-well are isolated from each other with an isolation region each having a shallow trench structure. Each memory cell includes two CMOS inverter circuits ... 07/28/05 - 20050161718 - Non-volatile dram and a method of making thereof A method of forming a non-volatile DRAM includes, in part, forming a first polysilicon layer above a first dielectric layer to form a control gate of the non-volatile device of the non-volatile DRAM; forming sidewall spacers adjacent the first polysilicon layer; forming a second oxide layer; forming a second polysilicon ... 07/21/05 - 20050156218 - Semiconductor memory cell and associated fabrication method A semiconductor memory cell and an associated fabrication method are provided in which a storage capacitor is connected to a selection transistor. The storage capacitor is formed in a trench of a semiconductor substrate. At the trench surface, a capacitor dielectric and an electrically conductive filling layer are formed thereon ... 07/21/05 - 20050156217 - Semiconductor memory device and method for fabricating the same A semiconductor memory device includes a plurality of memory cells. Each memory cell includes a capacitor which is composed of a first electrode, at least one particle made of ferroelectric or high dielectric constant material and selectively arranged on the first electrode, and a second electrode formed on the particle. ... 07/14/05 - 20050151179 - Dopant barrier for doped glass in memory devices A semiconductor device has a diffusion barrier formed between a doped glass layer and surface structures formed on a substrate. The diffusion barrier includes alumina and optionally a nitride, and has a layer thickness satisfying the high aspect ratio of the gaps between the surface structures, while adequately preventing dopants ... 07/14/05 - 20050151178 - Buried collar trench capacitor formed by locos using self starved ald nitride as an oxidation mask A method for manufacturing a trench capacitor that comprises defining a semiconductor substrate, forming a trench with a lower region and an upper region in the semiconductor substrate, forming a buried conductive region around the lower region, forming a first insulating layer along sidewalls of the trench up to a ... 07/07/05 - 20050145911 - Memory having a vertical transistor Structures and fabrication methods for a memory are provided. The memory includes an array of memory cells, where each memory cell has a pillar extending outwardly from a substrate. The pillar includes a first contact layer and a second contact layer separated by an insulating layer. A transistor is formed ... 07/07/05 - 20050145910 - Nonvolatile semiconductor memory device In a nonvolatile semiconductor memory device including a variable resistive element formed by sequentially stacking a lower electrode, a variable resistor with a perovskite-type crystal structure, and an upper electrode, at least one of the lower electrode and the upper electrode is a particulate electrode configured to include a particulate ... 06/30/05 - 20050139889 - Dram cell structure with buried surrounding capacitor and process for manufacturing the same A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and being spaced apart from other islands by ... 06/30/05 - 20050139888 - Semiconductor device and fabricating method thereof A semiconductor device and fabricating method thereof is provided, by which capacitance is enhanced by increasing an effective area of a lower electrode of a capacitor. A lower electrode is included on a semiconductor substrate, a plurality of conductive protrusions having a cup or U shape is formed on the ... 06/30/05 - 20050139887 - Methods of fabricating capacitor A fabricating method of a capacitor is disclosed. Particularly, a fabricating method of a capacitor which forms a capacitor in the place where the insulation layer of an STI region is removed, preventing interlayer dielectric layers from becoming thick. A disclosed method comprises: defining an STI region in the predetermined ... 06/30/05 - 20050139886 - Capacitor for semiconductor device and fabricating method thereof A capacitor for a semiconductor device includes a first inter metal dielectric layer is disposed on a substrate. A first electrode is disposed on the first inter metal dielectric layer. A second electrode partially overlaps the first electrode. A first dielectric layer is disposed between the first and second electrodes. ... 06/30/05 - 20050139885 - Capacitor pair structure for increasing the match thereof A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its ... 06/30/05 - 20050139884 - Memory cell having improved interconnect A memory cell having improved interconnect. Specifically, a dynamic random access memory (DRAM) based content addressable (CAM) memory cell is provided. The lower cell plate of the storage capacitor is implemented to provide an interconnect for the access transistor and the CAM portion of the memory cell. Conductive plugs are ... 06/16/05 - 20050127420 - Semiconductor memory device with surface strap and method of fabricating the same A method of fabricating a semiconductor memory device, comprising recess-etching a major surface of a semiconductor substrate, thereby forming a pillar that becomes a device formation region; burying an insulation film in the recess-etched region, thereby forming a device isolation region; burying a first oxide film at a side wall ... 06/16/05 - 20050127419 - Semiconductor integrated circuit device A semiconductor integrated circuit device is provided, which involves inhibiting a pattern change in the node interconnect and an increase of number of manufacturing process, when the capacitor is additionally installed in the SRAM, while providing higher reliability in the node interconnect. There is provided a semiconductor integrated circuit device, ... 06/09/05 - 20050121712 - Flash memory cell and method of manufacturing the same and programming/erasing/reading method of flash memory cell Disclosed is a flash memory cell and method of manufacturing the same, and programming/erasing/reading method thereof. The flash memory cell comprises a first tunnel oxide film formed at a given region of a semiconductor substrate, a first floating gate formed on the first tunnel oxide film, a second tunnel oxide ... 06/09/05 - 20050121711 - Chip and wafer integration process using vertical connections A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at ... 06/09/05 - 20050121710 - Semiconductor memory device for storing data as state of majority carriers accumulated in channel body and method of manufacturing the same A semiconductor memory device comprises a substrate; a first semiconductor layer of a first conduction type having a single crystalline structure isolated from the substrate by an insulator layer; a plurality of memory transistors, each having a gate electrode connected to a word line, a pair of impurity regions of ... 06/02/05 - 20050116273 - Semiconductor device and manufacturing method thereof In a DRAM-incorporated semiconductor device (SOC) which has a DRAM section and a logic section being formed on one and the same substrate, with the object of providing, with low cost, a SOC having necessary and sufficient characteristics in the DRAM section, while attaining higher-speed performance of the whole elements, ... 06/02/05 - 20050116272 - Semiconductor device and manufacturing method thereof A semiconductor device and a manufacturing method thereof in which the peripheral length of an aperture and the mechanical strength of cylinders in a cell can be increased without changing the occupation rate of patterns in the cell. By forming a slit in the middle of each mask pattern so ... ### FreshPatents.com Support - Terms & Conditions |