FREE patent keyword monitoring and additional FREE benefits. http://images1.freshpatents.com/images/triangleright (1K) REGISTER now for FREE triangleleft (1K)
FreshPatents.com Logo    FreshPatents.com icons
Monitor Keywords Patent Organizer File a Provisional Patent Browse Inventors Browse Industry Browse Agents


Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) > With Ferroelectric Material Layer

With Ferroelectric Material Layer

With Ferroelectric Material Layer patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

09/18/14 - 20140264510 - Memory array with self-aligned epitaxially grown memory elements and annular fet
A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory array...

09/18/14 - 20140264511 - Spin hall effect assisted spin transfer torque magnetic random access memory
Embodiments are directed to providing a spin hall effect (SHE) assisted spin transfer torque magnetic random access memory (STT-MRAM) device by coupling a magnetic tunnel junction (MTJ) to a SHE material, and coupling the SHE material to a transistor. Embodiments are directed to a spin transfer torque magnetic random access...

09/18/14 - 20140264512 - Structure and fabrication of memory array with epitaxially grown memory elements and line-space patterns
A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory elements...

09/18/14 - 20140264513 - Spin hall effect assisted spin transfer torque magnetic random access memory
Embodiments are directed to providing a spin hall effect (SHE) assisted spin transfer torque magnetic random access memory (STT-MRAM) device by coupling a magnetic tunnel junction (MTJ) to a SHE material, and coupling the SHE material to a transistor. Embodiments are directed to a spin transfer torque magnetic random access...

09/18/14 - 20140264514 - Complementary spin device and method for operation
A complementary device including a gate electrode, a channel, a source electrode connected to the gate electrode and the channel, and a first drain electrode and a second drain electrode connected to the gate electrode and the channel is provided. The first/second drain electrode is formed so that, in accordance...

09/18/14 - 20140264515 - Ferroelectric field-effect transistor
A ferroelectric field-effect transistor device includes: a semiconductor layer; a ferroelectric layer; and an ion conductor layer arranged between the semiconductor layer and the ferroelectric layer and in contact with the semiconductor layer. Methods for producing the ferroelectric field-effect transistor device and using the ferroelectric field-effect transistor device in non-volatile...

09/18/14 - 20140264516 - Methods of forming patterns and methods of manufacturing semiconductor devices using the same
An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a second direction. The plurality of line patterns extend in a first direction substantially perpendicular to the second direction. A second mask...

09/11/14 - 20140252438 - Three-dimensional magnetic random access memory with high speed writing
One embodiment of a magnetic random access memory includes a magnetic memory cell comprising a transistor disposed on a substrate, electrically coupled to a first conductive line and comprising a gate width; a plurality of magnetoresistive elements, each magnetoresistive element comprising an element width, a pinned magnetic layer comprising a...

09/11/14 - 20140252439 - Mram having spin hall effect writing and method of making the same
A spin-transfer-torque magnetoresistive memory comprises apparatus and method of manufacturing a three terminal magnetoresistive memory element having highly conductive bottom electrodes overlaid on top of a SHE-metal layer in the regions outside of an MTJ stack. The memory cell comprises a bit line positioned adjacent to selected ones of the...

08/21/14 - 20140231888 - Magneto-electric voltage controlled spin transistors
The invention relates to a magneto-electric spin-FET including a gate film of chromia and a thin film of a conductive channel material which may be graphene, InP, GaAs, GaSb, PbS, MoS2, WS2, MoSe2, WSe2 and mixtures thereof. The chromia, or other magneto-electric, and conduction channel material are in intimate contact...

08/21/14 - 20140231889 - Shift register memory and driving method thereof
A shift register memory according to the present embodiment includes a magnetic pillar including a plurality of magnetic layers and a plurality of nonmagnetic layers provided between the magnetic layers adjacent to each other. A stress application part applies a stress to the magnetic pillar. A magnetic-field application part applies...

08/07/14 - 20140217487 - Stt-mram and method of manufacturing the same
A planar STT-MRAM comprises apparatus, a method of operating a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory element having spin-transfer torques acting on a recording layer from a MTJ stack and a novel magnetoresistance with a spin-valve layer. The spin-valve layer is field-reversible between two stable magnetization states...

07/24/14 - 20140203341 - Electric field assisted perpendicular stt-mram
A perpendicular STT-MRAM comprises apparatus, a method of operating and a method of manufacturing a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory element having a recording layer which has an interface interaction with an underneath dielectric functional layer. The energy switch barrier of the recording layer is reduced...

07/24/14 - 20140203342 - Ferroelectric random access memory with optimized hardmask
Device structures, fabrication methods, and design structures for a capacitor of a memory cell of ferroelectric random access memory device. The capacitor may include a first electrode comprised of a first conductor, a ferroelectric layer on the first electrode, a second electrode on the ferroelectric layer, and a cap layer...

07/10/14 - 20140191304 - Cmos transistors, fin field-effect transistors and fabrication methods thereof
A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate; and configuring a channel region along a first direction. The method also includes forming trenches at both sides of the channel region along a second direction; and forming a magnetic material layer in each of...

06/26/14 - 20140175528 - Semiconductor magnetic field sensors
A semiconductor magnetic field sensor comprising a semiconductor well on top of a substrate layer is disclosed. The semiconductor well includes a first current collecting region and a second current collecting region and a current emitting region placed between the first current collecting region and the second current collecting region....

06/05/14 - 20140151770 - Thin film deposition and logic device
A method for depositing a material on a graphene layer includes arranging a graphene layer having an exposed substantially planar surface proximate to a magnetron assembly that is operative to emit a plasma plume substantially along a first line, wherein the exposed planar surface of the graphene layer is arranged...

06/05/14 - 20140151771 - Thin film deposition and logic device
A method for depositing a material on a graphene layer includes arranging a graphene layer having an exposed substantially planar surface proximate to a magnetron assembly that is operative to emit a plasma plume substantially along a first line, wherein the exposed planar surface of the graphene layer is arranged...

05/22/14 - 20140138753 - Transistors, memory cells and semiconductor constructions
Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate,...

05/15/14 - 20140131780 - Spin torque transfer memory cell structures and methods
Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures comprise a STT stack including: a pinned ferromagnetic material in contact with an antiferromagnetic material; a tunneling barrier material positioned between a ferromagnetic storage material and the pinned ferromagnetic material; a...

05/15/14 - 20140131781 - Low resistance stacked annular contact
An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting...

03/27/14 - 20140084352 - Ferroelectric random access memory with optimized hardmask
Device structures, fabrication methods, and design structures for a capacitor of a memory cell of ferroelectric random access memory device. The capacitor may include a first electrode comprised of a first conductor, a ferroelectric layer on the first electrode, a second electrode on the ferroelectric layer, and a cap layer...

03/13/14 - 20140070289 - Ferroelectric memory and manufacturing method thereof
According to one embodiment, a ferroelectric memory includes a gate insulation film formed on a semiconductor substrate, a ferroelectric film formed on the gate insulation film, and a control electrode formed on the ferroelectric film. The ferroelectric film is a film containing a metal, which is hafnium or zirconium, and...

03/13/14 - 20140070290 - Ferroelectric memory and manufacturing method of the same
According to one embodiment, a ferroelectric memory includes a semiconductor layer, an interfacial insulating film formed on the semiconductor layer, a ferroelectric film formed on the interfacial insulating film, and a gate electrode formed on the ferroelectric film, wherein the ferroelectric film is a film which includes a metal that...

02/13/14 - 20140042508 - Semiconductor memory devices
A semiconductor memory device includes a cell gate dielectric layer and a cell gate electrode disposed in a gate recess region crossing a cell active portion of a substrate, first and second doped regions disposed in the cell active portion at both sides of the gate recess region, respectively, at...

01/30/14 - 20140027830 - Access transistor with a buried gate
A magnetic memory cell is formed including a magneto tunnel junction (MTJ) and an access transistor, which is used to access the MTJ in operation. The access transistor, which is formed on a silicon substrate, includes a gate, drain and source with the gate position substantially perpendicular to the plane...

01/23/14 - 20140021520 - Semiconductor storage device
A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of...

01/02/14 - 20140001524 - Spin hall effect memory
An embodiment of the invention includes a memory cell having a magnet layer coupled to a metal layer and read line. The metal layer is also coupled to write and sense lines. During a write operation charge current is supplied to the metal layer via the write line and induces...

01/02/14 - 20140001525 - Semiconductor memory device and method of manufacturing the same
The semiconductor memory device includes a cell transistor having a gate insulating film deposited on an inner surface of a groove formed in an upper surface of the semiconductor substrate, a gate electrode buried in the groove with the gate insulating film formed on the inner surface thereof, and a...

11/28/13 - 20130313623 - Threshold gate and threshold logic array
Threshold gates and related circuitry are disclosed. In one embodiment, a threshold gate includes a threshold realization element and a magnetic tunnel junction (MTJ) element. The MTJ element is switchable from a first resistive state to a second resistive state. To realize a threshold function with the MTJ element, the...

10/24/13 - 20130277722 - Spin field effect logic devices
Provided are spin field effect logic devices, the logic devices including: a gate electrode; a channel formed of a magnetic material above the gate electrode to selectively transmit spin-polarized electrons; a source on the channel; and a drain and an output electrode on the channel outputting electrons transmitted from the...

10/17/13 - 20130270619 - Semiconductor device comprising ferroelectric elements and fast high-k metal gate transistors
Ferroelectric circuit elements, such as field effect transistors or capacitors, may be formed on the basis of hafnium oxide, which may also be used during the fabrication of sophisticated high-k metal gate electrode structures of fast transistors. To this end, the hafnium-based oxide having appropriate thickness and material composition may...

10/10/13 - 20130264620 - Integrated circuit having ferroelectric memory with dense via barrier
A method of forming a barrier/liner for ferroelectric memory capacitors includes chemical vapor depositing 15 to 40 A of a first layer including a refractory metal nitride over a substrate having a plurality of metal-oxide-semiconductor (MOS) gate structures, ferroelectric memory (FeRAM) capacitors, and vias in a dielectric layer overlying the...

09/19/13 - 20130240963 - Stt-mram reference layer having substantially reduced stray field and consisting of a single magnetic domain
An STT MTJ cell is formed with a magnetic anisotropy of its free and reference layers that is perpendicular to their planes of formation. The reference layer of the cell is an SAF multilayered structure with a single magnetic domain to enhance the bi-stability of the magnetoresistive states of the...

09/19/13 - 20130240964 - Magnetic storage apparatus
According to one embodiment, there is provided a magnetic storage apparatus that includes a magnetic resistance effect element with a ferromagnetic storage layer and a ferromagnetic reference layer, and a selective transistor connected to the magnetic resistance effect element. The magnetic resistance effect element has a resistance varied in accordance...

08/29/13 - 20130221417 - Memory devices and methods of fabricating the same
Memory devices and methods of fabricating the same include a substrate including a cell region and a peripheral circuit region, data storages on the cell region, first bit lines on and coupled to the data storages, first contacts coupled to peripheral transistors on the peripheral circuit region, and second bit...

08/08/13 - 20130200446 - Spin-based device
A spin-based device comprises a channel, first and second electrodes configured, in response to a bias configuration, to generate an electric field along the channel, and a spin injector arranged to inject spin into the channel at a point between the first and second electrodes. The device may further comprise...

07/11/13 - 20130175588 - Coherent spin field effect transistor
A coherent spin field effect transistor is provided by depositing a ferromagnetic base like cobalt on a substrate. A magnetic oxide layer is formed on the cobalt by annealing at temperatures on the order of 1000° K to provide a few monolayer thick layer. Where the gate is cobalt, the...

06/06/13 - 20130140614 - Semiconductor device and method for manufacturing the same
A method for manufacturing a semiconductor device comprises: forming a lower electrode on a semiconductor substrate, sputtering a ferroelectric film on the lower electrode using a target, thermal treating the ferroelectric film in an atmosphere containing oxygen in accordance with an accumulated period of use of the target for fabricating...

06/06/13 - 20130140615 - Spin torque transfer memory cell structures and methods
Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an antiferromagnetic material and a multiferroic material in contact with the ferromagnetic...

05/23/13 - 20130126953 - Methods and apparatus for mos capacitors in replacement gate process
Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates...

04/04/13 - 20130082314 - Low resistance stacked annular contact
An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting...

03/14/13 - 20130062674 - Spin transfer torque random access memory
A spin transfer torque random access memory includes a substance unit, a source line unit, an insulation unit, a transistor unit, a MTJ unit, and a bit line unit. The substance unit includes a substance layer. The source line unit includes a plurality of source lines formed inside the substance...

03/07/13 - 20130056810 - Semiconductor device and method for manufacturing same
According to one embodiment, a semiconductor device includes, a semiconductor substrate including a plurality of fins formed in an upper surface of the semiconductor substrate in a first region to extend in a first direction, a first gate electrode extending in a second direction intersecting the first direction to straddle...

03/07/13 - 20130056811 - Hydrogen-blocking film for ferroelectric capacitors
An ammonia-free method of depositing silicon nitride by way of plasma-enhanced chemical vapor deposition (PECVD). Source gases of silane (SiH4) and nitrogen (N2) are provided to a parallel-plate plasma reactor, in which energy is capacitively coupled to the plasma, and in which the wafer being processed has been placed at...

03/07/13 - 20130056812 - Semiconductor memory devices including vertical transistor structures
A semiconductor memory device may include a common source region on a substrate, an active pattern between the substrate and the common source region, a gate pattern facing a sidewall of the active pattern, a gate dielectric pattern between the gate pattern and the active pattern, a variable resistance pattern...

02/14/13 - 20130037871 - Integrated circuit device and method for manufacturing same
An integrated circuit device includes a plurality of fins on an upper surface of a semiconductor substrate and extending in a first direction, a device isolation insulating film placed between the fins, a gate electrode extending in a second direction crossing the first direction on the insulating film; and an...

02/14/13 - 20130037872 - Method for fabricating a damascene self-aligned ferroelectric random access memory (f-ram) having a ferroelectric capacitor aligned with a three dimensional transistor structure
Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM that allows for the formation of a ferroelectric capacitor with separated PZT layers aligned with a preexisting, three dimensional (3-D) transistor structure....

11/22/12 - 20120292677 - Ferroelectric semiconductor transistor devices having gate modulated conductive layer
Ferroelectric semiconductor switching devices are provided, including field effect transistor (FET) devices having gate stack structures formed with a ferroelectric layer disposed between a gate contact and a thin conductive layer (“quantum conductive layer”) . The gate contact and ferroelectric layer serve to modulate an effective work function of the...

11/15/12 - 20120286339 - Semiconductor storage device
A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of...

11/15/12 - 20120286340 - Controlling ferroelectricity in dielectric films by process induced uniaxial strain
A method of controlling ferroelectric characteristics of integrated circuit device components includes forming a ferroelectrically controllable dielectric layer over a substrate; and forming a stress exerting structure proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress...