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Having Insulated Electrode (e.g., Mosfet, Mos Diode)

Having Insulated Electrode (e.g., Mosfet, Mos Diode) patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

Related Categories:

Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)


Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode)



Charge compensation semiconductor devices
01/22/15 - 20150021670 - A field-effect semiconductor device includes a semiconductor body having a first surface and an edge, an active area, and a peripheral area between the active area and the edge, a source metallization on the first surface and a drain metallization. In the active area, first conductivity type drift portions alternate...

Field-effect transistor and method of manufacturing thereof
01/22/15 - 20150021671 - According to this GaN-based HFET, resistivity ρ of a semi-insulating film forming a gate insulating film is 3.9×109 Ωcm. The value of this resistivity ρ is a value derived when the current density is 6.25×10−4 (A/cm2). By inclusion of the gate insulating film by a semi-insulating film having a resistivity...

Contact for high-k metal gate device
01/22/15 - 20150021672 - An integrated circuit having an improved gate contact and a method of making the circuit are provided. In an exemplary embodiment, the method includes receiving a substrate. The substrate includes a gate stack disposed on the substrate and an interlayer dielectric disposed on the gate stack. The interlayer dielectric is...

Semiconductor device and manufacturing method thereof
01/22/15 - 20150021673 - A semiconductor device includes a substrate that has a surface. The semiconductor further includes a fin disposed on the surface and including a semiconductor member. The semiconductor further includes a spacer disposed on the surface, having a type of stress, and overlapping the semiconductor member in a direction parallel to...

Uniform height replacement metal gate
01/08/15 - 20150008488 - A method of manufacturing a semiconductor structure includes forming a raised source-drain region in a semiconductor substrate adjacent to a dummy gate and forming a chemical mechanical polish (CMP) stop layer over the gate structure and above a top surface of the semiconductor substrate. A first ILD layer is formed...

Fin-type field effect transistor and method of fabricating the same
01/08/15 - 20150008489 - A fin-type field effect transistor includes a first fin including a first source, a first drain, and a first channel. The fin-type field effect transistor includes a second fin including a second source, a second drain, and a second channel. The fin-type field effect transistor includes a first semiconductor region...

Fluctuation resistant finfet
01/08/15 - 20150008490 - This improved, fluctuation resistant FinFET, with a doped core and lightly doped epitaxial channel region between that core and the gate structure, is confined to the active-gate span because it is based on a channel structure having a limited extent. The improved structure is capable of reducing FinFET random doping...

Metal gate structure
01/08/15 - 20150008491 - A device comprises a metal gate structure in a trench and over a substrate, wherein the gate structure comprises a first metal sidewall in the trench, wherein the first metal sidewall becomes progressively thinner towards an upper portion of the first metal sidewall, a second metal sidewall in the trench,...

Semiconductor device and method of manufacturing same
01/08/15 - 20150008492 - According to one embodiment, a semiconductor device of a junctionless structure includes a semiconductor layer of a first conductivity type. A pair of source/drain electrodes at a distance is on the semiconductor layer. A gate insulating film is on the semiconductor layer between the source/drain electrodes. A gate electrode is...

Bulk finfet with partial dielectric isolation featuring a punch-through stopping layer under the oxide
01/01/15 - 20150001591 - A bulk finFET with partial dielectric isolation is disclosed. The dielectric isolation is disposed underneath the channel, and essentially bounded by the channel, such that it does not extend laterally beyond the channel under the source and drain regions. This allows increased volume of SiGe source and drain stressor regions...

Semiconductor device with self-protecting fuse and method of fabricating the same
01/01/15 - 20150001592 - A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature...

Method for forming multi-gate device with dual channel
01/01/15 - 20150001593 - The present disclosure relates a Fin field effect transistor (FinFET) device having large effective oxide thickness that mitigates hot carrier injection, and an associated method of formation. In some embodiments, the FinFET device has a conductive channel of a first fin protruding from a planar substrate. The conductive channel has...

Forming tunneling field-effect transistor with stacking fault and resulting device
01/01/15 - 20150001594 - Methods for forming stacking faults in sources, or sources and drains, of TFETs to improve tunneling efficiency and the resulting devices are disclosed. Embodiments may include designating areas within a substrate that will subsequently correspond to a source region and a drain region, selectively forming a stacking fault within the...

Finfet with multiple concentration percentages
01/01/15 - 20150001595 - An apparatus of a semiconductor is provided wherein the apparatus comprises a substrate, a stack, and a fin. The substrate supports the stack and the substrate comprises a first material. The stack provides for the fin and the stack comprises: a strain induced in the stack via the substrate; the...

Radiation tolerant dummy gate-assisted n-mosfet, and method and apparatus for modeling channel of semiconductor device
01/01/15 - 20150001596 - The DGA n-MOSFET layout of the present invention can properly operate in a radioactive environment by blocking leakage current paths that may be created by radiation. Hence, the DGA n-MOSFET layout can be applied to design of electronic components operable in radioactive environments, such as outer space, planetary exploration, and...

Substantially planar electronic devices and circuits
01/01/15 - 20150001597 - A method of manufacturing a substantially planar electronic device is disclosed. The method employs a resist having three different thicknesses used for defining different structures in a single masking step. Exemplary structures are substantially planar transistors having side-gates and diodes....

Divot-free planarization dielectric layer for replacement gate
01/01/15 - 20150001598 - After formation of a silicon nitride gate spacer and a silicon nitride liner overlying a disposable gate structure, a dielectric material layer is deposited, which includes a dielectric material that is not prone to material loss during subsequent exposure to wet or dry etch chemicals employed to remove disposable gate...

Power semiconductor package with non-contiguous, multi-section conductive carrier
01/01/15 - 20150001599 - In one implementation, a power semiconductor package includes a non-contiguous, multi-section conductive carrier. A control transistor with a control transistor terminal is coupled to a first section of the multi-section conductive carrier, while a sync transistor with a sync transistor terminal is coupled to a second section of the multi-section...

Semiconductor structure and manufacturing method thereof
12/25/14 - 20140374805 - A manufacturing method for a semiconductor device first provides a substrate having at least a first transistor formed thereon. The first transistor includes a first conductivity type. The first transistor further includes a first metal gate and a protecting layer covering sidewalls of the first metal gate. A portion of...

Four terminal transistor
12/25/14 - 20140374806 - A transistor includes a substrate, a first electrically conductive material layer positioned on the substrate, and a first electrically insulating material layer is positioned on the first electrically conductive material layer. A gate includes a second electrically conductive material and a reentrant profile in which a first portion of the...

Method of device isolation in cladding si through in situ doping
12/25/14 - 20140374807 - Aspects of the present invention relate to an approach for forming an integrated circuit having a set of fins on a silicon substrate, with the set of fins being formed according to a predetermined pattern. In situ doping of the fins with an N-type dopant prior to deposition of an...

Finfet spacer etch for esige improvement
12/18/14 - 20140367751 - A method for etching FinFET spacers by inserting a Si recess step directly after the traditional spacer ME step and the resulting device are provided. Embodiments include forming a gate on a substrate having a silicon fin, the gate having a nitride cap on an upper surface thereof and an...

Transistor having all-around source/drain metal contact channel stressor and method to fabricate same
12/18/14 - 20140367752 - An intermediate transistor structure includes a fin structure disposed on a surface of an insulating layer. The fin structure has a gate structure disposed thereon between first and second ends of the fin structure. A first portion of the fin structure is a first doped portion that is disposed over...

Cmos device with double-sided terminals and method of making the same
12/18/14 - 20140367753 - A transistor device includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a gate structure disposed on the first surface and configured to form a channel region, and source and drain regions disposed on opposite sides of the channel region. The device also...

Method for manufacturing semiconductor device and semiconductor device
12/18/14 - 20140367754 - A method for manufacturing a semiconductor device includes, forming, on a substrate, an element isolation insulating film which includes a protruding portion protruding above a level of a surface of the substrate, forming a first film on the substrate and on the element isolation insulating film, polishing the first film...

Gate electrode with stabilized metal semiconductor alloy-semiconductor stack
12/11/14 - 20140361351 - A gate structure is provided on a channel portion of a semiconductor substrate. The gate structure may include an electrically conducting layer present on a gate dielectric layer, a semiconductor-containing layer present on the electrically conducting layer, a metal semiconductor alloy layer present on the semiconductor-containing layer, and a dielectric...

Semiconductor device and fabrication method thereof
12/11/14 - 20140361352 - A method for fabricating a semiconductor device is provided herein and includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate, wherein a periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a...

Semiconductor device and method for manufacturing the same
12/11/14 - 20140361353 - The present application discloses a method for manufacturing a semiconductor device, comprising: forming a T-shape dummy gate structure on the substrate; removing the T-shape dummy gate structure and retaining a T-shape gate trench; filling successively a gate insulation layer and a metal layer in the T-shape gate trench, wherein the...

Embedded transistor
12/11/14 - 20140361354 - An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate...

Method and apparatus for a reduced capacitance middle-of-the-line (mol) nitride stack
12/04/14 - 20140353728 - A method of capacitance reduction in a middle-of-the-line (MOL) nitride stack and a resulting device are disclosed. Embodiments include forming an oxide layer between one or more semiconductor devices on a wafer, the one or more semiconductor devices having source/drain junctions therebetween, forming a nitride layer over the one or...

Semiconductor structure and method for forming the same
12/04/14 - 20140353729 - A semiconductor structure and a method for forming the same are provided. The method comprises following steps. A gate material film is formed on a substrate in a first device region and a second device region. The gate material film in the first device region is patterned to form a...

Low gate-to-drain capacitance fully merged finfet
12/04/14 - 20140353730 - A low gate-to-drain capacitance merged finFET and methods of manufacture are disclosed. The method includes forming a plurality of fins on a substrate. The method further includes forming at least one dummy gate structure intersecting the plurality of fins. The method further includes forming a gap between sidewalls of the...

Tuning strain in semiconductor devices
12/04/14 - 20140353731 - A Fin Field-Effect Transistor (FinFET) includes a semiconductor layer over a substrate, wherein the semiconductor layer forms a channel of the FinFET. A first silicon germanium oxide layer is over the substrate, wherein the first silicon germanium oxide layer has a first germanium percentage. A second silicon germanium oxide layer...

Halo region formation by epitaxial growth
12/04/14 - 20140353732 - A semiconductor device and method for manufacturing the same, wherein the method includes fabrication of field effect transistors (FET). The method includes growing a doped epitaxial halo region in a plurality of sigma-shaped source and drain recesses within a semiconductor substrate. An epitaxial stressor material is grown within the sigma-shaped...

Protection of the gate stack encapsulation
12/04/14 - 20140353733 - Semiconductor device structures at advanced technologies are provided, wherein a reliable encapsulation of a gate dielectric is already formed during very early stages of fabrication. In illustrative embodiments, a gate stack is formed over a surface of a semiconductor substrate and a sidewall spacer is formed adjacent to the gate...

Semiconductor devices and methods of fabrication with reduced gate and contact resistances
12/04/14 - 20140353734 - Semiconductor structures with reduced gate and/or contact resistances and fabrication methods are provided. The method includes: providing a semiconductor device, which includes forming a transistor of the semiconductor device, where the transistor forming includes: forming a T-shaped gate for the transistor, the T-shaped gate being T-shaped in elevational cross-section; and...

Localized fin width scaling using a hydrogen anneal
12/04/14 - 20140353735 - Transistors and methods for fabricating the same include forming one or more semiconductor fins on a substrate; covering source and drain regions of the one or more semiconductor fins with a protective layer; annealing uncovered channel portions of the one or more semiconductor fins in a gaseous environment to reduce...

Field-effect transistor
12/04/14 - 20140353736 - A field-effect transistor includes a plurality of unit elements, an insulating film, and a wiring. The plurality of unit elements include a semiconductor layer having a first surface, a plurality of drain electrodes, gate electrodes, and a source electrode. The source electrode is electrically continuously provided across the plurality of...

Semiconductor device including embedded crystalline back-gate bias planes, related design structure and method of fabrication
11/27/14 - 20140346573 - A method of forming a semiconductor device is disclosed. The method includes forming a first dielectric layer on a substrate; forming a set of bias lines on the first dielectric layer; covering the set of bias lines with a second dielectric layer; forming a semiconductor layer on the second dielectric...

Asymmetric finfet semiconductor devices and methods for fabricating the same
11/27/14 - 20140346574 - Asymmetric FinFET devices and methods for fabricating such devices are provided. In one embodiment, a method includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon and depositing a conformal liner over the fin structures. A first portion of the conformal liner is removed, leaving a first...

Semiconductor device with self-aligned contact and method of manufacturing the same
11/27/14 - 20140346575 - A semiconductor device with a self-aligned contact and a method of manufacturing the same, wherein the method comprises the step of forming a 1st dielectric layer on gate structures, form a self-aligned contact trench between two gate structures, forming an 2nd dielectric layer on the 1st dielectric layer and in...

Mosfets with multiple dislocation planes
11/27/14 - 20140346576 - A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET). The Method includes performing an implantation to form a pre-amorphization implantation (PAI) region adjacent to a gate electrode of the MOSFET, forming a strained capping layer over the PAI region, and performing an annealing on the strained capping layer and the...

Electronic device with asymmetric gate strain
11/27/14 - 20140346577 - The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain can be obtained through non symmetric placement of stress inducing structures as part of the gate electrode....

Finfet device and method of fabrication
11/20/14 - 20140339610 - Embodiments of the present invention provide a novel method and structure for forming finFET structures that comprise standard cells. An H-shaped cut mask is used to reduce the number of fins that need to be removed, hence increasing the fin efficiency....

Stacked semiconductor nanowires with tunnel spacers
11/20/14 - 20140339611 - A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating...

Using sacrificial oxide layer for gate length tuning and resulting device
11/20/14 - 20140339612 - Methods for controlling the length of a replacement metal gate to a designed target gate length and the resulting device are disclosed. Embodiments may include removing a dummy gate from above a substrate forming a cavity, wherein side surfaces of the cavity are lined with an oxidized spacer layer and...

Semiconductor device and method of manufacturing same
11/20/14 - 20140339613 - In one embodiment, a semiconductor device includes a semiconductor substrate, and a gate insulator arranged on the semiconductor substrate. The device further includes a gate electrode including a semiconductor layer and a metal layer which are sequentially arranged on the gate insulator. The device further includes a contact plug arranged...

Self-aligned wrapped-around structure
11/13/14 - 20140332859 - An embodiment vertical wrapped-around structure and method of making. An embodiment method of making a self-aligned vertical structure-all-around device including forming a spacer around an exposed portion of a semiconductor column projecting from a structure layer, forming a photoresist over a protected portion of the structure layer and a first...

Stacked carbon-based fets
11/13/14 - 20140332860 - Methods and systems for forming stacked transistors. Such methods include forming a lower channel layer on a substrate; forming a pair of vertically aligned gate regions over the lower channel layer; forming a pair of vertically aligned source regions and a pair of vertically aligned drain regions on the lower...

Fin structure with varying isolation thickness
11/13/14 - 20140332861 - Semiconductor fins having isolation regions of different thicknesses on the same integrated circuit are disclosed. Nitride spacers protect the lower portion of some fins, while other fins do not have spacers on the lower portion. The exposed lower portion of the fins are oxidized to provide isolation regions of different...

Stacked carbon-based fets
11/13/14 - 20140332862 - Stacked transistor devices include a lower channel layer formed on a substrate; a pair of vertically aligned source regions formed over the lower channel layer, where the pair of source regions are separated by an insulator; a pair of vertically aligned drain regions formed on the lower channel layer, where...

Semiconductor device and method of manufacturing the same
11/13/14 - 20140332863 - Provided are a semiconductor device and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an active fin on a substrate; oxidizing a portion of the active fin to form an insulating pattern between the active fin and the substrate; forming a first gate...

Method for providing a gate metal layer of a transistor device and associated transistor
11/13/14 - 20140332864 - A method includes providing a dummy gate structure on a substrate. The dummy gate structure includes a gate dielectric layer and a dummy gate electrode layer, and is laterally defined by inner sidewalls of a set of spacers. The method also includes laterally embedding the dummy gate structure, removing the...

Semiconductor device
11/13/14 - 20140332865 - A semiconductor device includes a substrate having an edge, a semiconductor layer provided on a substrate, an electrode pad provided on the semiconductor layer, an inorganic insulating film having a first opening through which an upper surface of the electrode pad is exposed, and a resin film provided on the...

Semiconductor device
11/13/14 - 20140332866 - A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface...

Semiconductor device and manufacturing method thereof
11/13/14 - 20140332867 - It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is...

Raised source/drain and gate portion with dielectric spacer or air gap spacer
11/06/14 - 20140327054 - A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes epitaxial raised source/drain (RSD) regions formed on the surface of a semiconductor substrate through selective epitaxial growth. In one embodiment, the faceted side portions of the RSD regions are utilized to form cavity regions which...

Replacement gate process and device manufactured using the same
11/06/14 - 20140327055 - A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard...

Semiconductor device having contact plug and method of manufacturing the same
11/06/14 - 20140327056 - The device further comprises a contact hole extending through the interlayer dielectric layer and a contact plug having an upper surface and electrically connecting to the substrate in the contact hole. The upper surface of the contact plug has a second height lower than the first height. A spacer is...

Power semiconductor device with a double metal contact
11/06/14 - 20140327057 - A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof....

Self-aligned contacts for replacement metal gate transistors
11/06/14 - 20140327058 - Embodiments of the invention include methods of forming gate caps. Embodiments may include providing a semiconductor device including a gate on a semiconductor substrate and a source/drain region on the semiconductor substrate adjacent to the gate, forming a blocking region, a top surface of which extends above a top surface...

Photolithographic, thickness non-uniformity, compensation features for optical photolithographic semiconductor structure formation
10/30/14 - 20140319586 - A semiconductor structure having a substrate; an active device formed in an active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region between a pair of electrical contacts; and a photolithographic, thickness non-uniformity, compensation feature, disposed...

Through-substrate vias and methods for forming the same
10/30/14 - 20140319587 - A device includes a semiconductor substrate and a Metal-Oxide-Semiconductor (MOS) transistor. The MOS transistor includes a gate electrode over the semiconductor substrate, and a source/drain region on a side of the gate electrode. A source/drain contact plug includes a lower portion and an upper portion over the lower portion, wherein...

Fin-fet transistor with punchthrough barrier and leakage protection regions
10/23/14 - 20140312393 - A method of forming a field effect transistor includes forming a punchthrough region having a first conductivity type in a substrate, forming an epitaxial layer having the first conductivity type on the substrate, patterning the epitaxial layer to form a fin that protrudes from the substrate, forming a dummy gate...

Semiconductor device including a material to absorb thermal energy
10/23/14 - 20140312394 - A semiconductor device includes a semiconductor chip and a first material including molecules that are configured to absorb thermal energy by reversibly changing a spatial molecular structure of the molecules....

Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact
10/23/14 - 20140312395 - A photo-patternable dielectric material is provided to a structure which includes a substrate having at least one gate structure. The photo-patternable dielectric material is then patterned forming a plurality of sacrificial contact structures adjacent the at least one gate structure. A planarized middle-of-the-line dielectric material is then provided in which...

Split multi-gate field-effect transistor
10/23/14 - 20140312396 - A semiconductor device based on split multi-gate field-effect transistor radio frequency devices is provided. The semiconductor device includes a substrate and a gate structure above the substrate and orthogonal to a channel axis. The semiconductor device also includes a semiconductor fin structure above the substrate along the channel axis. The...

Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact
10/23/14 - 20140312397 - A photo-patternable dielectric material is provided to a structure which includes a substrate having at least one gate structure. The photo-patternable dielectric material is then patterned forming a plurality of sacrificial contact structures adjacent the at least one gate structure. A planarized middle-of-the-line dielectric material is then provided in which...

Recessing sti to increase fin height in fin-first process
10/23/14 - 20140312398 - A method includes forming a gate stack over top surfaces of a semiconductor strip and insulation regions on opposite sides of the semiconductor strip. The insulation regions include first portions overlapped by the gate stack, and second portions misaligned from the gate stack. An end portion of the semiconductor strip...

Semiconductor device and method of manufacturing the same
10/23/14 - 20140312399 - A gate insulating film of a conventional semiconductor device is subjected to dielectric breakdown at a low electric field strength and thus its service life is short. This is because since the size of the asperity of at least one of a semiconductor layer-side interface and an electrode-side interface is...

Unltra-shallow junction semiconductor field-effect transistor and method of making
10/16/14 - 20140306271 - An ultra-shallow junction semiconductor field-effect transistor and its methods of making are disclosed. In the present disclosure, a mixture film is formed on a semiconductor substrate with a gate structure formed thereon using a physical vapor deposition (PVD) process, which employs a mixture of metal and semiconductor dopants as a...

Method of forming a finfet structure
10/16/14 - 20140306272 - A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed...

Structure of metal gate structure and manufacturing method of the same
10/16/14 - 20140306273 - A manufacturing method of a metal gate structure is provided. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate...

Self-aligned structure for bulk finfet
10/16/14 - 20140306274 - A FinFET structure which includes a bulk semiconductor substrate; semiconductor fins extending from the bulk semiconductor substrate, each of the semiconductor fins having a top portion and a bottom portion such that the bottom portion of the semiconductor fins is doped and the top portion of the semiconductor fins is...

Semiconductor device and method of manufacturing semiconductor device
10/16/14 - 20140306275 - A semiconductor device is disclosed. The semiconductor device includes an insulating layer formed selectively on a semiconductor layer; a lower electrode, formed on the insulating layer, having an end portion at a position spaced apart by a predetermined distance inward from a periphery of the insulating layer; a dielectric film...