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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode) Having Insulated Electrode (e.g., Mosfet, Mos Diode)Having Insulated Electrode (e.g., Mosfet, Mos Diode) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/31/08 - 20080023733 - Fabrication methods for compressive strained-silicon and transistors using the same Fabrication methods for compressive strained-silicon by ion implantation. Ions are implanted into a silicon-containing substrate and high temperature processing converts the vicinity of the ion-contained region into strained-silicon. Transistors fabricated by the method are also provided. ... 01/31/08 - 20080023732 - Use of carbon co-implantation with millisecond anneal to produce ultra-shallow junctions Embodiments of the present invention include methods for forming an ultra-shallow junction in a substrate. In one embodiment, the method includes providing a silicon substrate, co-implanting the silicon substrate with carbon and a dopant to form a doped silicon substrate, and exposing the silicon substrate to a short time thermal ... 01/24/08 - 20080017899 - Self-aligned nanotube field effect transistor and method of fabricating same A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a ... 01/24/08 - 20080017898 - Integrated circuit having second epitaxial layer An integrated circuit having a semiconductor device with reduced “tail” resistance and production method for such a device is disclosed. One embodiment provides at least one substrate of a first conduction type doped with a first concentration of donors of a first atom type, and a first epitaxial layer of ... 01/24/08 - 20080017897 - Semiconductor device and method of manufacturing same A semiconductor device includes: a semiconductor layer of a first conductivity type; a plurality of first semiconductor pillar regions of the first conductivity type provided on a major surface of the semiconductor layer; a plurality of second semiconductor pillar regions of a second conductivity type being adjacent to the first ... 01/17/08 - 20080012052 - Semiconductor device and method for implantation of doping agents in a channel A semiconductor device includes a substrate of a first type of conductivity provided with at least one gate on one of its faces, and at least two doped regions of a second type of conductivity for forming a drain region and a source region. The two doped regions are arranged ... 01/10/08 - 20080006856 - Semiconductor device with back surface electrode including a stress relaxation film A semiconductor device includes a semiconductor substrate which has first and second principal surface regions; an insulated gate structure which is formed in the first principal surface region; a back surface region semiconductor layer which is formed in the second principal surface region and has a thickness of at most ... 12/27/07 - 20070296003 - Thin film transistor substrate and method for manufacturing the same A thin-film transistor (TFT) substrate includes a base substrate, a semiconductor layer, a gate insulating layer, a first gate electrode and a second gate electrode. The semiconductor layer is formed on the base substrate and includes source, drain, channel and low concentration doped regions. The channel region is formed between ... 12/20/07 - 20070290239 - Method of fabricating semiconductor device In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including ... 12/13/07 - 20070284633 - Curled semiconductor transistor A curled transistor comprises a coiled semiconductor substrate having a plurality of concentrically curled layers. Source and drain regions are configured on a portion of the coiled semiconductor substrate, and a gate dielectric is positioned between the source and drain regions. A first set of metallic contacts electrically couple to ... 12/13/07 - 20070284630 - Field effect transistor for measuring biocomponents The invention relates to a device for measuring living cells or similar biocomponents comprising a field effect transistor which is provided with a source, a drain and a channel area placed on a substrate. Said channel area connects said source and drain and is provided with a gate-electrode mounted thereon. ... 11/29/07 - 20070272955 - Reliable contacts A nickel-based germanide contact includes a processing material that inhibits agglomeration of nickel-based germanide during processing to form the contact as well as during post-germanidation processes. The processing material is either in the form of a capping layer over the nickel layer or integrated into the nickel layer used to ... 11/15/07 - 20070262363 - Low temperature fabrication of discrete silicon-containing substrates and devices Fabrication methods and processes are described, the methods and processes occurring at a low-temperature and involving passivation. The methods and processes easily incorporate annealing, deposition, patterning, lithography, etching, oxidation, epitaxy and chemical mechanical polishing for forming suitable devices, such as diodes and MOSFETs. Such fabrication is a suitable and more ... 11/01/07 - 20070252181 - Semiconductor device, method for manufacturing semiconductor device, and electronic appliance having the semiconductor device In order to connect a semiconductor device including an integrated circuit to an external circuit typified by an antenna, the shape of the contact electrode to be formed in the semiconductor device is devised, so that bad connection between the external circuit and the contact electrode is not easily caused ... 11/01/07 - 20070252180 - Semiconductor element, semiconductor device, and method for manufacturing the same A semiconductor element includes: a semiconductor region formed in a semiconductor substrate and containing an impurity of a predetermined conductivity type; source and drain regions formed to face each other in the semiconductor region, and containing a metal or a compound of a metal and a semiconductor forming the semiconductor ... 10/25/07 - 20070246754 - Semiconductor device and method for manufacture A semiconductor device is formed with a lower field plate (32) and optional lateral field plates (34) around semiconductor (20) in which devices are formed, for example power FETs or other transistor or diode types. The semiconductor device is manufactured by forming trenches with insulated sidewalls, etching cavities (26) at ... 10/25/07 - 20070246753 - Metal gated ultra short mosfet devices MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer ... 10/25/07 - 20070246752 - Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering and methods for fabricating such device structures and for fabricating a semiconductor-on-insulator substrate Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering, methods for fabricating such device structures, and methods for forming a semiconductor-on-insulator substrate. The semiconductor structure comprises a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first ... 10/25/07 - 20070246751 - Spacer structure and fabrication method thereof A spacer structure contains a carbon-containing oxynitride film positioned on a gate sidewall and a nitride film covering the carbon-containing oxide film. The carbon-containing oxynitride film has low etch rate so that the spacer structure can have a good profile during etching the carbon-containing oxynitride film. ... 10/18/07 - 20070241373 - Semiconductor device and its manufacturing method In the process of manufacturing a semiconductor device, a first layer is formed on a substrate, and the first layer and the substrate are etched to form a trench. The inner wall of the trench is thermally oxidized. On the substrate, including inside the trench, is deposited a first conductive ... 10/11/07 - 20070235779 - Lateral dmos transistor and method for the production thereof A lateral DMOS-transistor is provided that includes a MOS-diode made of a semi-conductor material of a first type of conductivity, a source-area of a second type of conductivity and a drain-area of a second type of conductivity which is separated from the MOS-diode by a drift region made of a ... 10/11/07 - 20070235776 - Forming memory arrays Source strap cells which are manufactured in a very similar way to conventional memory cells may be utilized to enable connections to the source of a memory cell. In other words, the source and the drain may be contacted by vias which are arranged identically in some embodiments. This may ... 10/11/07 - 20070235775 - High efficiency and/or high power density wide bandgap transistors Field effect transistors having a power density of greater than 40 W/mm when operated at a frequency of at least 4 GHz are provided. The power density of at least 40 W/mm may be provided at a drain voltage of 135 V. Transistors with greater than 60% PAE and a ... 10/04/07 - 20070228430 - Devices and methods of preventing plasma charging damage in semiconductor devices Methods for protecting semiconductor devices from plasma charging damage are disclosed. An example disclosed method includes depositing an etching stop layer on a substrate with at least one predetermined structure; depositing a premetallic dielectric layer and a charge preservation layer on the entire surface of the etching stop layer; depositing ... 10/04/07 - 20070228429 - Method of doping a gate electrode of a field effect transistor A method of fabricating a structure and fabricating related semiconductor transistors and novel semiconductor transistor structures. The method of fabricating the structure includes: providing a substrate having a top surface; forming an island on the top surface of the substrate, a top surface of the island parallel to the top ... 10/04/07 - 20070228428 - High-voltage metal-oxide-semiconductor device and method of manufacturing the same The present invention pertains to a high-voltage MOS device. The high-voltage MOS device includes a substrate, a first well, a first field oxide layer enclosing a drain region, a second field oxide enclosing a source region, and a third field oxide layer encompassing the first and second field layers with ... 10/04/07 - 20070228425 - Method and manufacturing low leakage mosfets and finfets By aligning the primary flat of a wafer with a (100) plane rather than a (110) plane, devices can be formed with primary currents flowing along the (100) plane. In this case, the device will intersect the (111) plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation/relief ... 09/27/07 - 20070221972 - Mosfet for synchronous rectification This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by connecting a shunt FET of low impedance to the MOSFET device. The shunt FET is to shunt a transient current therethrough. The shunt FET is employed for preventing an inadvertent turning on of ... 09/27/07 - 20070221969 - Semiconductor device and method of manufacturing the same In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type silicon substrate. In the epitaxial layer, P type diffusion layers as a base region, N type diffusion layers as collector regions and an N type diffusion layer as an emitter region ... 09/27/07 - 20070221967 - Semiconductor device and method for forming the same A semiconductor device may include a semiconductor substrate having a first dopant type. A first semiconductor region within the semiconductor substrate may have a plurality of first and second portions (44, 54). The first portions (44) may have a first thickness, and the second portions (54) may have a second ... 09/27/07 - 20070221966 - Method for integrally forming an electrical fuse device and a mos transistor A method for integrally forming a metal-oxide-semiconductor (MOS) device and an electrical fuse device on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. A dielectric layer is deposited over the isolation structure and the semiconductor substrate. A metal layer is deposited on ... 09/27/07 - 20070221965 - Dmos device with sealed channel processing A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then ... 09/20/07 - 20070215920 - Semiconductor component arrangement comprising a trench transistor Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least a gate electrode disposed in the at least one trench. An electrode structure ... 09/20/07 - 20070215919 - Reduction of threshold voltage instabilities in a mos transistor A MOS transistor includes an etch stop layer presenting a density of less than a determined threshold value, below which the material of said stop layer is permeable to molecules of dihydrogen and/or water. The material may comprise a nitride. A material used for the etch stop layer preferably has ... 09/20/07 - 20070215918 - Semiconductor device with extension structure and method for fabricating the same A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in ... 09/20/07 - 20070215915 - Multi-step gate structure and method for preparing the same A multi-step gate structure comprises a semiconductor substrate having a multi-step structure, a gate oxide layer positioned on the multi-step structure and a conductive layer positioned on the gate oxide layer. Preferably, the gate oxide layer has different thicknesses on each step surface of the multi-step structure. In addition, the ... 09/20/07 - 20070215914 - Power semiconductor device having improved performance and method In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes an offset body region. ... 09/13/07 - 20070210358 - Method of forming a gate oxide film for a high voltage region of a flash memory device A method of forming a gate oxide film for high voltage region of semiconductor devices includes forming patterns on a semiconductor substrate having a high voltage region, thereby exposing only a gate oxide film formation region for high voltage, forming a metal oxidization layer on the entire surface, and performing ... 09/13/07 - 20070210357 - Mosfet having recessed channel and method of fabricating the same A MOSFET having a recessed channel and a method of fabricating the same. The critical dimension (CD) of a recessed trench defining the recessed channel in a semiconductor substrate is greater than the CD of the gate electrode disposed on the semiconductor substrate. As a result, the misalignment margin for ... 09/13/07 - 20070210356 - Power semiconductor device A power semiconductor device which includes an implant region in the base region thereof to reduce Qgd. ... 09/13/07 - 20070210355 - Semiconductor device A semiconductor device includes: an insulating layer; a semiconductor fin protruding from the insulating layer, extending in a first direction parallel to a major surface of the insulating layer, and having a source region, a channel section, and a drain region arranged in the first direction; a gate electrode opposed ... 09/13/07 - 20070210352 - Semiconductor device and method of manufacturing the same The present invention relates to a semiconductor device and a method of manufacturing the same, and is intended to keep the electrical resistance of source/drain regions at a low level while preventing diffusion of impurities from a semiconductor film and a sidewall. In order to achieve these objects, the semiconductor ... 09/06/07 - 20070205446 - Reducing nitrogen concentration with in-situ steam generation In-situ steam generation (ISSG) is used to reduce the nitrogen concentration in silicon and silicon oxide areas. ... 09/06/07 - 20070205445 - Semiconductor device having a field effect source/drain region A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by ... 09/06/07 - 20070205444 - Architecture of a n-type metal-oxide-semiconductor transistor with a compressive strained silicon-germanium channel fabricated on a silicon (110) substrate The present invention discloses an architecture of a NMOS transistor with a compressive strained Si—Ge channel fabricated on a silicon (110) substrate, which comprises: a p-silicon (110) substrate, two n+ ion-implanted regions functioning as the source and the drain respectively, a compressive strained Si—Ge channel layer, and a gate structure. ... 09/06/07 - 20070205443 - Vertical gated access transistor According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The plurality of ... 09/06/07 - 20070205442 - Semiconductor device A semiconductor device 10 comprises a P type base region 13 formed in an N− type base region 11, and N+ type emitter regions 14 formed plurally in the P type base region 13 so as to be spaced form each other. The N+ type emitter regions 14 are formed ... 08/23/07 - 20070194355 - Transistor device with two planar gates and fabrication process A planar transistor device includes two independent gates (a first and second gates) along with a semiconductor channel lying between the gates. The semiconductor channel is formed of a first material. The channel includes opposed ends comprising dielectric zone with a channel region positioned between the gates. The dielectric zones ... 08/23/07 - 20070194354 - Nitride based transistors for millimeter wave operation Field effect transistors having a power density of greater than 5 W/mm when operated at a frequency of at least 30 GHz are provided. The power density of at least 5 W/mm may be provided at a drain voltage of 28 V. Transistors with a power density of at least ... 08/16/07 - 20070187731 - Methods for forming semiconductor wires and resulting devices Methods for forming a wire from silicon or other semiconductor material are disclosed. Also disclosed are various devices including such a semiconductor wire. According to one embodiment, a wire is spaced apart from an underlying substrate, and the wire extends between a first end and an opposing second end, each ... 08/16/07 - 20070187728 - Field effect transistor with suitable source, drain and channel materials and integrated circuit comprising same The normally on transistor comprises a source, a drain and a channel. The source, drain and channel materials are chosen such that, for a NMOS type transistor, the electronic affinity of the drain material is lower than the electronic affinity of the channel material and the electronic affinity of the ... 08/09/07 - 20070181920 - Manufacturing method for a semiconductor substrate comprising at least a buried cavity and devices formed with this method A method for manufacturing a semiconductor substrate of a first concentration type is described, which comprises at least a buried insulating cavity, comprising the following steps: forming on the semiconductor substrate a plurality of trenches, forming a surface layer on the semiconductor substrate in order to close superficially the plurality ... 08/09/07 - 20070181919 - Novel isolated ldmos ic technology A lateral double diffused metal oxide semiconductor (LDMOS) device includes a gate to control the device, a drain coupled to the gate formed in a well of a first type, a source to form a current path with the drain, and a first field oxide region disposed between the gate ... 08/09/07 - 20070181918 - Semiconductor device A semiconductor device has a MOS capacitor in which a drain region and a source region of a MOS structure are commonly connected, and a capacitance is formed between the commonly connected drain region/source region and a gate electrode of the MOS structure; and a wiring capacitor which has a ... 08/09/07 - 20070181917 - Split dual gate field effect transistor A semiconductor device with at least two gate regions. The device includes a substrate region including a surface, a source region in the substrate region, and a drain region in the substrate region. The drain region and the source region are separate from each other. Additionally, the device includes a ... 07/26/07 - 20070170474 - Semiconductor device and method of fabricating the same A semiconductor device according to one embodiment of the present invention includes: a semiconductor substrate; a non-planar type transistor region having at least one of a fin type transistor region including a fin type transistor in which a current is induced to flow through side faces of a fin formed ... 07/26/07 - 20070170473 - Apparatus using manhattan geometry having non-manhattan current flow A device is described, including a first diffusion region having a first terminal, a second diffusion region having a second terminal, and a channel region disposed between the first diffusion region and the second diffusion region. Further, the first terminal and the second terminal are offset to enable a non-Manhattan ... 07/19/07 - 20070164328 - Method of manufacturing semiconductor device and the semiconductor device manufactured by the method The method of manufacturing the semiconductor device that includes a high voltage MOS transistor with high operating voltage under both high and low gate voltages with low-cost is disclosed. When manufacturing the high voltage MOS transistor, a portion of a gate insulation film is removed to form an opening that ... 07/19/07 - 20070164326 - Field effect transistor A field effect transistor includes a semiconductor layer structure including GaN channel layer 12 and AlGa electron supply layer 13, source electrode 1 and drain electrode 3 which are formed on electron supply layer 13 so as to be separated from each other, gate electrode 2 formed between source electrode ... 07/12/07 - 20070158703 - Electronic device and a process for forming the electronic device An electronic device can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive member, spaced apart from and adjacent to ... 07/12/07 - 20070158702 - Transistor including flatband voltage control through interface dipole engineering A transistor comprising a semiconductor including a source, a drain, and a channel interposed between the source and the drain; a first dielectric layer having a first thickness, the first dielectric layer being positioned on the channel; a second dielectric layer having a second thickness, the second dielectric layer being ... 07/12/07 - 20070158701 - Excessive round-hole shielded gate trench (sgt) mosfet devices and manufacturing processes This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a shielded gate trench ... 07/12/07 - 20070158700 - Field effect transistor and method for producing the same A field effect transistor comprising: a semiconductor layer projecting from the plane of a base; a gate electrode provided on opposite side surfaces of the semiconductor layer; a gate insulating film interposed between the gate electrode and the side surface of the semiconductor layer; and source/drain regions where a first ... 07/05/07 - 20070152245 - Semiconductor device and method for manufacturing the same Disclosed is a semiconductor device. The semiconductor device includes; a pair of drift regions formed in a semiconductor substrate; a trench region formed between the pair of drift regions; an oxide layer spacer on both sidewalls of the trench region; a gate formed in the trench region; and a source ... 06/28/07 - 20070145436 - Thin film transistor substrate of liquid crystal display and method for fabricating same An exemplary thin film transistor substrate (200) includes a substrate (201), a gate (212), a gate insulating layer (203), an amorphous silicon layer (214), a pixel electrode (216), a drain (217), and a source (218). The gate is formed at the gate. The gate insulating layer is formed at the ... 06/28/07 - 20070145435 - Mos varactor Embodiments relate to a MOS varactor and a method for manufacturing the same, in which an ion implantation process for adjusting a threshold voltage may be omitted so as to lower the surface density of an N type well, thereby expanding a tuning range. The MOS varactor may include a ... 06/28/07 - 20070145434 - Semiconductor device Embodiments relate to a method for manufacturing a semiconductor substrate. According to embodiments, a gate oxide layer may be formed on a semiconductor substrate. Also, a well region may be formed in the semiconductor substrate including the gate oxide layer. Then, after forming a gate electrode on the semiconductor substrate, ... 06/28/07 - 20070145433 - Semiconductor device Embodiments relate to a semiconductor device and a method for manufacturing the same. According to embodiments, a semiconductor device may include an active area defined on a semiconductor substrate by a first isolation layer and a second isolation layer, a diode in the active area placed at one side of ... 06/28/07 - 20070145432 - Semiconductor device Embodiments relate to a semiconductor device that may include a gate stack formed on an upper portion of an active region in a semiconductor substrate, the gate stack including a gate insulating layer and a gate, a first shallow impurity region formed on both sides of the gate in the ... 06/28/07 - 20070145430 - Cmos device with asymmetric gate strain The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain is obtained through non symmetric placement of stress inducing structures as part of the gate electrode. Silicon nitride layers may ... 06/21/07 - 20070138518 - Semiconductor device and method of manufacturing thereof An active region on a semiconductor substrate is electrically isolated by trench isolation. A structure of the trench isolation is constituted of: a trench; a silicon oxide film formed on the inner wall of trench; an oxidation preventive film formed between silicon oxide film and semiconductor substrate; and a filling ... 06/21/07 - 20070138517 - Field-effect transistor, semiconductor device including the field-effect transistor, and method of producing semiconductor device A field-effect transistor includes a semi-insulating substrate, a source electrode, a drain electrode, a gate electrode, the electrodes being provided on the semi-insulating substrate, and a buried gate region which is provided under the gate electrode and in which an impurity is doped, wherein a concave slit is provided in ... 06/21/07 - 20070138516 - Semiconductor memory device and method of manufacturing thereof A semiconductor memory (26) having a plurality of memory cells (25), the semiconductor memory (26) having a substrate (1), at least one wordline (2) and first (3) and second lines (4). Each memory cell (25) of the plurality of memory cells (25) includes a fin (15) of semiconductor material, the ... 06/14/07 - 20070131986 - Semiconductor device and method of manufacturing the same Embodiments relate to a semiconductor device and a method for manufacturing the same. According to embodiments, a semiconductor device may include an LDD which may include a space having a first width and may be formed in a semiconductor substrate, a channel area which may be formed in the semiconductor ... 06/14/07 - 20070131985 - Semiconductor device and method for manufacturing the same A semiconductor device and a method for manufacturing the same are provided, in which the work function of a gate electrode being in contact with a gate insulating film can be efficiently adjusted while depletion of the gate electrode is suppressed. An SOI substrate is composed of a p-type silicon ... 06/14/07 - 20070131984 - Semiconductor device and method for fabricating the same A semiconductor device includes a first MIS transistor of a non-salicide structure and a second MIS transistor of a salicide structure which are both formed on a substrate of silicon. The first MIS transistor includes a first gate electrode of silicon, first sidewalls, a first source and drain, and plasma ... 06/14/07 - 20070131983 - Tri-gate integration with embedded floating body memory cell using a high-k dual metal gate Dual-gate memory cells and tri-gate CMOS devices are integrated on a common substrate. A plurality of silicon bodies are formed from a monocrystalline silicon on the substrate to define a plurality of transistors including dual-gate memory cells, PMOS transistors, and NMOS transistors. An insulative layer is formed overlying the silicon ... 06/14/07 - 20070131982 - Memory cell structure and method for fabricating the same A memory cell structure comprises a semiconductor substrate, two stack structures positioned on the semiconductor substrate, two conductive spacers positioned on sidewalls of the two stack structures, a gate oxide layer covering a portion of the semiconductor substrate between the two conductive spacers and a gate structure positioned at least ... 06/14/07 - 20070131981 - Patterning method and field effect transistors Patterning method, and field effect transistors An explanation is given of, inter alia, a patterning method, in which a filling material (22) with a T-shaped cross section is used as a mask during patterning in order to produce structures having sublithographic dimensions, in particular a double-fin field effect transistor. ... 06/07/07 - 20070126038 - Small-sized semiconductor device featuring protection circuit for mosfet In a semiconductor device, a metal oxide semiconductor field effect transistor (MOSFET) is formed in a semiconductor substrate, and an isolation layer is formed on the semiconductor substrate so as to extend along a side of the semiconductor substrate. A first conductive layer is formed on the isolation layer along ... 06/07/07 - 20070126037 - Electric device having nanowires, manufacturing method thereof, and electric device assembly An electric device having a plurality of nanowires, in which at least one of the nanowires is cut or changed in its electric characteristics so as to have a desired characteristic value of the electric device. ... 06/07/07 - 20070126036 - Semiconductor device and semiconductor device manufacturing method A semiconductor device is configured so that there is formed a stressor film 4 covering the first field effect transistor and the second field effect transistor, formed with openings from which the originating area and the terminating area of each of the first field effect transistor and the second field ... 06/07/07 - 20070126035 - Field-effect microelectronic device, capable of forming one or several transistor channels The invention relates to a field-effect microelectronic device, as well as the method of production thereof. The device includes a substrate (700) as well as at least one improved structure (702) capable of forming one or more transistor channels. This structure, formed by a plurality of bars stacked on the ... 06/07/07 - 20070126034 - Semiconductor substrate, semiconductor device and process for producing semiconductor substrate An opening 35 is formed on an assembly having a silicon germanium layer 32, a silicon layer 33, and a silicon oxide layer 34 sequentially formed on a silicon basis material 31. An additional silicon oxide layer 36 is formed so as to cover the silicon oxide layer 34 and ... 05/31/07 - 20070120156 - Enhanced segmented channel mos transistor with multi layer regions By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges ... 05/31/07 - 20070120155 - Colors only process to reduce package yield loss Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical ... 05/31/07 - 20070120154 - Finfet structure with multiply stressed gate electrode A semiconductor structure and its method of fabrication include a semiconductor fin located over a substrate. A gate electrode is located over the semiconductor fin. The gate electrode has a first stress in a first region located closer to the semiconductor fin and a second stress which is different than ... 05/24/07 - 20070114581 - Transistor of semiconductor device and method for manufacturing the same A transistor of a semiconductor device capable of improving the device reliability, and a method for manufacturing the same are provided. The transistor includes an active portion having a first height from a semiconductor substrate surface and having a line-shaped cross-section; a device isolation layer in which a round portion ... 05/24/07 - 20070114580 - Nonvolatile semicondutor storage device and manufacturing method thereof A nonvolatile semiconductor storage device includes a plurality of memory cells, each including a drain formed above a substrate, a source formed at a bottom of a groove in the substrate, a floating gate formed above the substrate between the drain and a side surface of the groove, and a ... 05/24/07 - 20070114579 - Method for integrally forming a damascene gate structure and a resistive device A method for integrally forming a damascene gate structure and a resistive device on a semiconductor substrate is disclosed. A first dielectric layer having a first opening and a second opening is formed on the semiconductor substrate. One or more sidewall spacers are formed on inner sides of the first ... 05/17/07 - 20070108483 - Thin film transistor and method of fabricating the same A thin film transistor having an offset or a lightly doped drain (LDD) structure by self alignment and a method of fabricating the same comprises a substrate, a silicon layer disposed on the substrate and including a channel region, a source region and a drain region at both sides of ... 05/17/07 - 20070108482 - Non-volatile electromechanical field effect devices and circuits using same and methods of forming same Under one aspect, a field effect device includes a gate, a source, and a drain, with a conductive channel between the source and the drain; and a nanotube switch having a corresponding control terminal, said nanotube switch being positioned to control electrical conduction through said conductive channel. Under another aspect, ... 05/17/07 - 20070108481 - Electronic devices including a semiconductor layer and a process for forming the same An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the ... 05/17/07 - 20070108480 - Field effect transistor and method of fabricating the same A field effect transistor according to the present invention has a semiconductor layer through which carriers injected from a source region travel toward a drain region, the semiconductor layer being formed from a composite material including an organic semiconductor material and nanotubes. The nanotubes may be nanotubes including plural ones ... 05/10/07 - 20070102735 - Semiconductor device and method for manufacturing the semiconductor device A semiconductor device includes: a semiconductor substrate; a well formed on the semiconductor substrate; a semiconductor layer formed by epitaxial growth avoiding the well; a buried insulating layer embedded between the semiconductor substrate and the semiconductor layer; a first gate electrode formed on the semiconductor layer, the first gate electrode ... 05/10/07 - 20070102734 - Semiconductor device and method of fabricating the same Disclosed is a semiconductor device and method of fabricating the same. The semiconductor device is applicable to various electronic devices such as transistors or memories with transistors. A MOS transistor of the semiconductor device includes a first region and a second region, different in impurity concentration, which are formed in ... 05/03/07 - 20070096175 - Complementary mis device A CMOS device includes a p-channel MOS transistor and an n-channel MOS transistor having a structure formed on a (100) surface of a silicon substrate and having a different crystal surface, a high-quality gate insulation film formed on such a structure by a microwave plasma process, and a gate electrode ... 05/03/07 - 20070096174 - Semiconductor device having pn junction diode and method for manufacturing the same A semiconductor device includes: a semiconductor support substrate having a first conductive type; an insulation layer on the substrate; a semiconductor layer on the insulation layer; a semiconductor element in the semiconductor layer; and a first impurity diffusion region having a second conductive type. The first impurity diffusion region in ... 05/03/07 - 20070096173 - Semiconductor device and method for manufacturing semiconductor device Provided are a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes: a gate electrode formed of polysilicon on a substrate with a gate insulating layer interposed between the gate electrode and the substrate; a source region and a drain region formed on the substrate ... 05/03/07 - 20070096172 - Semiconductor component with a space-saving edge termination, and method for production of such component An arrangement for use in a semiconductor component includes a semiconductor body and an edge structure. The semiconductor body having a first face, a second face, a first semiconductor zone of a first conductance type, at least one second semiconductor zone of a second conductance type, and a semiconductor junction ... 05/03/07 - 20070096171 - Semiconductor laser device that has the effect of phonon-assisted light amplification and method for manufacturing the same A semiconductor laser device that has the effect of phonon-assisted light amplification and a method for manufacturing the same are proposed. A conductive layer is formed on a semiconductor silicon substrate. A current flow is used to accomplish electro-luminescence of silicon. A silicon dioxide nanometer particle layer is sandwiched between ... 05/03/07 - 20070096170 - Low modulus spacers for channel stress enhancement A semiconductor structure and its method of fabrication employ a semiconductor substrate having a channel region. A gate electrode is located over the semiconductor substrate. A spacer is located adjacent a sidewall of the gate electrode. The spacer is formed of a material having a modulus of from about 10 ... 04/26/07 - 20070090417 - Semiconductor device and method for fabricating the same A semiconductor device includes a first MIS transistor including a first gate electrode fully silicided with a metal. With the first MIS transistor includes: a first gate insulating film formed on a semiconductor region; the first gate electrode formed on the first gate insulating film; a first sidewall spacer formed ... 04/26/07 - 20070090416 - Cmos devices with a single work function gate electrode and method of fabrication Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed ... 04/26/07 - 20070090415 - Power device with high switching speed and manufacturing method thereof A power device is formed by a thyristor and by a MOSFET transistors, series-connected between a first and a second current-conduction terminal. The power device moreover has a control terminal connected to an insulated-gate electrode of the MOSFET transistor and receiving a control voltage for turning on/off the device, and ... 04/19/07 - 20070085113 - Dielectric materials for electronic devices A dielectric material prepared from a siloxy/metal oxide hybrid composition, and electronic devices such as thin film transistors comprising such dielectric material are provided herein. The siloxy/metal oxide hybrid composition comprises a siloxy component such as, for example, a siloxane or silsesquioxane. The siloxy/metal oxide hybrid composition is useful for ... 04/19/07 - 20070085112 - Thin film transistor, display device and liquid crystal display device and method for manufacturing the same As a wiring becomes thicker, discontinuity of an insulating film covering the wiring has become a problem. It is difficult to form a wiring with width thin enough for a thin film transistor used for a current high definition display device. As a wiring is made thinner, signal delay due ... 04/05/07 - 20070075342 - Semiconductor device with fin structure and method of manufacturing the same A semiconductor device with a fin structure according to one embodiment of the present invention includes: a fin of a predetermined height formed on an insulating layer of a substrate; a gate electrode formed on both sides of the fin through a gate insulating film; and a source/drain region formed ... 03/29/07 - 20070069257 - Power semiconductor component having a field electrode and method for producing this component A power semiconductor component includes a semiconductor body and a field electrode. The semiconductor body has a drift zone of a first conduction type and a further component defining a junction therebetween. The junction is configured to cause a space charge zone to propagate when a reverse voltage is applied ... 03/29/07 - 20070069256 - Semiconductor device comprising at least one mos transistor having an etch stop layer, and corresponding fabrication process A semiconductor device includes at least one MOS transistor, each transistor being provided with a source region and a drain region formed in a semiconductor substrate, along with a gate region and spacers. The transistor is covered with a unitary etch stop layer that includes at least a first zone ... 03/29/07 - 20070069255 - Mos transistors having optimized channel plane orientation, semiconductor devices including the same, and methods of fabricating the same MOS transistors having an optimized channel plane orientation are provided. The MOS transistors include a semiconductor substrate having a main surface of a (100) plane. An isolation layer is provided in a predetermined region of the semiconductor substrate to define an active region. A source region and a drain region ... 03/29/07 - 20070069254 - Multiple-gate mos transistor using si substrate and method of manufacturing the same Provided are a multiple-gate MOS (metal oxide semiconductor) transistor and a method of manufacturing the same. The transistor includes a single crystalline active region having a channel region having an upper portion of a streamlined shape (∩) obtained by patterning an upper portion of a bulk silicon substrate with an ... 03/22/07 - 20070063231 - Power semiconductor device with integrated passive component A power semiconductor device that includes a passive component, e.g., a capacitor, mechanically and electrically coupled to at least one pole thereof. ... 03/15/07 - 20070057293 - Ultra high voltage mos transistor device An ultra high voltage MOS transistor device includes a substrate of a first conductivity type; a source region of a second conductivity type formed in the substrate; a first doping region of the first conductivity type formed in the substrate and bordering upon the source region; a first ion well ... 03/01/07 - 20070045676 - Self aligned metal gates on high-k dielectrics A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on a substrate and a sacrificial carbon gate is formed on the gate dielectric. Sacrificial carbon sidewall spacers are formed adjacent to the sacrificial carbon ... 03/01/07 - 20070045675 - High voltage metal oxide semiconductor transistor and fabricating method thereof A high voltage MOS transistor including a substrate, a well, a gate insulation layer, a gate, two drift regions, a channel region, a source/drain region and an isolation structure is provided. The well is disposed in the substrate and the gate insulation layer is disposed over the substrate. The gate ... 02/22/07 - 20070040193 - Semiconductor device, electro-optic device, and electric device A semiconductor device includes a semiconductor layer, and a first transistor and a second transistor that are formed using the semiconductor layer, wherein each conductance of the first and second transistors changes complementarily to each other according to a curvature of the semiconductor layer. ... 02/15/07 - 20070034912 - Low voltage cmos structure with dynamic threshold voltage A method for dynamically varying a threshold voltage of a complimentary metal oxide semiconductor (CMOS) includes providing a substrate pickup formed a semiconductor material type which is complimentary to the semiconductor material type of a well thereof, so as to define a diode. The diode is at least partially turned ... 02/15/07 - 20070034911 - Metal-oxide-semiconductor transistor and method of manufacturing the same The trench MOS transistor according to the present invention includes a drain region in a form of a trench filled with a semiconductor material. The trench has a bottom surface and side surfaces and extends vertically downward from the top surface of the covering layer into the buried layer, the ... 02/08/07 - 20070029588 - Formation of low leakage thermally assisted radical nitrided dielectrics One or more aspects of the present invention relate to forming a dielectric suitable for use as a gate dielectric in a transistor. The gate dielectric is formed by a nitridation process that adds nitrogen to a semiconductor substrate. ... 02/08/07 - 20070029587 - Mos varactor with segmented gate doping A MOS varactor is formed having a gate electrode comprising at least two abutting oppositely doped regions shorted together, in which the two regions are implanted simultaneously with source/drain implants for first and second types of transistor; at least one contact to a lower electrode is also formed simultaneously with ... 02/01/07 - 20070023795 - Semiconductor device and method of fabricating the same A semiconductor device includes a metal oxide semiconductor (MOS) transistor including two source/drain regions located at a surface layer side of the semiconductor substrate, a stress-inducing film formed so as to cover the source/drain region of the MOS transistor, the stress-inducing film applying stress to a channel region formed between ... 02/01/07 - 20070023794 - Stacked semiconductor device and related method A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the ... 02/01/07 - 20070023793 - Trench-gate semiconductor device and manufacturing method of trench-gate semiconductor device Disclosed is a trench-gate semiconductor device including: a trench gate structure; a source layer having a first conductivity type, facing a gate electrode via a gate insulating film, and having a top plane; a base layer having a second conductivity type, being adjacent to the source layer, and facing the ... 02/01/07 - 20070023792 - Transistor and transistor manufacturing method In a transistor of the invention, at a boundary between gate oxide 112 formed on a silicon substrate 101 of a device formation region 10 and a device isolation film 110 adjoining the gate oxide 112, a thickness D′ of the gate electrode 114 is set larger than a uniform ... 02/01/07 - 20070023791 - Method of fabricating gate of fin type transistor A method of fabricating a gate of a fin type transistor includes forming hard masks to define active regions of a substrate. A shallow trench isolation method is performed to form a first device separation layer, and then an etch-back process is performed such that the active regions protrude. Sidewall ... 01/25/07 - 20070018209 - Semiconductor circuit device and simulation method of the same A first PMIS transistor includes a first active region which is formed on a semiconductor substrate and a first gate electrode which is formed on the first active region and which is connected at one end thereof to a first gate wiring and includes at the other end thereof a ... 01/25/07 - 20070018208 - Depletable cathode low charge storage diode An integrated circuit device comprising a diode and a method of making an integrated circuit device comprising a diode are provided. The diode can comprise an island of a first conductivity type, a first region of a second conductivity type formed in the island, and a cathode diffusion contact region ... 01/25/07 - 20070018207 - Split gate storage device including a horizontal first gate and a vertical second gate in a trench A split gate storage device includes a first gate electrode in contact with a first gate dielectric and a second gate electrode in contact with a second gate dielectric. A first diffusion region underlies a portion of a trench defined in a semiconductor substrate and a second diffusion region occupies ... 01/25/07 - 20070018206 - Surround gate access transistors with grown ultra-thin bodies A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching processes. The body has ultra-thin dimensions and provides controlled short ... 01/25/07 - 20070018205 - Structure and method for improved stress and yield in pfets with embedded sige source/drain regions The present invention provides a technique for forming a CMOS structure including at least one pFET that has a stressed channel which avoids the problems mentioned in the prior art. Specifically, the present invention provides a method for avoiding formation of deep canyons at the interface between the active area ... 01/18/07 - 20070012961 - N-type carbon nanotube field effect transistor and method of fabricating the same Provided are an n-type carbon nanotube field effect transistor (CNT FET) and a method of fabricating the n-type CNT FET. The n-type CNT FET may include a substrate; electrodes formed on the substrate and separated from each other; a CNT forrmed on the substrate and electrically connected to the electrodes; ... 01/18/07 - 20070012960 - Direct channel stress An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming a strained channel region in semiconductor devices. Embodiments include forming a stressor layer over an amorphous portion of the semiconductor device at an intermediate stage of fabrication. The device is masked and strain in a portion ... 01/11/07 - 20070007560 - Metal-substituted transistor gates One aspect of this disclosure relates to an integrated circuit structure. An integrated circuit structure embodiment includes a substrate, a gate dielectric over the substrate, a carbon structure having a predetermined thickness in contact with and over the gate dielectric, and a layer of desired gate material for a transistor ... 01/04/07 - 20070001200 - Semiconductor device and method of manufacturing the same A semiconductor device including: a semiconductor substrate including an electrode; a resin protrusion formed on the semiconductor substrate; and an interconnect electrically connected to the electrode and formed to extend over the resin protrusion. The interconnect includes a first portion formed on a top surface of the resin protrusion and ... 01/04/07 - 20070001199 - Circuits and integrated circuits including field effect transistors having differing body effects Field effect transistor integrated circuits include field effect transistors in an integrated circuit substrate, such as a semiconductor substrate. A first one of the field effect transistors has a body effect that is substantially lower than that of a second one of the field effect transistors during operation of the ... 12/28/06 - 20060289909 - Self-aligned low-k gate cap A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be significantly reduced by forming a CMOS structure in which a low-k dielectric ... 12/28/06 - 20060289908 - Field effect device with a channel with a switchable conductivity A field effect device includes a source electrode, a drain electrode, a channel formed between the source electrode and the drain electrode, and a gate electrode formed directly on the channel and arranged in a gap between the source electrode and the drain electrode. The channel includes a switching material ... 12/28/06 - 20060289907 - Metal oxide semiconductor (mos) transistors having buffer regions below source and drain regions and methods of fabricating the same A unit cell of a metal oxide semiconductor (MOS) transistor is provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. ... 12/28/06 - 20060289906 - Semiconductor device including a capacitance It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer ... 12/28/06 - 20060289905 - Semiconductor device A semiconductor device comprising at least one FET formed on the semiconductor substrate, wherein the FET comprises a source region, a drain region, a channel region formed between the source and drain regions and including a plurality of projected epitaxial silicon regions arranged in a width direction of the channel ... 12/28/06 - 20060289904 - Semiconductor device and method of manufacturing the same In the semiconductor device which has partial trench isolation as isolation between elements formed in an SOI substrate, resistance reduction of the source drain of a transistor and reduction of leakage current are aimed at. A MOS transistor is formed in the active region specified by the isolation insulating layer ... 12/21/06 - 20060284221 - Semiconductor device and electronic device A channel forming region of a thin-film transistor is covered with an electrode and wiring line that extends from a source line. As a result, the channel forming region is prevented from being illuminated with light coming from above the thin-film transistor, whereby the characteristics of the thin-film transistor can ... 12/21/06 - 20060284220 - Semiconductor device and manufacturing method of the semiconductor device A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint ... 12/21/06 - 20060284219 - Semiconductor integrated circuit device method of fabricating the same A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a semiconductor substrate, a transistor having a gate interconnection that extends in one direction on the semiconductor substrate and source/drain regions aligned in the gate interconnection and formed in the semiconductor substrate, and a diffusion-preventing metallic pattern ... 12/21/06 - 20060284218 - Nanoelectonic devices based on nanowire networks Semiconductor devices where networks of molecular nanowires (or nanofibers) are used as the semiconductor material. Field effect transistors are disclosed where networks of molecular nanowires are used to provide the electrical connection between the source and drain electrodes. The molecular nanowires have diameters of less than 500 nm and aspect ... 12/14/06 - 20060278903 - Semiconductor device with electrostrictive layer in semiconductor layer and method of manufacturing the same A semiconductor device includes a first semiconductor layer, and a first insulated-gate field-effect transistor of a first conductivity type that is provided in a major surface region of the first semiconductor layer. The semiconductor device further includes an electrostrictive layer that is provided on a back surface of the first ... 12/14/06 - 20060278902 - Nano structure electrode design A microelectronic switch having a substrate layer, an electrically conductive switching layer formed on the substrate layer, an electrically conductive cavity layer formed on the switching layer, an electrically conductive cap layer formed on the cavity layer, the cap layer forming a first electrode and a second electrode that are ... 12/07/06 - 20060273357 - Semiconductor device and manufacturing method thereof The technique capable of reducing the power consumption in the MISFET by suppressing the scattering of the carriers due to the fixed charges is provided. A silicon oxynitride film with a physical thickness of 1.5 nm or more and the relative dielectric constant of 4.1 or higher is formed at ... 11/23/06 - 20060261384 - Lateral misfet and method for fabricating it A lateral MISFET having a semiconductor body has a doped semiconductor substrate of a first conduction type and an epitaxial layer of a second conduction type, which is complementary to the first conduction type, the epitaxial layer being provided on the semiconductor substrate. This MISFET has, on the top side ... 11/16/06 - 20060255379 - Stable diodes for low and high frequency applications A diode is defined on a die. The diode includes a substrate of P conductivity having an upper surface and a lower surface, the substrate having first and second ends corresponding to first and second edges of the die. An anode contacts the lower surface of the substrate. A layer ... 11/16/06 - 20060255378 - Semiconductor device A semiconductor device comprises a P−-type semiconductor substrate (15), an N−-type semiconductor substrate (21) formed on the P−-type semiconductor substrate (15), an upper P-type semiconductor region (13) formed in the surface region of the N−-type semiconductor substrate (21) and electrically connected to a ground electrode (1), a lower P-type semiconductor ... 11/09/06 - 20060249760 - High-voltage transistor of semiconductor device and method of forming the same There are provided a high-voltage transistor and a method of forming the same. A channel region of the high-voltage transistor includes a first region and a second region. The first region has high impurity concentration that is higher than that of the second region. In addition, the first region may ... 11/02/06 - 20060244019 - Semiconductor device and method of fabricating the same A semiconductor device includes a semiconductor substrate having a source region and a drain region, a gate formed on the semiconductor substrate, a diode having a cathode region connected to the drain region, and a bit line connected to an anode region of the diode. The drain region and the ... 11/02/06 - 20060244018 - Semiconductor device and method of manufacture thereof A semiconductor device includes a semiconductor substrate having a first surface. First gate electrodes are formed along a first direction on the first surface. Source/drain areas are formed in the first surface and sandwich a channel region. A first interlayer insulating layer fills a region between the first gate electrodes ... 10/26/06 - 20060237754 - Semiconductor device and method of manufacturing the same A semiconductor device includes a semiconductor substrate having a plurality of trenches, a plurality of element isolation regions formed by burying an element isolation insulating film in the trenches, a gate insulating film formed in an element formation region defined between the element isolation regions on the semiconductor substrate, and ... 10/19/06 - 20060231874 - Field effect transistor and method for fabricating it A transistor is provided which advantageously utilizes a part of the area which, in conventional transistors, is provided for the isolation between the transistors. In this case, the channel width can be enlarged in a self-aligned manner without the risk of short circuits. The field-effect transistor according to the invention ... 10/19/06 - 20060231873 - Planar dual-gate field effect transistors (fets) A semiconductor structure and the associated method for fabricating the same. The semiconductor structure includes (a) a semiconductor substrate, (b) a back gate region on the semiconductor substrate, (c) a back gate dielectric region on the back gate region, (d) a semiconductor region on the back gate dielectric region comprising ... 10/19/06 - 20060231872 - Field effect transistor using insulator-semiconductor transition material layer as channel material and method of manufacturing the same Provided is a field effect transistor including an insulator-semiconductor transition material layer. The insulator-semiconductor transition material layer selectively provides a first state where charged holes are not introduced to a surface of the insulator-semiconductor transition material layer when a gate field is not applied and a second state where a ... 10/12/06 - 20060226455 - Integrated circuit devices having buried insulation layers and methods of forming the same An integrated circuit device includes a gate electrode formed on an active region of an integrated circuit device and on a field isolation layer adjacent to the active region. A source region and a drain region are in the active region on alternate sides of the gate electrode. At least ... 10/12/06 - 20060226454 - Semiconductor device A semiconductor device 1 according to the present invention includes a semiconductor substrate 5, a first transistor 10 which is formed on the semiconductor substrate 5 and includes a first gate electrode portion 16 constituted by a first gate insulating film 24 and a first gate electrode 26 having a ... 10/12/06 - 20060226453 - Methods of forming stress enhanced pmos structures Methods of forming a microelectronic structure are described. Embodiments of those methods include providing a gate structure disposed on a substrate comprising at least one recess, wherein a channel region is in a <110> direction, and then forming a compressive layer in the at least one recess. ... 10/05/06 - 20060220075 - Methods of fabricating self-aligned source of flash memory device Example methods of fabricating semiconductor devices are disclosed. One example method may include depositing an oxide layer, a first conducting layer for a floating gate, a dielectric layer, and a second conducting layer for a control gate in sequence on a semiconductor substrate including a device isolation layer; forming gates ... 10/05/06 - 20060220074 - Carbon nanotube energy well (cnew) field effect transistor A structure to form an energy well within a Carbon nanotube is described. The structure includes a doped semiconductor region and an undoped semiconductor region. The Carbon nanotube is between the doped semiconductor region and the undoped semiconductor region. The structure also includes a delta doped semiconductor region. The undoped ... 09/28/06 - 20060214198 - Semiconductor device and manufacturing method thereof An object of this invention is to prevent the NBTI degradation which may occur following the recent progress in miniaturization of the semiconductor device. By using a silicon nitride film, in which a concentration of Si—H bonds is not greater than 1×1021 cm−3, at least for a liner film or ... 09/28/06 - 20060214197 - Semiconductor device A semiconductor device comprises a semiconductor substrate of a first conductivity type; a semiconductor layer of the first type on the semiconductor substrate; a base layer of a second conductivity type on a surface of the semiconductor layer; a gate insulator formed on sidewalls of each of trenches formed through ... 09/21/06 - 20060208287 - Lateral programmable polysilicon structure incorporating polysilicon blocking diode A programmable element includes a diode and a programmable structure formed in a polysilicon layer isolated from a semiconductor substrate by a dielectric layer. The diode includes a first region and a second region of opposite conductivity types. The programmable structure includes a third region and a fourth region of ... 09/14/06 - 20060202241 - D/a converter circuit, semiconductor device incorporating the d/a converter circuit, and manufacturing method of them D/A conversion having higher accuracy is provided by improving relative accuracy of the resistance value of resistors which configure a resistor string. A manufacturing method of a D/A converter circuit of the invention comprises the steps of: forming a resistor string 11 which includes a plurality of resistors R0 to ... 09/14/06 - 20060202240 - Semiconductor device Provided is a semiconductor device which includes a conductive bonding pad formed on a semiconductor substrate of the first conduction type via an insulating film and a diffusion layer of the second conduction type formed on a surface of the semiconductor substrate under the bonding pad. Characteristics do not deteriorate ... 09/14/06 - 20060202239 - Methods for providing gate conductors on semiconductors and semiconductors formed thereby A method of providing a gate conductor on a semiconductor is provided. The method includes defining an organic polymer plating mandrel on the semiconductor, activating one or more sites of the organic polymer plating mandrel, binding a seed layer to the activated sites, and plating the dummy gate on the ... 09/07/06 - 20060197126 - Methods for forming structures including strained-semiconductor-on-insulator devices The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. ... 09/07/06 - 20060197125 - Methods for forming double gate strained-semiconductor-on-insulator device structures The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. ... 09/07/06 - 20060197124 - Double gate strained-semiconductor-on-insulator device structures The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. ... 09/07/06 - 20060197123 - Methods for forming strained-semiconductor-on-insulator bipolar device structures The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. ... 09/07/06 - 20060197122 - Charge trapping device A silicon based semiconductor device and method uses charge trapping to alter a density of carriers available in a channel of a field effect transistor (FET) for conduction. The charge trapping mechanism can be controlled by a source-drain bias voltages applied to the FET, so that the device can be ... 09/07/06 - 20060197121 - Abrupt channel doping profile for fermi threshold field effect transistors A Fermi threshold voltage FET has Germanium implanted to form a shallow abrupt transition between the semiconductor substrate dopant type, or well dopant type, and a counter doping layer of opposite type closely adjacent the surface of the semiconductor substrate. Germanium is a charge neutral impurity in silicon that significantly ... 09/07/06 - 20060197120 - Gate electrode for semiconductor devices The present invention provides an MIS type semiconductor device, comprising a semiconductor substrate and a gate electrode formed on the gate insulating film and formed of gate material. The gate electrode comprises: a first layer of activated crystalline gate material having a first side oriented towards a substrate and a ... 08/31/06 - 20060192232 - Semiconductor device and method of manufacturing semiconductor device A semiconductor device includes a side wall spacer formed on the side surface of a gate electrode formed on the upper side of a semiconductor substrate with a gate insulation film therebetween, extension regions built up on the semiconductor substrate, and source/drain regions formed on the extension regions, wherein a ... 08/17/06 - 20060180836 - Semiconductor device and manufacturing method thereof In the present invention, in a pattern in which gate electrodes are provided in a stripe shape and source regions are provided in a ladder shape, body regions are provided in a stripe shape parallel to the gate electrodes. A first body region is exposed to a surface of a ... 08/17/06 - 20060180835 - Semiconductor component with integrated backup capacitance On embodiment of the invention provides a semiconductor component with at least one thin oxide transistor, the gate of which is directly connected to a first electrical potential by means of a connecting element. The connecting element contains a thermal desired breaking point. In order to realize an integrated backup ... 08/10/06 - 20060175640 - Semiconductor memory device, memory cell array, and method for fabricating the same A semiconductor memory device suitable for use in a memory cell array includes a solid electrolyte memory cell including: a first electrode device, a second electrode device, and a solid electrolyte material region between the first and second electrode devices. The solid electrolyte material region is materially cohesive, and the ... 08/03/06 - 20060170017 - Semiconductor device and manufacturing method thereof A method of manufacturing a semiconductor device includes forming a semiconductor layer containing a semiconductor material having a first oxide-generating Gibbs free energy required to become an oxide; forming a first material for a gate insulator on the semiconductor layer, said first material containing an element having a second oxide-generating ... 08/03/06 - 20060170016 - Asymmetric spacers and asymmetric source/drain extension layers A method of forming a semiconductor device is provided in which a substrate (102) is provided which has a gate dielectric layer (106) disposed thereon, and a gate electrode (116) having first and second sidewalls is formed over the gate dielectric layer. First (146) and second (150) extension spacer structures ... 07/27/06 - 20060163626 - High voltage transistor structure for semiconductor device A high voltage MOS transistor has a thermally-driven-in first doped region and a second doped region that form a double diffused drain structure. Boundaries of the first doped region are graded. A gate-side boundary of the first doped region extends laterally below part of the gate electrode. The second doped ... 07/27/06 - 20060163625 - Semiconductor layer and forming method thereof, and semiconductor device and manufacturing method thereof technical field The present invention relates to a semiconductor layer applicable to a hetero-junction bipolar transistor, a forming method thereof, and a semiconductor device and a manufacturing method thereof, for example. The semiconductor layer and the forming method thereof according to the present invention includes a first SiGe film or SiGeC film ... 07/27/06 - 20060163624 - Semiconductor device, and manufacturing method thereof The present invention provides a semiconductor device having a fully silicided gate electrode (full-silicide gate electrode) and a manufacturing method thereof, that has no problem of the increase in junction leak current, can increase a thickness of a metal silicide film formed on a source/drain region, and can form a ... 07/27/06 - 20060163623 - Semiconductor device and manufacturing method thereof A semiconductor device includes a semiconductor layer, an insulated-gate field effect transistor provided in the semiconductor layer, an etching stopper film provided above the insulated-gate field effect transistor, and an interlayer insulating layer provided above the etching stopper film; the insulated-gate field effect transistor including a gate insulating layer provided ... 07/20/06 - 20060157755 - Transistor of volatile memory device with gate dielectric structure capable of trapping charges and method for fabricating the same The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure ... 07/20/06 - 20060157754 - Semiconductor device including high-k insulating layer and method of manufacturing the same A semiconductor memory device a first dopant area and a second dopant area, the first dopant area and the second dopant area disposed in a semiconductor substrate, an insulating layer disposed in contact with the first dopant area and the second dopant area, the insulating layer including a material selected ... 07/20/06 - 20060157753 - Multi-bit nonvolatile memory devices and methods of manufacturing the same Multi-bit nonvolatile memory devices and related methods of manufacturing the same are described. In some multi-bit nonvolatile memory devices, a semiconductor substrate has a recessed region defined therein. An insulating layer, which can include an ONO layer, is configured to store data within programming regions therein, and covers a sidewall ... 07/20/06 - 20060157752 - Method of manufacturing semiconductor device having side wall spacers Gate insulating films 12A and 12B of different thickness are formed in element openings 16a and 16b in the isolation film 16 of a wafer 10. The gate insulating film 12B is the thinnest gate insulating film. A dummy insulating film having the same thickness as the thinnest gate insulating ... 07/20/06 - 20060157751 - Metal oxide semiconductor field effect transistor and method of fabricating the same There are provided a MOSFET and a method for fabricating the same. The MOSFET includes a semiconductor substrate, a germanium layer formed by implanting germanium (Ge) ions into the semiconductor substrate, an epitaxial layer doped with high concentration impurities over the germanium layer, a gate structure on the epitaxial layer, ... 07/20/06 - 20060157750 - Semiconductor device having etch-resistant l-shaped spacer and fabrication method thereof Provided is a semiconductor device having an etch-resistant L-shaped spacer and a fabrication method thereof. The semiconductor device comprises a semiconductor substrate, a gate insulating layer formed on the semiconductor substrate, a gate electrode formed on the gate insulating layer, an L-shaped lower spacer conformally formed on sidewalls of the ... 07/20/06 - 20060157749 - Fin-type semiconductor device with low contact resistance and its manufacture method A semiconductor device comprises a fin-type semiconductor region (fin) on a support substrate, having a pair of generally vertical side walls and an upper surface coupling the side walls; an insulated gate electrode structure traversing an intermediate portion of the fin and having side walls in conformity with the side ... 07/20/06 - 20060157748 - Metal junction diode and process A junction diode includes a substrate having first and second cathode regions separated by an anode region. Metal silicide layers contact the first and second cathode regions and the anode regions. The anode region has a doping concentration sufficient to create a depletion region in the anode region adjacent to ... 07/20/06 - 20060157747 - Forming field effect transistors from conductors A nanotube transistor, such as a carbon nanotube transistor, may be formed with a top gate electrode and a spaced source and drain. Conduction along the transistor from source to drain is controlled by the gate electrode. Underlying the gate electrode are at least two nanotubes. In some embodiments, the ... 06/29/06 - 20060138479 - Tensile strained substrate An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a ... 06/29/06 - 20060138478 - Semiconductor device and method of forming same A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a gate spacer disposed on both sidewalls of the gate pattern, and a fixed charge layer disposed in the semiconductor substrate below the gate spacer. Elements generating fixed charges are injected into the fixed charge layer. A layer ... 06/29/06 - 20060138477 - Asymmetric recessed gate mosfet and method for manufacturing the same Disclosed are an asymmetric recessed gate MOSFET, and a method for manufacturing the same. The asymmetric recessed gate MOSFET comprises: recess regions formed at a predetermined depth in a semiconductor; recessed gate electrodes formed at a predetermined height on a semiconductor substrate by gap-filling the recess regions, and misaligned with ... 06/29/06 - 20060138476 - Dc amplifier and semiconductor integrated circuit therefor A rectangular parallelepiped projecting portion 21 having a height of HB and a width of WB is formed on a silicon substrate, and a gate oxide film is formed on a part of the top surface and the side surface of the projecting portion 21. A source and a drain ... 06/29/06 - 20060138475 - Method of manufacturing a semiconductor device and semiconductor device obtained by means of such a method The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (1) and a semiconductor body (2) comprising a first (N-MOS)PET (3) with a first channel region (3A) and a first gate electrode (3B) which includes a first conductor and which is separated from the channel ... 06/22/06 - 20060131622 - Semiconductor device having a silicon layer in a gate electrode A CMOS device includes a silicon substrate, a gate insulating film, and a gate electrode including a silicon layer doped with boron and phosphorous, a tungsten nitride layer and a tungsten layer. A ratio of a maximum boron concentration to a minimum boron concentration in a boron concentration profile across ... 06/15/06 - 20060124975 - Dual work function gate in cmos device A transistor has a first silicon layer comprising a source region and a drain region separated by a channel region. A gate oxide is formed over the first silicon layer. A second silicon layer is formed over the gate oxide and comprises a dual work function gate. The dual work ... 05/25/06 - 20060108616 - High-voltage metal-oxide-semiconductor transistor A high-voltage metal-oxide-semiconductor (HV MOS) transistor is provided to form the decoder in a source driver of a display apparatus for substantially saving the layout area. The HV MOS transistor includes two doped regions with a first conductivity type disposed in a semiconductor substrate, and a gate region having a ... 05/11/06 - 20060097294 - Semiconductor device and method for fabricating the same Gate electrodes 5A through 5F are formed to have the same geometry, and protruding parts of the gate electrodes 5A through 5F extend across an isolation region onto impurity diffusion regions. The gate electrode 5B and P-type impurity diffusion regions 7B6 are connected through a shared contact 9A1 to a ... 05/11/06 - 20060097293 - Esd structure An IGFET that minimizes the effect of the dislocation at the edge of the device region by displacing the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation. This minimizes the lateral diffusion of the source and drain impurities and the ... 05/11/06 - 20060097292 - Semiconductor device A semiconductor device includes a second conductivity type layer selectively formed by changing impurity concentrations on a semiconductor substrate, a first conductivity type source region formed on the second conductivity type layer, a first conductivity type drain region formed on the second conductivity type layer apart from the first conductivity ... 05/04/06 - 20060091433 - Semiconductor integrated circuit device and manufacturing method thereof A semiconductor integrated circuit device includes a projected semiconductor layer formed at a part of the upper surface of a semiconductor substrate; a gate insulation film formed on a first side surface of the semiconductor layer; a gate electrode formed on the gate insulation film; a first insulation film formed ... 05/04/06 - 20060091432 - Damascene gate field effect transistor with an internal spacer structure A MOSFET is disclosed that comprises a channel between a source extension and a drain extension, a dielectric layer over the channel, a gate spacer structure formed on a peripheral portion of the dielectric layer, and a gate formed on a non-peripheral portion of the dielectric layer, with at least ... 04/20/06 - 20060081896 - Semiconductor device and method for forming the same The present invention disclosed herein is a semiconductor device and a method for forming the same. The semiconductor device includes a first semiconductor pattern defining an active region, second semiconductor patterns placed on the first semiconductor pattern apart from each other, an insulated gate electrode spaced apart from the second ... 04/20/06 - 20060081895 - Semiconductor device having fin transistor and planar transistor and associated methods of manufacture Disclosed is a fin transistor and a planar transistor and a method of forming the same. The fin transistor and the planar transistor are formed to have gate electrodes with similar thicknesses by selectively recessing a semiconductor substrate in a planar region where the planar transistor is formed. ... 04/20/06 - 20060081894 - Recessed drain extensions in transistor device A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate structure has a first sidewall and a second sidewall (59x). The method also forms ... 04/13/06 - 20060076586 - Virtual ground memory array and method therefor A virtual ground memory array (VGA) is formed by a storage layer over a substrate with a conductive layer over the storage layer. The conductive layer is opened according to a patterned photoresist layer. The openings are implanted to form source/drain lines in the substrate, then filled with a layer ... 04/06/06 - 20060071249 - Low noise field effect transistor An FET (field effect transistor) having source, drain and channel regions of a conductivity type in a semiconductor body of opposite conductivity type. The channel region is located at the lower extremity of the source and drain regions so as to be spaced from the surface of the semiconductor body ... 03/30/06 - 20060065914 - Structure and method for making strained channel field effect transistor using sacrificial spacer A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides ... 03/16/06 - 20060054944 - Semiconductor device and process for manufacturing the same The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3), the gate insulation film ... 03/09/06 - 20060049436 - Semiconductor component with a mos transistor The source area (3) is highly doped, like the channel area, for the same conductance type. The drain area (4) is doped for the opposite conductance type. This results in a saving of area since the source connection (S) can at the same time be used as the well connection ... 03/02/06 - 20060043435 - Nano-scaled gate structure with self-interconnect capabilities Gate conductors on an integrated circuit are formed with enlarged upper portions which are utilized to electrically connect the gate conductors with other devices. A semiconductor device comprises a gate conductor with an enlarged upper portion which electrically connects the gate conductor to a local diffusion region. Another semiconductor device ... 03/02/06 - 20060043434 - Semiconductor devices and methods of manufacture thereof A semiconductor device, for example a MOSFET or IGBT, includes a region (30, 36, 50) in the drain drift region (14) juxtaposed with its channel-accommodating region (15) and spaced from the drain contact region (14a) by means of an intermediate portion of the drift region. The region comprises alternating stripes ... 02/09/06 - 20060027842 - Control of liner thickness for improving thermal cycle reliability A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on ... 02/02/06 - 20060022229 - Semiconductor integrated circuit A semiconductor integrated circuit according to the present invention comprises an MOS substrate having a substrate region (MOS) and a source region separated from each other, a dummy MOS circuit substrate-separated from the MOS circuit and having a substrate region (dummy) and a source region (dummy) separated from each other, ... 02/02/06 - 20060022228 - Method of manufacturing silicon nitride film, method of manufacturing semiconductor device, and semiconductor device A method of manufacturing a silicon nitride film that forms a silicon nitride film on a surface of a substrate comprises sequentially repeating first through third steps. The first step includes feeding a first gas containing silicon and nitrogen to the surface of the substrate. The second step includes feeding ... 01/26/06 - 20060017079 - N-type transistor with antimony-doped ultra shallow source and drain We disclose a process for forming ultra shallow n+p junctions. The junction is formed by, for example, implanting 3E14 ions/cm2 of antimony ions at 5 keV into silicon. The silicon is pre-amorphized by a previous ion-implantation. The pre-amorphizing implant species may be germanium or arsenic. Germanium may be implanted at ... 01/12/06 - 20060006434 - Semiconductor device including insulated gate type transistor and insulated gate type capacitance, and method of manufacturing the same It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which ... 01/12/06 - 20060006433 - Electrical passivation of silicon-containing surfaces using organic layers Electrical structures and devices may be formed and include an organic passivating layer that is chemically bonded to a silicon-containing semiconductor material to improve the electrical properties of electrical devices. In different embodiments, the organic passivating layer may remain within finished devices to reduce dangling bonds, improve carrier lifetimes, decrease ... 01/12/06 - 20060006432 - Semiconductor devices, dc/dc converter and power supply A semiconductor device in which the self-turn-on phenomenon is prevented that can significantly improve power conversion efficiency. The semiconductor device is a system-in-package for power supply applications in which a high-side switch, a low-side switch, and two drivers are included in a single package. The device includes an auxiliary switch ... 01/12/06 - 20060006431 - Metal oxide semiconductor (mos) varactor A metal oxide semiconductor (MOS) varactor includes a first terminal and a second terminal, and the MOS varactor comprises a substrate; a deep well, formed on the substrate; and a first MOS device, formed on the deep well; wherein a gate of the first MOS device is coupled to the ... 01/05/06 - 20060001058 - Fin field effect transistor memory cell A fin field effect transistor memory cell having a first and a second source/drain region, a gate region, a semiconductor fin having a channel region between the first and the second source/drain region, a charge storage layer configured as a trapping layer arranged at least partly on the gate region, ... 12/29/05 - 20050285163 - Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of ... 12/29/05 - 20050285162 - Semiconductor devices having a stacked structure and methods of forming the same Methods of forming a semiconductor device having stacked structures include forming a first semiconductor structure on a substrate and forming a first interlayer insulating layer on the substrate. The first interlayer insulating layer has a substantially level upper face. A semiconductor layer is formed on the first interlayer insulating layer ... 12/29/05 - 20050285161 - Method of fabricating multi-gate transistor and multi-gate transistor fabricated thereby Provided are a method of fabricating an improved multi-gate transistor and a multi-gate transistor fabricated using the method, which can reproduce a profile of a gate electrode in a stable manner. The method includes forming an active pattern on a substrate, the active pattern having two or more surfaces on ... 12/29/05 - 20050285160 - Methods for forming semiconductor wires and resulting devices Methods for forming a wire from silicon or other semiconductor material are disclosed. Also disclosed are various wire structures and devices including these wire structures (e.g., transistors). A wire structure may comprise a wire that extends between two spaced-apart anchors, with each anchor affixed to an underlying substrate and the ... 12/29/05 - 20050285159 - Compressive sige <110> growth and structure of mosfet devices A structure for conducting carriers and method for forming is described incorporating a single crystal substrate of Si or SiGe having an upper surface in the <110> and a psuedomorphic or epitaxial layer of SiGe having a concentration of Ge different than the substrate whereby the psedomorphic layer is under ... 12/22/05 - 20050280053 - Semiconductor device with diagonal gate signal distribution runner A semiconductor device includes a device body, a gate pad and a gate signal distribution runner. The device body includes a plurality of parallel cells and the gate pad is located on a top surface of the device body adjacent a corner of the device body. The gate signal distribution ... 12/22/05 - 20050280052 - Field effect transistor with local source/drain insulation and associated method of production A field-effect transistor (FET) with local source-drain insulation is described. The FET includes a semiconductor substrate, source and drain depressions, a depression insulation layer, an electrically conductive filling layer, a gate dielectric, and a gate layer. The depression insulation layer is formed at least in bottom regions of the source ... 12/15/05 - 20050274992 - Method of fabricating a tunneling nanotube field effect transistor A method of fabricating a tunneling nanotube field effect transistor includes forming in a nanotube an n-doped region and a p-doped region which are separated by an undoped channel region of the transistor. Electrical contacts are provided for the doped regions and a gate electrode that is formed upon a ... 12/08/05 - 20050269602 - Semiconductor device and method of manufacturing the same The inner wall of a trench formed in an element isolation region on a silicon substrate is oxidized to form an inner wall oxide film. The inner wall oxide film is subjected to two nitridation steps including thermal nitridation and radical nitridation. A first nitride layer is formed by the ... 12/01/05 - 20050263803 - Semiconductor device includes gate insulating film having a high dielectric constant A semiconductor device comprising a semiconductor substrate and a MOSFET provided on the semiconductor substrate, the MOSFET including a gate insulating film and a gate electrode provided on the gate insulating film, wherein the gate insulating film has a higher dielectric constant in a side contacting the semiconductor substrate than ... 12/01/05 - 20050263802 - Semiconductor device A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high dielectric constant film 108a and a polycrystalline silicon ... 12/01/05 - 20050263801 - Phase-change memory device having a barrier layer and manufacturing method A semiconductor device comprises a semiconductor substrate having an isolation region that defines an active region. The active region has a planar surface and a non-planar surface that extends from the planar surface. The device further includes a gate dielectric layer covering the non-planar surface and a first gate electrode ... 11/24/05 - 20050258461 - High-voltage ldmosfet and applications therefor in standard cmos A high-voltage LDMOSFET includes a semiconductor substrate, in which a gate well is formed. A source well and a drain well are formed on either side of the gate well, and include insulating regions within them that do not reach the full depth. An insulating layer is disposed on the ... 11/24/05 - 20050258460 - Fabrication methods for compressive strained-silicon and transistors using the same Fabrication methods for compressive strained-silicon by ion implantation. Ions are implanted into a silicon-containing substrate and high temperature processing converts the vicinity of the ion-contained region into strained-silicon. Transistors fabricated by the method are also provided. ... 11/17/05 - 20050253175 - Mos-transistor on soi substrate with source via In an inventive MOS transistor having a source region, a drain region and a channel region, which are formed in a semiconductor layer of an SOI substrate, which has a semiconductor substrate below the semiconductor layer and an isolation layer between semiconductor layer and semiconductor substrate, the drain or source ... 11/17/05 - 20050253174 - Mos transistor and a semiconductor integrated circuit apparatus having the same A MOS transistor comprises: a first conduction type region; a second conduction type drain region formed on the outermost layer portion of the first conduction type region; a second conduction type source region formed on the outermost layer portion of the first conduction type region with a channel region provided ... 11/03/05 - 20050242379 - Optical properties restoration apparatus, the restoration method, and an optical system used in the apparatus The objectives of the present invention are to prevent or inhibit the deterioration of optical systems that determine the longevity of an optical apparatus which delivers effects such as light transmission, diffraction, reflection, spectrum generation, and interference, and these combinations, and by so doing, decrease the frequency of maintenance operations ... 10/20/05 - 20050230718 - Method of manufacturing a semiconductor device A semiconductor device design is disclosed. An example semiconductor device comprises a semiconductor substrate comprising an active region and a non-active region. A first gate electrode comprising a gate oxide, a first conducting layer pattern, and an insulating layer that is configured to function as a normal gate electrode is ... 10/20/05 - 20050230717 - Semiconductor device of transistor structure having strained semiconductor layer The semiconductor device comprises a p type Si substrate 10; a SiGe buffer layer 12 formed on the p type Si substrate 10 and having element isolation grooves 16 formed in the surface, which define an active region 18; a SiGe regrown buffer layer 20 formed on the SiGe buffer ... 10/20/05 - 20050230716 - Semiconductor integrated circuit equipment and its manufacture method The object of the present invention is to suppress the increase of the contact resistance at the interface between the metal layer and the silicon plug in the wiring structure in which a metal layer is formed on and connected to a silicon plug. For its achievement, a lower semiconductor ... 10/13/05 - 20050224848 - Semiconductor device and method for manufacturing semiconductor device An active groove filled region 23a is kept at a portion of an active groove 22a connecting to an embedded region 24 positioned below a gate groove 83. The active groove filled region 23a connects to a source electrode film 58a so as to have the same electric potential as ... 10/13/05 - 20050224847 - Semiconductor memory device and manufacturing method for the same The present invention provides a semiconductor memory device including: a semiconductor substrate of a first conductivity type; and a memory cell including: (i) a columnar semiconductor portion formed on the substrate, (ii) at least two charge-storage layers formed around a periphery of the columnar semiconductor portion and divided in a ... 10/13/05 - 20050224846 - Semiconductor device and method of manufacturing the same A semiconductor device includes a semiconductor substrate, a T-shaped gate electrode, a moisture-proof insulating film, and an interlayer dielectric film. The T-shaped gate electrode has a leg portion joined to the semiconductor substrate and an overhanging head portion spaced from the semiconductor substrate. The T-shaped gate electrode includes a gate ... 10/06/05 - 20050218435 - Semiconductor integrated circuit device and production method thereof A CVD device (100) used for depositing a silicon nitride has a structure in which a hot wall furnace (103) for thermally degrading a source gas and a chamber (101) for forming a film over a surface of a wafer (1) are separated from each other. The hot wall furnace ... 10/06/05 - 20050218434 - Transistor having asymmetric channel region, semiconductor device including the same, and method of fabricating semiconductor device including the same According to embodiments of the invention, a transistor includes a semiconductor substrate having an active region. A channel trench is disposed to cross the active region. A gate insulating layer covers an inner wall of the channel trench. A gate pattern is disposed to fill the channel trench and to ... 09/29/05 - 20050212018 - Conductive lines buried in insulating areas An integrated circuit comprising a semiconductor substrate in which active areas surround or are surrounded by hollowings filled with an insulator, and in which a conductive region is embedded in the insulator of at least one hollowing, the conductive region being connected to a reference voltage and being connected at ... 09/22/05 - 20050205900 - Semiconductor constructions and transistor gates One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewall edge comprising a first-layer-defined ... 09/22/05 - 20050205899 - Method for fabricating semiconductor device A method for fabricating a semiconductor device is provided. The method comprises: providing a substrate; forming a gate structure on the substrate, the gate structure including a gate dielectric layer on the substrate and a gate conductive layer on the gate dielectric layer; forming an oxide layer conformally covering the ... 09/15/05 - 20050199920 - Fin field effect transistors with low resistance contact structures and methods of manufacturing the same Fin FET semiconductor devices are provided which include a substrate, an active pattern that protrudes vertically from the substrate and that extends laterally in a first direction, a device isolation layer which has a top surface that is lower than a top surface of the active pattern, a gate structure ... 09/15/05 - 20050199919 - Semiconductor integrated circuit and method for manufacturing the same Upstanding thin-film channel regions 5 having different heights are formed between source regions 7 and drain regions 8 of MOS transistors, respectively. ... 09/08/05 - 20050194622 - Nonvolatile capacitor of a semiconductor device, semiconductor memory device including the capacitor, and method of operating the same In a capacitor of a semiconductor device, a semiconductor memory device including the capacitor, and a method of operating the semiconductor memory device, the capacitor includes a lower electrode, a dielectric layer stacked on the lower electrode, the dielectric layer including a phase-transition layer capable of exhibiting two different resistance ... 09/01/05 - 20050189572 - Semiconductor device and method of manufacturing the same In a semiconductor device, pining regions 105 are disposed along the junction portion of a drain region 102 and a channel forming region 106 locally in a channel width direction. With this structure, because the spread of a depletion layer from a drain side is restrained by the pining regions ... 08/25/05 - 20050184319 - Triple-gate mosfet transistor and methods for fabricating the same Transistors and fabrication methods are presented in which a semiconductor body is deposited in a cavity of a temporary form structure above a semiconductor starting structure. The formed semiconductor body can be epitaxial silicon deposited in the form cavity over a silicon substrate, and includes three body portions, two of ... 08/25/05 - 20050184318 - Power mosfet and method for forming same using a self-aligned body implant A method for making a power MOSFET includes forming a trench in a semiconductor layer, forming a gate dielectric layer lining the trench, forming a gate conducting layer in a lower portion of the trench, and forming a dielectric layer to fill an upper portion of the trench. Portions of ... 08/18/05 - 20050179069 - Semiconductor device and method of manufacturing same A semiconductor device is produced by forming a gate oxide film on a silicon substrate, forming a gate electrode on the gate oxide film, forming a nitrogen-containing oxide film on the silicon substrate and gate electrode in an N2O gas or an NO gas, forming a BPSG film on the ... 08/18/05 - 20050179068 - Integrated semiconductor circuit having a logic and power metallization without intermetal dielectric An integrated semiconductor circuit having a first and a second portion of a substrate, in which a power semiconductor circuit structure and a logic circuit structure are respectively formed. The metallization having a power metal layer and an in relative terms thinner logic metal layer, the two metal layers being ... 08/18/05 - 20050179067 - Semiconductor device and fabricating method thereof A semiconductor device and fabricating method thereof in which a drain-source breakdown voltage is improved by additional ion implantation into a lightly doped drain are disclosed. An example method of fabricating a semiconductor device includes forming a gate having a gate oxide underneath on a semiconductor substrate, forming a first ... 08/18/05 - 20050179066 - Fabricating strained channel epitaxial source/drain transistors The mobility of carriers may be increased in strained channel epitaxial source/drain transistors. Doped silicon material may be blanket deposited after removing ion implanted source/drain regions. The blanket deposition forms amorphous films over non-source/drain areas and crystalline films in source/drain regions. By using an etch which is selective to amorphous ... 08/18/05 - 20050179065 - Isfet using pbtio3 as sensing film A PbTiO3/SiO2-gated ISFET device comprising a PbTiO3 thin film as H+-sensing film, and a method of forming the same. The PbTiO3 thin film is formed through a sol-gel process which offers many advantages, such as, low processing temperature, easy control of the composition of the film and easy coating over ... 08/11/05 - 20050173741 - Top drain mosfet with thickened oxide at trench top A top drain MOSFET has active trenches with an enlarged width at the top of each trench which has a thicker oxide than the gate oxide adjacent the channel region. The thicker oxide at the top of the trench reduces Qgd. The thicker oxide at the top of the active ... 08/11/05 - 20050173740 - Multi-gate transistor formed with active patterns of uniform critical dimension For fabricating a multi-gate transistor, at least one active pattern having uniform critical dimension is formed. Epitaxy structures are grown from exposed portions of the active pattern. A channel region of the transistor is formed from at least two surfaces of the active pattern. Source and drain are formed using ... 08/04/05 - 20050167706 - Mos transistor and method for producing a mos transistor structure A MOS transistor, and a method for producing the same, is provided with a source region, a gate-region, a drain region, and a drift region in an SOI wafer. The SOI-wafer has a carrier layer, which carries an insulating intermediate layer, and whereby the insulating intermediate layer carries an active ... 07/28/05 - 20050161711 - High performance fet devices and methods thereof Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to ... 07/21/05 - 20050156211 - Semiconductor device and method for producing the same A semiconductor device of the present invention includes a semiconductor substrate including an active region and an isolating region provided so as to enclose the active region; a capacitance insulating film that is provided on the active region and is in contact with the isolating region; an upper electrode provided ... 07/21/05 - 20050156210 - Methods of forming reacted conductive gate electrodes A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion ... 07/21/05 - 20050156209 - Semiconductor device and process for producing the same To provide a semiconductor device that can effectively suppress the short channel effect without deterioration of carrier migration, an impurity ion is added from a direction of the <110> axis with respect to a silicon substrate on forming a punch through stopper under the gate electrode. In this invention, because ... 07/21/05 - 20050156208 - Device having multiple silicide types and a method for its fabrication Provided are a semiconductor device and a method for its fabrication. In one example, the semiconductor device includes an active region formed on a substrate using a first silicide type and another active region formed on the substrate using another silicide type. The two silicide types differ and at least ... 07/21/05 - 20050156207 - Examination apparatus for biological sample and chemical sample A wireless sensor chip suitable for the compact, high-sensitive, and low-cost examination apparatus for easily examining a biological material such as gene at low cost is provided. A sensor chip is formed on an SOI substrate, and an n type semiconductor layer on which a pMOS transistor is formed and ... 07/21/05 - 20050156206 - High photosensitivity cmos image sensor pixel architecture The photosensitive volume of a pixel is extended beyond the photodiode region, which allows the pixel sensitivity to be relatively independent of the photodiode region. In an example embodiment, the photosensitive volume can be maximized by using a CMOS process to remove heavily doped material (e.g., as from in a ... 07/14/05 - 20050151174 - Semiconductor device and fabricating method thereof A semiconductor device and fabrication method thereof are disclosed. An example semiconductor device includes a semiconductor substrate having a device isolation area defining an active area; a gate oxide layer formed on the active area of the substrate; a gate on the gate oxide layer; a spacer provided to a ... 07/14/05 - 20050151173 - Semiconductor device and methods of manufacturing the same A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by ... 07/14/05 - 20050151172 - Semiconductor device and its manufacturing method A semiconductor device includes a first insulating layer, a semiconductor layer formed on the first insulating layer, a second insulating layer on a part of the semiconductor layer, and a gate electrode formed on the semiconductor layer through the second insulating layer. The semiconductor layer includes a low concentration region ... 07/07/05 - 20050145899 - Manufacturing method of semiconductor device After deposition of a conductor film made of titanium tungsten over a main surface of a semiconductor substrate formed with grooves, an initial conductor film made of aluminium is further deposited. Subsequently, the conductor film is made to reflow and run into the grooves. Thereafter, while heating, further conductor films ... 07/07/05 - 20050145898 - Non-volatile semiconductor memory device and process for fabricating the same A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive ... 07/07/05 - 20050145897 - Manufacturing method of semiconductor device A method of manufacture of a semiconductor device includes forming a gate insulating film and a gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride ... 07/07/05 - 20050145896 - Memory device and method of manufacturing the same A memory device and a method of fabricating the same are provided. The method includes forming a gate stack on a semiconductor substrate and partially exposing upper end portions of the semiconductor substrate by etching the gate stack to form a gate stack structure, and implanting a dopant into the ... 07/07/05 - 20050145895 - Amplifiers using gated diodes A circuit comprises a control line and a two terminal semiconductor device having first and second terminals. The first terminal is coupled to a signal line, and the second terminal is coupled to the control line. The two terminal semiconductor device is adapted to have a capacitance when a voltage ... 07/07/05 - 20050145894 - Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films The present invention relates to the deposition of a layer above a transistor structure, causing crystalline stress within the transistor, and resulting in increased performance. The stress layer may be formed above a plurality of transistors formed on a substrate, or above a plurality of selected transistors. ... 07/07/05 - 20050145893 - Methods for fabricating metal gate structures Methods of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a gate dielectric layer, and then laser annealing the substrate. ... 07/07/05 - 20050145892 - Mask, semiconductor device manufacturing method, and semiconductor device A mask capable of improving superimposing accuracy of patterns drawn on a plurality of masks, a production method of a semiconductor device capable of improving a yield of semiconductor devices, and a semiconductor device wherein a pattern can be made finer are provided. A mask including a plurality of mask ... 07/07/05 - 20050145891 - Semiconductor device provided with matrix type current load driving circuits, and driving method thereof A current load cell (113, 114) includes a current load driving circuit which is provided with a transistor (115) connected in series with a current load (122) between first and second power supplies (109, 110); a capacitance (116) connected between the control terminal of the transistor (115) and the first ... 06/30/05 - 20050139876 - Transistors and manufacturing methods thereof Transistors and manufacturing methods thereof are disclosed. An example transistor includes a semiconductor substrate divided into device isolation regions and a device active region. The example transistor includes a gate insulating film formed in the active region of the semiconductor substrate, a gate formed on the gate insulating film, a ... 06/30/05 - 20050139875 - Mos transistors and methods of manufacturing the same MOS transistors having a low junction capacitance between their halo regions and their source/drain extension regions and methods for manufacturing the same are disclosed. A disclosed MOS transistor includes: a semiconductor substrate of a first conductivity type; a gate insulating layer pattern and a gate on an active region of ... 06/30/05 - 20050139874 - Test patterns for semiconductor devices and methods of fabricating the same Test patterns for semiconductor devices and method for fabricating test patterns are disclosed. In a disclosed method, one well mask having multiple intervals of different widths is used to evaluate a well-isolation characteristic and to find an optimal sizing factor in an early stage of development. A disclosed test mask ... 06/30/05 - 20050139873 - Semiconductor device and method of manufacturing the same A semiconductor device comprises a plurality of unit cells, each comprising a vertical metal oxide semiconductor field effect transistor (MOSFET). The unit cell includes a first source region formed in a first base region, a second source region formed in the first base region and separated from the first source ... 06/30/05 - 20050139872 - Drive current improvement from recessed sige incorporation close to gate A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral ... 06/23/05 - 20050133836 - Asymmetric mos transistor with trench-type gate a A MOS (metal oxide semiconductor) transistor with a trench-type gate is fabricated with a channel stopping region for forming an asymmetric channel region for reducing short channel effects. For example in fabricating an N-channel MOS transistor, a gate structure is formed within a trench that is within a P-well. ... 06/23/05 - 20050133835 - Reduced hydrogen sidewall spacer oxide An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a spacer oxide layer 90 with a hydrogen content of ... 06/23/05 - 20050133834 - Semiconductor device and fabrication method thereof A semiconductor device of this invention includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a pair of source and drain electrodes respectively formed in regions of the semiconductor substrate situated on opposite sides of the gate electrode in a plan view; and a germanium-containing channel layer ... 06/23/05 - 20050133833 - Metal oxide semiconductor device and fabricating method thereof A method of fabricating an MOS device is described. A substrate doped a first type dopant is provided as a drain. A first type epitaxial layer is formed on the substrate and is patterned with a trench to form several islands. A gate dielectric layer is than formed on the ... 06/23/05 - 20050133832 - Methods for selective deposition to improve selectivity Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area ... 06/23/05 - 20050133831 - Body contact formation in partially depleted silicon on insulator device An SOI device (100) has a gate electrode with one or more additional gate regions (120), and oxygen or halogen ions (128) under the additional gate regions (120). The oxygen or halogen ions (128) form thicker gate oxide regions or shallow trench isolation regions. ... 06/23/05 - 20050133830 - Method for fabricating a recessed channel filed effect transistor (fet) device A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a ... 06/16/05 - 20050127412 - Self-aligned double gate mosfet with separate gates A structure and method of manufacturing a double-gate integrated circuit which includes forming a laminated structure having a channel layer and first insulating layers on each side of the channel layer, forming openings in the laminated structure, forming drain and source regions in the openings, removing portions of the laminated ... 06/16/05 - 20050127411 - Mos type variable capacitance device An n-well is formed in a p-type semiconductor substrate. A gate insulative film is formed to the p-type semiconductor substrate and the n-well, and a gate electrode is formed on the gate insulative film. A source layer selectively diffused with n-type impurities at high concentration is formed adjacent to the ... 06/16/05 - 20050127410 - Method of making a mos transistor A method of making a MOS transistor is disclosed. The disclosed techniques can completely transform a polysilicon gate electrode into a metal silicide electrode through a brief thermal treatment process by extending the contact area between the polysilicide gate electrode and a metal layer prior to a formation of a ... 06/16/05 - 20050127409 - System for high-precision double-diffused mos transistors The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor ... 06/16/05 - 20050127408 - Ultra-thin si channel cmos with improved series resistance Thin silicon channel SOI devices provide the advantage of sharper sub-threshold slope, high mobility, and better short-channel effect control but exhibit a typical disadvantage of increased series resistance. This high series resistance is avoided by using a raised source-drain (RSD), and expanding the source drain on the pFET transistor in ... 06/09/05 - 20050121706 - Semiconductor nano-rod devices In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing ... 06/09/05 - 20050121705 - Method and apparatus for fabricating semiconductor device A method for fabricating a semiconductor device, wherein a BTBAS—SiN film and an oxide film formed on a reverse-surface side of a semiconductor substrate at the same time as the formation of a BTBAS—SiN film for a side wall or a liner and an oxide film for an offset spacer ... 06/09/05 - 20050121704 - Semiconductor device and method of manufacturing the same Provided is a semiconductor device including a semiconductor substrate which includes a first semiconductor layer of a first conductivity and a pair of second semiconductor layers disposed on the first semiconductor layer and spaced apart from each other to form a trench therebetween, wherein the second semiconductor layer includes a ... 06/09/05 - 20050121703 - Semiconductor device and method for manufacturing the same Disclosed is a semiconductor device comprising an underlying insulating film having a depression, a semiconductor structure which includes a first semiconductor portion having a portion formed on the underlying insulating film and a first overlap portion which overlaps the depression, a second semiconductor portion having a portion formed on the ... 06/09/05 - 20050121702 - Modulated trigger device An integrated circuit structure, a trigger device and a method of electrostatic discharge protection, the integrated circuit structure including: a substrate having a top surface defining a horizontal direction, the substrate of a first dopant type; a first horizontal layer in the substrate, the first layer of a second dopant ... 06/02/05 - 20050116268 - Semiconductor device A semiconductor device of the generation with the minimum processing dimensions of 90 nm, or later, wherein variation of processing dimensions of gate electrodes in a logic block and a power source noise are suppressed; wherein a gate electrode formed to have a comb-shaped pattern is formed on a normal ... 06/02/05 - 20050116267 - Mos transistor device The invention relates to a MOS transistor device of the trench type, in which, in a semiconductor region of a first conductivity type, within a deep gate trench extending in the vertical direction of the semiconductor region, a vertical gate electrode and a gate oxide with a field plate step ... 06/02/05 - 20050116266 - Method of producing insulator thin film, insulator thin film, method of manufacturing semiconductor device, and semiconductor device A method of producing an insulator thin film, for forming a thin film on a substrate by use of the atomic layer deposition process, includes a first step of forming a silicon atomic layer on the substrate and forming an oxygen atomic layer on the silicon atomic layer, and a ... 06/02/05 - 20050116265 - Semiconductor device In a semiconductor device in which high voltage MOS transistors and low voltage MOS transistors are mixedly mounted, a process is simplified and miniaturization thereof is achieved, without causing a parasitic transistor operation. An active region doped with a low impurity concentration of an impurity is formed in a channel ... ### FreshPatents.com Support - Terms & Conditions |