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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode)

Having Insulated Electrode (e.g., Mosfet, Mos Diode)

Having Insulated Electrode (e.g., Mosfet, Mos Diode) patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

11/27/14 - 20140346573 - Semiconductor device including embedded crystalline back-gate bias planes, related design structure and method of fabrication
A method of forming a semiconductor device is disclosed. The method includes forming a first dielectric layer on a substrate; forming a set of bias lines on the first dielectric layer; covering the set of bias lines with a second dielectric layer; forming a semiconductor layer on the second dielectric...

11/27/14 - 20140346574 - Asymmetric finfet semiconductor devices and methods for fabricating the same
Asymmetric FinFET devices and methods for fabricating such devices are provided. In one embodiment, a method includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon and depositing a conformal liner over the fin structures. A first portion of the conformal liner is removed, leaving a first...

11/27/14 - 20140346575 - Semiconductor device with self-aligned contact and method of manufacturing the same
A semiconductor device with a self-aligned contact and a method of manufacturing the same, wherein the method comprises the step of forming a 1st dielectric layer on gate structures, form a self-aligned contact trench between two gate structures, forming an 2nd dielectric layer on the 1st dielectric layer and in...

11/27/14 - 20140346576 - Mosfets with multiple dislocation planes
A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET). The Method includes performing an implantation to form a pre-amorphization implantation (PAI) region adjacent to a gate electrode of the MOSFET, forming a strained capping layer over the PAI region, and performing an annealing on the strained capping layer and the...

11/27/14 - 20140346577 - Electronic device with asymmetric gate strain
The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain can be obtained through non symmetric placement of stress inducing structures as part of the gate electrode....

11/20/14 - 20140339610 - Finfet device and method of fabrication
Embodiments of the present invention provide a novel method and structure for forming finFET structures that comprise standard cells. An H-shaped cut mask is used to reduce the number of fins that need to be removed, hence increasing the fin efficiency....

11/20/14 - 20140339611 - Stacked semiconductor nanowires with tunnel spacers
A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating...

11/20/14 - 20140339612 - Using sacrificial oxide layer for gate length tuning and resulting device
Methods for controlling the length of a replacement metal gate to a designed target gate length and the resulting device are disclosed. Embodiments may include removing a dummy gate from above a substrate forming a cavity, wherein side surfaces of the cavity are lined with an oxidized spacer layer and...

11/20/14 - 20140339613 - Semiconductor device and method of manufacturing same
In one embodiment, a semiconductor device includes a semiconductor substrate, and a gate insulator arranged on the semiconductor substrate. The device further includes a gate electrode including a semiconductor layer and a metal layer which are sequentially arranged on the gate insulator. The device further includes a contact plug arranged...

11/13/14 - 20140332859 - Self-aligned wrapped-around structure
An embodiment vertical wrapped-around structure and method of making. An embodiment method of making a self-aligned vertical structure-all-around device including forming a spacer around an exposed portion of a semiconductor column projecting from a structure layer, forming a photoresist over a protected portion of the structure layer and a first...

11/13/14 - 20140332860 - Stacked carbon-based fets
Methods and systems for forming stacked transistors. Such methods include forming a lower channel layer on a substrate; forming a pair of vertically aligned gate regions over the lower channel layer; forming a pair of vertically aligned source regions and a pair of vertically aligned drain regions on the lower...

11/13/14 - 20140332861 - Fin structure with varying isolation thickness
Semiconductor fins having isolation regions of different thicknesses on the same integrated circuit are disclosed. Nitride spacers protect the lower portion of some fins, while other fins do not have spacers on the lower portion. The exposed lower portion of the fins are oxidized to provide isolation regions of different...

11/13/14 - 20140332862 - Stacked carbon-based fets
Stacked transistor devices include a lower channel layer formed on a substrate; a pair of vertically aligned source regions formed over the lower channel layer, where the pair of source regions are separated by an insulator; a pair of vertically aligned drain regions formed on the lower channel layer, where...

11/13/14 - 20140332863 - Semiconductor device and method of manufacturing the same
Provided are a semiconductor device and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an active fin on a substrate; oxidizing a portion of the active fin to form an insulating pattern between the active fin and the substrate; forming a first gate...

11/13/14 - 20140332864 - Method for providing a gate metal layer of a transistor device and associated transistor
A method includes providing a dummy gate structure on a substrate. The dummy gate structure includes a gate dielectric layer and a dummy gate electrode layer, and is laterally defined by inner sidewalls of a set of spacers. The method also includes laterally embedding the dummy gate structure, removing the...

11/13/14 - 20140332865 - Semiconductor device
A semiconductor device includes a substrate having an edge, a semiconductor layer provided on a substrate, an electrode pad provided on the semiconductor layer, an inorganic insulating film having a first opening through which an upper surface of the electrode pad is exposed, and a resin film provided on the...

11/13/14 - 20140332866 - Semiconductor device
A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface...

11/13/14 - 20140332867 - Semiconductor device and manufacturing method thereof
It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is...

11/06/14 - 20140327054 - Raised source/drain and gate portion with dielectric spacer or air gap spacer
A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes epitaxial raised source/drain (RSD) regions formed on the surface of a semiconductor substrate through selective epitaxial growth. In one embodiment, the faceted side portions of the RSD regions are utilized to form cavity regions which...

11/06/14 - 20140327055 - Replacement gate process and device manufactured using the same
A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard...

11/06/14 - 20140327056 - Semiconductor device having contact plug and method of manufacturing the same
The device further comprises a contact hole extending through the interlayer dielectric layer and a contact plug having an upper surface and electrically connecting to the substrate in the contact hole. The upper surface of the contact plug has a second height lower than the first height. A spacer is...

11/06/14 - 20140327057 - Power semiconductor device with a double metal contact
A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof....

11/06/14 - 20140327058 - Self-aligned contacts for replacement metal gate transistors
Embodiments of the invention include methods of forming gate caps. Embodiments may include providing a semiconductor device including a gate on a semiconductor substrate and a source/drain region on the semiconductor substrate adjacent to the gate, forming a blocking region, a top surface of which extends above a top surface...

10/30/14 - 20140319586 - Photolithographic, thickness non-uniformity, compensation features for optical photolithographic semiconductor structure formation
A semiconductor structure having a substrate; an active device formed in an active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region between a pair of electrical contacts; and a photolithographic, thickness non-uniformity, compensation feature, disposed...

10/30/14 - 20140319587 - Through-substrate vias and methods for forming the same
A device includes a semiconductor substrate and a Metal-Oxide-Semiconductor (MOS) transistor. The MOS transistor includes a gate electrode over the semiconductor substrate, and a source/drain region on a side of the gate electrode. A source/drain contact plug includes a lower portion and an upper portion over the lower portion, wherein...

10/23/14 - 20140312393 - Fin-fet transistor with punchthrough barrier and leakage protection regions
A method of forming a field effect transistor includes forming a punchthrough region having a first conductivity type in a substrate, forming an epitaxial layer having the first conductivity type on the substrate, patterning the epitaxial layer to form a fin that protrudes from the substrate, forming a dummy gate...

10/23/14 - 20140312394 - Semiconductor device including a material to absorb thermal energy
A semiconductor device includes a semiconductor chip and a first material including molecules that are configured to absorb thermal energy by reversibly changing a spatial molecular structure of the molecules....

10/23/14 - 20140312395 - Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact
A photo-patternable dielectric material is provided to a structure which includes a substrate having at least one gate structure. The photo-patternable dielectric material is then patterned forming a plurality of sacrificial contact structures adjacent the at least one gate structure. A planarized middle-of-the-line dielectric material is then provided in which...

10/23/14 - 20140312396 - Split multi-gate field-effect transistor
A semiconductor device based on split multi-gate field-effect transistor radio frequency devices is provided. The semiconductor device includes a substrate and a gate structure above the substrate and orthogonal to a channel axis. The semiconductor device also includes a semiconductor fin structure above the substrate along the channel axis. The...

10/23/14 - 20140312397 - Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact
A photo-patternable dielectric material is provided to a structure which includes a substrate having at least one gate structure. The photo-patternable dielectric material is then patterned forming a plurality of sacrificial contact structures adjacent the at least one gate structure. A planarized middle-of-the-line dielectric material is then provided in which...

10/23/14 - 20140312398 - Recessing sti to increase fin height in fin-first process
A method includes forming a gate stack over top surfaces of a semiconductor strip and insulation regions on opposite sides of the semiconductor strip. The insulation regions include first portions overlapped by the gate stack, and second portions misaligned from the gate stack. An end portion of the semiconductor strip...

10/23/14 - 20140312399 - Semiconductor device and method of manufacturing the same
A gate insulating film of a conventional semiconductor device is subjected to dielectric breakdown at a low electric field strength and thus its service life is short. This is because since the size of the asperity of at least one of a semiconductor layer-side interface and an electrode-side interface is...

10/16/14 - 20140306271 - Unltra-shallow junction semiconductor field-effect transistor and method of making
An ultra-shallow junction semiconductor field-effect transistor and its methods of making are disclosed. In the present disclosure, a mixture film is formed on a semiconductor substrate with a gate structure formed thereon using a physical vapor deposition (PVD) process, which employs a mixture of metal and semiconductor dopants as a...

10/16/14 - 20140306272 - Method of forming a finfet structure
A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed...

10/16/14 - 20140306273 - Structure of metal gate structure and manufacturing method of the same
A manufacturing method of a metal gate structure is provided. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate...

10/16/14 - 20140306274 - Self-aligned structure for bulk finfet
A FinFET structure which includes a bulk semiconductor substrate; semiconductor fins extending from the bulk semiconductor substrate, each of the semiconductor fins having a top portion and a bottom portion such that the bottom portion of the semiconductor fins is doped and the top portion of the semiconductor fins is...

10/16/14 - 20140306275 - Semiconductor device and method of manufacturing semiconductor device
A semiconductor device is disclosed. The semiconductor device includes an insulating layer formed selectively on a semiconductor layer; a lower electrode, formed on the insulating layer, having an end portion at a position spaced apart by a predetermined distance inward from a periphery of the insulating layer; a dielectric film...

10/09/14 - 20140299923 - Field effect transistor
A field effect transistor includes a semiconductor substrate having a protrusion with at least one inclined surface, a gate insulator disposed at least on a portion of the inclined surface, and a gate conductor disposed on the gate insulator, wherein the semiconductor substrate comprises doped regions sandwiching a channel region,...

10/09/14 - 20140299924 - Formation of the dielectric cap layer for a replacement gate structure
Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a...

10/02/14 - 20140291734 - Thin channel mosfet with silicide local interconnect
A semiconductor structure and method of manufacturing the same are provided. The semiconductor structure includes a semiconductor substrate having an isolated area comprising a first region and a second region. A first raised RSD region is formed in the first region and a second RSD region is formed in the...

10/02/14 - 20140291735 - Double patterning via triangular shaped sidewall spacers
An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers for mandrels of a filler material substantially different...

10/02/14 - 20140291736 - Semiconductor device and method of manufacturing the same
In one embodiment, a first main terminal region of a first conductivity type and a second main terminal region of a second conductivity type, which is an opposite conductivity type of the first conductivity type, formed in the semiconductor substrate so as to sandwich a gate electrode, a diffusion layer...

10/02/14 - 20140291737 - Transistor architecture having extended recessed spacer and source/drain regions and method of making same
Techniques are disclosed for forming transistor architectures having extended recessed spacer and source/drain (S/D) regions. In some embodiments, a recess can be formed, for example, in the top of a fin of a fin-based field-effect transistor (finFET), such that the recess allows for forming extended recessed spacers and S/D regions...

10/02/14 - 20140291738 - Semiconductor device and manufacturing method therefor
A semiconductor electronic device structure includes an active area array disposed in a substrate, an isolation structure, a plurality of recessed gate structures, a plurality of word lines, and a plurality of bit lines. The active area array a plurality of active area columns and a plurality of active area...

10/02/14 - 20140291739 - Junction-less transistor having reverse polarity structure
A junction-less transistor having an reverse polarity structure includes a substrate, a semiconductor body, a gate and a gate insulation layer. The substrate has a first polarity. The semiconductor body is disposed on the substrate, and includes a drain, a source and a channel section connected between the drain and...

10/02/14 - 20140291740 - Perforated channel field effect transistor
A device including a plurality of perforations to a semiconductor channel is provided. The device includes a semiconductor structure forming the semiconductor channel. Additionally, the device includes a source contact, a drain contact, and a gate contact to the semiconductor channel. The plurality of perforations can be located in the...

10/02/14 - 20140291741 - Semiconductor device and fabrication method thereof
A method of fabricating a semiconductor device includes forming a first metal gate electrode over a substrate, forming a second metal gate electrode over the substrate, removing at least a part of the first metal gate electrode to form a first opening, and filling the first opening with a non-conductive...

10/02/14 - 20140291742 - Pixel structure and fabricating method thereof
A fabrication method of a pixel structure and a pixel structure are provided. A first patterned metal layer including scan lines and a gate is formed on a substrate. A first insulation layer, a semiconductor layer, an etching stop pattern and a metal layer are formed sequentially on the first...

09/25/14 - 20140284667 - Finfet with reduced capacitance
An improved finFET structure, and method forming the same, including a plurality of fins etched from a semiconductor substrate, a plurality of gates above and perpendicular to the plurality of fins, each comprising a pair of spacers on opposing sides of the gates, and a gap fill material above the...

09/25/14 - 20140284668 - Semiconductor device and method for manufacturing the same
An object of the present invention is to provide a semiconductor device having a conductive film, which sufficiently serves as an antenna, and a method for manufacturing thereof. The semiconductor device has an element formation layer including a transistor, which is provided over a substrate, an insulating film provided on...

09/18/14 - 20140264478 - Interface for metal gate integration
A metal oxide semiconductor field effect transistor (MOSFET) includes a semiconductor substrate and a interlayer dielectric (ILD) over the semiconductor substrate. A gate structure is formed within the ILD and disposed on the semiconductor substrate, wherein the gate structure includes a high-k dielectric material layer and a metal gate stack....

09/18/14 - 20140264479 - Methods of increasing space for contact elements by using a sacrificial liner and the resulting device
One method includes forming a sidewall spacer adjacent a gate structure, forming a first liner layer on the sidewall spacer, forming a second liner layer on the first liner layer, forming a first layer of insulating material above the substrate and adjacent the second liner layer, selectively removing at least...

09/18/14 - 20140264480 - Semiconductor device and method of forming the same
A method of forming a semiconductor device includes the following steps. At first, a semiconductor substrate is provided, and a metal gate structure and a first dielectric layer are disposed on the semiconductor substrate, wherein a top surface of the metal gate structure is aligned with a top surface of...

09/18/14 - 20140264481 - Plug structure and process thereof
A plug structure including a first dielectric layer, a second dielectric layer, a barrier layer and a second plug is provided. The first dielectric layer having a first plug therein is located on a substrate, wherein the first plug physically contacts a source/drain in the substrate. The second dielectric layer...

09/18/14 - 20140264482 - Carbon-doped cap for a raised active semiconductor region
After formation of a disposable gate structure, a raised active semiconductor region includes a vertical stack, from bottom to top, of an electrical-dopant-doped semiconductor material portion and a carbon-doped semiconductor material portion. A planarization dielectric layer is deposited over the raised active semiconductor region, and the disposable gate structure is...

09/18/14 - 20140264483 - Metal gate structures for field effect transistors and method of fabrication
The present invention relates to combinations of materials and fabrication techniques which are useful in the fabrication of filled, metal-comprising gates for use in planar and 3D Field Effect Transistor (FET) structures. The FET structures described are of the kind needed for improved performance in semiconductor device structures produced at...

09/18/14 - 20140264484 - Fluorine-doped channel silicon-germanium layer
Methods for forming P-type channel metal-oxide-semiconductor field effect transistors (PMOSFETs) with improved interface roughness at the channel silicon-germanium (cSiGe) layer and the resulting devices are disclosed. Embodiments may include designating a region in a substrate as a channel region, forming a cSiGe layer above the designated channel region, and implanting...

09/18/14 - 20140264485 - Fin-type semiconductor device
An apparatus comprises a substrate and a fin-type semiconductor device extending from the substrate. The fin type semiconductor device comprises a fin that comprises a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second...

09/18/14 - 20140264486 - Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
One method includes forming a recessed gate/spacer structure that partially defines a spacer/gate cap recess, forming a gate cap layer in the spacer/gate cap recess, forming a gate cap protection layer on an upper surface of the gate cap layer, and removing portions of the gate cap protection layer, leaving...

09/18/14 - 20140264487 - Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned...

09/18/14 - 20140264488 - Methods of forming low defect replacement fins for a finfet semiconductor device and the resulting devices
One illustrative device disclosed herein includes a substrate fin formed in a substrate comprised of a first semiconductor material, wherein at least a sidewall of the substrate fin is positioned substantially in a <100> crystallographic direction of the crystalline structure of the substrate, a replacement fin structure positioned above the...

09/18/14 - 20140264489 - Wrap around stressor formation
For the formation of a stressor on one or more of a source and drain defined on a fin of FINFET semiconductor structure, a method can be employed including performing selective epitaxial growth (SEG) on one or more of the source and drain defined on the fin, separating the fin...

09/18/14 - 20140264490 - Replacement gate electrode with a self-aligned dielectric spacer
A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions....

09/18/14 - 20140264491 - Semiconductor strips with undercuts and methods for forming the same
An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first...

09/18/14 - 20140264492 - Counter-doped low-power finfet
FinFETs and methods for making FinFETs are disclosed. A fin is formed on a substrate, wherein the fin has a height greater than 2 to 6 times of its width, a length defining a channel between source and drain ends, and the fin comprises a lightly doped semiconductor. A conformally...

09/18/14 - 20140264493 - Semiconductor device and fabricating the same
A semiconductor device includes a substrate, a gate stack having at least one gate vertex directed to an area in the substrate below the gate stack. The semiconductor device also includes a source structure having at least one vertex directed toward the area in the substrate and a drain structure...

09/18/14 - 20140264494 - Metal-oxide-semiconductor field-effect transistor with metal-insulator semiconductor contact structure to reduce schottky barrier
A method includes depositing a first metal layer on a native SiO2 layer that is disposed on at least one of a source and a drain of a metal-oxide-semiconductor field-effect transistor (MOSFET). A metal oxide layer is formed from the native SiO2 layer and the first metal layer, wherein the...

09/18/14 - 20140264495 - Self-aligned liner method of avoiding pl gate damage
A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The...

09/18/14 - 20140264496 - Stress enhanced finfet devices
A non-planar semiconductor with enhanced strain includes a substrate and at least one semiconducting fin formed on a surface of the substrate. A gate stack is formed on a portion of the at least one semiconducting fin. A stress liner is formed over at least each of a plurality of...

09/18/14 - 20140264497 - Self-aligned approach for drain diffusion in field effect transistors
A method for doping terminals of a field-effect transistor (FET), the FET including a drain region, a source region, and a surround gate surrounding a channel region, the method including depositing a dopant-containing layer, such that the surround gate prevents the dopant-containing layer from contacting the channel region of the...

09/18/14 - 20140264498 - Memory device and method of manufacturing the same
A memory device includes a gate structure, a contact plug, and a spacer. The gate structure includes first and second conductive layer patterns sequentially stacked on a substrate. The contact plug passes through the second conductive layer pattern, and a sidewall of the contact plug directly contacts at least a...

09/18/14 - 20140264499 - Semiconductor devices having dielectric caps on contacts and related fabrication methods
Semiconductor device structures are provided. An exemplary semiconductor device structure includes a substrate of a semiconductor material and a gate structure overlying the substrate. The semiconductor substrate further includes a doped region formed in the substrate proximate the gate structure and a first dielectric material overlying the doped region. The...