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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode)

Having Insulated Electrode (e.g., Mosfet, Mos Diode)

Having Insulated Electrode (e.g., Mosfet, Mos Diode) patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

04/03/14 - 20140091369 - High voltage metal-oxide-semiconductor transistor device
A HV MOS transistor device is provided. The HV MOS transistor device includes a substrate comprising at least an insulating region formed thereon, a gate positioned on the substrate and covering a portion of the insulating region, a drain region and a source region formed at respective sides of the...

04/03/14 - 20140091370 - Transistor formation using cold welding
A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is...

04/03/14 - 20140091371 - Semiconductor device
A semiconductor device including: a substrate having a channel region and first and second recesses disposed on opposite sides of the channel region; a gate insulating layer disposed on the channel region; a gate structure disposed on the gate insulating layer; and a source region disposed in the first recess...

04/03/14 - 20140091372 - Method for producing semiconductor device and semiconductor device
In a first step, a planar silicon layer is formed on a silicon substrate and first and second pillar-shaped silicon layers are formed on the planar silicon layer; a second step includes forming an oxide film hard mask on the first and second pillar-shaped silicon layers, and forming a second...

04/03/14 - 20140091373 - Semiconductor device with breakdown preventing layer
A semiconductor device with a breakdown preventing layer is provided. The breakdown preventing layer can be located in a high-voltage surface region of the device. The breakdown preventing layer can include an insulating film with conducting elements embedded therein. The conducting elements can be arranged along a lateral length of...

03/27/14 - 20140084351 - Replacement channels for semiconductor devices and methods for forming the same using dopant concentration boost
A replacement channel and a method for forming the same in a semiconductor device are provided. A channel area is defined in a substrate which is a surface of a semiconductor wafer or a structure such as a fin formed over the wafer. Portions of the channel region are removed...

03/20/14 - 20140077274 - Integrated circuits with improved gate uniformity and methods for fabricating same
Integrated circuits with improved gate uniformity and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure including a first region and a second region and a structure surface formed by the first region and the second region....

03/20/14 - 20140077275 - Semiconductor device and method with greater epitaxial growth on 110 crystal plane
A semiconductor processing method is provided which promotes greater growth on <110> crystallographic planes than on other crystallographic planes. Growth rates with the process can be reversed compared to typical epitaxial growth processes such that the highest rate of growth occurs on <110> crystallographic planes and the least amount of...

03/20/14 - 20140077276 - Middle-of-line borderless contact structure and method of forming
Various embodiments disclosed include semiconductor structures and methods of forming such structures. In one embodiment, a method includes: providing a semiconductor structure including: a substrate; at least one gate structure overlying the substrate; and an interlayer dielectric overlying the substrate and the at least one gate structure; removing the ILD...

03/20/14 - 20140077277 - Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate that has a surface. The semiconductor further includes a fin disposed on the surface and including a semiconductor member. The semiconductor further includes a spacer disposed on the surface, having a type of stress, and overlapping the semiconductor member in a direction parallel to...

03/20/14 - 20140077278 - Semiconductor device and manufacturing method of the same
The performance of power semiconductor device of partial gate type structure may be improved by providing the source region only adjacent the gate electrodes in the structure, and providing the contact spaced from the gate by the source. The device includes a plurality of field plate electrodes which extend inwardly...

03/20/14 - 20140077279 - Semiconductor device and manufacturing method therefor
A semiconductor device and a manufacturing method therefor are provided. The semiconductor device includes a semiconductor substrate including a trench used for a source/drain region; and a SiGe seed layer formed simultaneously on the sidewall and bottom of the trench, and the SiGe seed layer on the sidewall of the...

03/20/14 - 20140077280 - Semiconductor device
A semiconductor device includes: a substrate; a semiconductor element on the substrate; an interconnection on the substrate and electrically connected to the semiconductor element; a window frame member on the substrate, surrounding the semiconductor element, and in contact with the interconnection; and a sealing window bonded to the window frame...

03/20/14 - 20140077281 - Semiconductor device and method of fabricating the same
A semiconductor device includes an interlayer insulating film on a substrate, the interlayer insulating film including a trench, a gate insulating film in the trench, a diffusion film on the gate insulating film, the diffusion film including a first diffusion material, a gate metal structure on the diffusion film, the...

03/13/14 - 20140070282 - Self-aligned contacts
Self-aligned contacts in a metal gate structure and methods of manufacture are disclosed herein. The method includes forming a metal gate structure having a sidewall structure. The method further includes recessing the metal gate structure and forming a masking material within the recess. The method further includes forming a borderless...

03/13/14 - 20140070283 - Field effect transistor and method of fabrication
An improved field effect transistor and method of fabrication are disclosed. A barrier layer stack is formed in the base and sidewalls of a gate cavity. The barrier layer stack has a first metal layer and a second metal layer. A gate electrode metal is deposited in the cavity. The...

03/13/14 - 20140070284 - Self-aligned carbon nanostructure field effect transistors using selective dielectric deposition
Self-aligned carbon nanostructure field effect transistor structures are provided, which are formed using selective dielectric deposition techniques. For example, a transistor device includes an insulating substrate and a gate electrode embedded in the insulating substrate. A dielectric deposition-prohibiting layer is formed on a surface of the insulating substrate surrounding the...

03/13/14 - 20140070285 - Methods of forming semiconductor devices with self-aligned contacts and the resulting devices
One method includes forming a sacrificial gate structure above a substrate, forming a first sidewall spacer adjacent a sacrificial gate electrode, removing a portion of the first sidewall spacer to expose a portion of the sidewalls of the sacrificial gate electrode, and forming a liner layer on the exposed sidewalls...

03/13/14 - 20140070286 - Nano-pillar transistor fabrication and use
A field effect nano-pillar transistor has a pillar shaped gate element incorporating a biomimitec portion that provides various advantages over prior art devices. The small size of the nano-pillar transistor allows for advantageous insertion into cellular membranes, and the biomimitec character of the gate element operates as an advantageous interface...

03/13/14 - 20140070287 - Semiconductor device and method of manufacturing same
To provide a semiconductor device and a manufacturing method thereof achieving both reduction in ON resistance and increase in breakdown voltage and suppressing a short circuit. The semiconductor device has, in its semiconductor substrate having a main surface, a p− type epitaxial region, n− type epitaxial region, n type offset...

03/06/14 - 20140061732 - Method and device to achieve self-stop and precise gate height
A method for enabling fabrication of RMG devices having a low gate height variation and a substantially planar topography and resulting device are disclosed. Embodiments include: providing on a substrate two dummy gate electrodes, each between a pair of spacers; providing a source/drain region between the two dummy gate electrodes;...

03/06/14 - 20140061733 - Semiconductor device with a passivation layer
A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride...

03/06/14 - 20140061734 - Finfet with reduced parasitic capacitance
A gate dielectric and a gate electrode are formed over a plurality of semiconductor fins. An inner gate spacer is formed and source/drain extension regions are epitaxially formed on physically exposed surface of the semiconductor fins as discrete components that are not merged. An outer gate spacer is subsequently formed....

03/06/14 - 20140061735 - Semiconductor device and method of manufacturing thereof
A method for manufacturing a transistor device is provided, the transistor device comprising a germanium based channel layer, the method comprising providing a gate structure on the germanium comprising channel layer provided on a substrate, the gate structure being provided between a germanium based source area and a germanium based...

03/06/14 - 20140061736 - Semiconductor device and method of manufacturing the same
A semiconductor device includes a stack structure of a conductive line and an insulating capping line extending in a first direction on a substrate, a plurality of contact plugs arranged in a row along the first direction and having sidewall surfaces facing the conductive line with air spaces between the...

02/27/14 - 20140054654 - Mos transistor and process thereof
A MOS transistor includes a gate structure on a substrate, and the gate structure includes a wetting layer, a transitional layer and a low resistivity material from bottom to top, wherein the transitional layer has the properties of a work function layer, and the gate structure does not have any...

02/27/14 - 20140054655 - Semiconductor gate structure and method of fabricating thereof
A semiconductor gate structure is provided having a trench, the trench assembled by a dielectric structure and a stack structure. A first conductive layer may be conformally applied to the dielectric structure and the stack structure. An oxide layer is formed along the first conductive layer and may then be...

02/27/14 - 20140054656 - Semiconductor structure and method for manufacturing the same
A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a device region, a first doped region and a gate structure. The first doped region is formed in the substrate adjacent to the device region. The gate structure is on the first...

02/27/14 - 20140054657 - Semiconductor device and method of manufacturing same
In one embodiment, a semiconductor device includes a substrate, a gate insulator on the substrate, and a gate electrode on the gate insulator. The device further includes a source diffusion layer of a first conductivity type and a drain diffusion layer of a second conductivity type disposed on a surface...

02/27/14 - 20140054658 - Semiconductor device and method for manufacturing the same
The present invention discloses a semiconductor device, comprising: a substrate, a gate stack structure on the substrate, source and drain regions in the substrate on both sides of the gate stack structure, and a channel region between the source and drain regions in the substrate, characterized in that at least...

02/27/14 - 20140054659 - Semiconductor devices and methods fabricating same
Disclosed are semiconductor devices and methods of forming the same. According to the semiconductor device, gate structures are provided to be buried in a substrate and first dopant regions and second dopant regions are provided at both ends of the gate structures. Conductive lines cross the gate structures and are...

02/27/14 - 20140054660 - Film formation method and nonvolatile memory device
According to one embodiment, a film formation method can include irradiating a layer to be processed provided on an underlayer with an ionized gas cluster containing any one of oxygen and nitrogen to modify at least part of the layer....

02/20/14 - 20140048855 - Semiconductor device and fabrication method thereof
A semiconductor device and a method for fabricating the semiconductor device are disclosed. A gate stack is formed over a substrate. A spacer is formed adjoining a sidewall of the gate stack. A recess is formed between the spacer and the substrate. Then, a strained feature is formed in the...

02/20/14 - 20140048856 - Semiconductor device including transistors
A semiconductor device includes an active area defined by a device isolation layer and including a plurality of source/drain regions, a gate structure disposed on the active area and extending in a first direction, a stress layer contacting a side surface of each of the plurality of source/drain regions and...

02/20/14 - 20140048857 - Bulk fin-field effect transistors with well defined isolation
A process fabricates a fin field-effect-transistor by implanting a dopant into an exposed portion of a semiconductor substrate within a cavity. The cavity is formed in a dielectric layer on the semiconductor substrate. The cavity exposes the portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially...

02/20/14 - 20140048858 - Semiconductor device
A semiconductor device including a silicon substrate including a first region and a second region; a gate electrode above the first region and the second region; an insulation film extending from the gate electrode to the second region to cover part of the gate electrode and part of the second...

02/13/14 - 20140042499 - Stress enhanced high voltage device
A method of forming a device is disclosed. A substrate having a device region is provided. The device region comprises a source region, a gate region and a drain region defined thereon. A gate is formed in the gate region, a source is formed in the source region and drain...

02/13/14 - 20140042500 - Contact structure of semiconductor device
The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a...

02/13/14 - 20140042501 - Mos transistor and process thereof
A MOS transistor includes a gate structure and a spacer. The gate structure is located on a substrate. The spacer is located on the substrate beside the gate structure, and the spacer includes an L-shaped inner spacer and an outer spacer, wherein the outer spacer is located on the L-shaped...

02/13/14 - 20140042502 - Semiconductor devices with self-aligned contacts and low-k spacers
One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes...

02/13/14 - 20140042503 - Semiconductor memory device having an electrically floating body transistor
A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface...

02/13/14 - 20140042504 - Method for manufacturing semiconductor device and semiconductor device
A manufacturing method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer; forming diffusion layers in an upper portion of the pillar-shaped silicon layer, an upper portion of...

02/13/14 - 20140042505 - Device active channel length/width greater than channel length/width
A device including a drain, a channel, and a gate. The channel surrounds the drain and has a channel length to width ratio. The gate is situated over the channel to provide an active channel region that has an active channel region length to width ratio that is greater than...

02/06/14 - 20140035010 - Integrated circuit having a replacement gate structure and method for fabricating the same
A method for fabricating an integrated circuit includes forming a temporary gate structure on a semiconductor substrate. The temporary gate structure includes a temporary gate material disposed between two spacer structures. The method further includes forming a first directional silicon nitride liner overlying the temporary gate structure and the semiconductor...

02/06/14 - 20140035011 - Methods and devices for forming nanostructure monolayers and devices including such monolayers
Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also...

01/30/14 - 20140027820 - Forming facet-less epitaxy with self-aligned isolation
A method of forming a semiconductor structure may include preparing a continuous active layer in a region of the substrate and forming a plurality of adjacent gates on the continuous active layer. A first raised epitaxial layer may be deposited on a recessed region of the continuous active layer between...

01/30/14 - 20140027821 - Device performance enhancement
Among other things, one or more techniques for enhancing device (e.g., transistor) performance are provided herein. In one embodiment, device performance is enhanced by forming an extended dummy region at an edge of a region of a device and forming an active region at a non-edge of the region. Limitations...

01/30/14 - 20140027822 - Copper contact plugs with barrier layers
A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer...

01/30/14 - 20140027823 - Method for forming thin metal compound film and semiconductor structure with thin metal compound film
A method for forming a metal compound film includes: providing a substrate structure; forming a first metal layer on the substrate structure; performing a first microwave annealing process to conduct a reaction between the first metal layer and the substrate structure so as to form a first polycrystalline film of...

01/30/14 - 20140027824 - Semiconductor devices (as amended)
In a semiconductor device and a method of manufacturing the same, the semiconductor device includes a gate structure crossing an active region of a silicon substrate. Spacers are provided on both sides of the gate structure, respectively. Silicon patterns fill up recessed portions of the silicon substrate and on both...

01/30/14 - 20140027825 - Threshold voltage adjustment in a fin transistor by corner implantation
When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics...