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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode)

Having Insulated Electrode (e.g., Mosfet, Mos Diode)

Having Insulated Electrode (e.g., Mosfet, Mos Diode) patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

07/31/14 - 20140209984 - Semiconductor device with multi level interconnects and method of forming the same
A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a gate structure separating source and drain (S/D) features. The semiconductor device further includes a first dielectric layer formed over the substrate, the first dielectric layer including a first interconnect...

07/24/14 - 20140203333 - Semiconductor device having modified profile metal gate
In one embodiment, a method includes providing a semiconductor substrate having a trench disposed thereon and forming a plurality of layers in the trench. The plurality of layers formed in the trench is etched thereby providing at least one etched layer having a top surface that lies below a top...

07/24/14 - 20140203334 - Method for fabricating a finfet device including a stem region of a fin element
A method includes providing a substrate having a fin extending from a first (e.g., top) surface of the substrate. The fin has first region (a stem region) and a second region (an active region) each having a different composition. The first region of the fin is modified to decrease a...

07/24/14 - 20140203335 - Semiconductor devices and methods for fabricating the same
A semiconductor device includes an insulating film on a substrate and including a trench, a gate insulating film in the trench, a DIT (Density of Interface Trap) improvement film on the gate insulating film to improve a DIT of the substrate, and a first conductivity type work function adjustment film...

07/24/14 - 20140203336 - Adhesion layer and multiphase ultra-low k dielectric material
A dielectric material incorporating a graded carbon adhesion layer whereby the content of C increases with layer thickness and a multiphase ultra low k dielectric comprising a porous SiCOH dielectric material having a k less than 2.7 and a modulus of elasticity greater than 7 GPa is described. A semiconductor...

07/24/14 - 20140203337 - Method of forming gate dielectric layer and method of fabricating semiconductor device
A method for fabricating a semiconductor device includes ion-implanting germanium into a monocrystalline silicon-containing substrate; forming a gate oxide layer over a surface of the monocrystalline silicon-containing substrate and forming, under the gate oxide layer, a germanium-rich region in which the germanium is concentrated, by performing a plasma oxidation process;...

07/24/14 - 20140203338 - Finfet device with epitaxial structure
A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material...

07/24/14 - 20140203339 - Semiconductor device comprising self-aligned contact elements and a replacement gate electrode structure
A semiconductor device includes a high-k metal gate electrode structure that is positioned above an active region, has a top surface that is positioned at a gate height level, and includes a high-k dielectric material and an electrode metal. Raised drain and source regions are positioned laterally adjacent to the...

07/17/14 - 20140197468 - Methods of forming semiconductor device with self-aligned contact elements and the resulting device
One method disclosed includes forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers, removing a portion of the sidewall spacers to define recessed sidewall spacers, removing a portion of the final gate structure to define a recessed final gate structure and forming an...

07/10/14 - 20140191295 - Dummy gate interconnect for semiconductor device
A method of forming a semiconductor device comprising a dummy gate interconnect includes forming a dummy gate on a substrate, the dummy gate comprising a dummy gate metal layer located on the substrate, and a dummy gate polysilicon layer located on the dummy gate metal layer; forming an active gate...

07/10/14 - 20140191296 - Self-aligned dielectric isolation for finfet devices
Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height...

07/10/14 - 20140191297 - Strained finfet with an electrically isolated channel
A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material...

07/10/14 - 20140191298 - Semiconductor device and manufacturing method of the same
A semiconductor device includes a semiconductor substrate, a metal gate structure, at least an epitaxial layer, an interlayer dielectric, at least a contact hole, at least a metal silicide layer and a fluorine-containing layer. The semiconductor substrate has at least a gate region and at least a source/drain region adjoining...

07/10/14 - 20140191299 - Dual damascene metal gate
A method for fabricating a dual damascene metal gate includes forming a dummy gate onto a substrate, disposing a protective layer on the substrate and the dummy gate, and growing an expanding layer on sides of the dummy gate. The method further includes removing the protective layer, forming a spacer...

07/10/14 - 20140191300 - Hard mask etch stop for tall fins
A hard mask etch stop is formed on the top surface of tall fins to preserve the fin height and protect the top surface of the fin from damage during etching steps of the transistor fabrication process. In an embodiment, the hard mask etch stop is formed using a dual...

07/10/14 - 20140191301 - Transistor and fabrication method
Transistors and fabrication methods are provided. A first sidewall can be formed on each sidewall of a gate structure. A second sidewall can be formed on the first sidewall. The first sidewall can be made of a doped material. After forming a source and a drain, a metal silicide layer...

07/03/14 - 20140183605 - Semiconductor device and method of manufacturing the semiconductor device
A method of manufacturing a semiconductor device includes forming a plurality of fin structures on a substrate, the plurality of fin structures including a diffusion region, forming an epitaxial layer on the plurality of fin structures in an area of the diffusion region such that a height of the upper...

06/26/14 - 20140175526 - Semiconductor device for current control and method thereof
A semiconductor device where at least one of a portion of the first metal layer that extends from the source contact, a portion of the second metal layer that extends from the source contact, a portion of the first metal layer that extends from the drain contact, and a portion...

06/26/14 - 20140175527 - Semiconductor structure and process thereof
A semiconductor structure includes a gate, a dual spacer and two recesses. The gate is located on a substrate. The dual spacer is located on the substrate beside the gate. The recesses are located in the substrate and the dual spacers, wherein the sidewall of each of the recesses next...

06/19/14 - 20140167119 - Methods of forming a sidewall spacer having a generally triangular shape and a semiconductor device having such a spacer
A method of forming a spacer is disclosed that involves forming a layer of spacer material above an etch stop layer, performing a first main etching process on the layer of spacer material to remove some of material, stopping the etching process prior to exposing the etch stop layer and...

06/19/14 - 20140167120 - Methods of forming a finfet semiconductor device by performing an epitaxial growth process
A method of forming a FinFET device involves performing an epitaxial growth process to form a layer of semiconducting material on a semiconducting substrate, wherein a first portion of the layer of semiconducting material will become a fin structure for the FinFET device and wherein a plurality of second portions...

06/19/14 - 20140167121 - Filament free silicide formation
A device and methods for forming the device are disclosed. The method includes providing a substrate. A gate having a gate electrode and sidewall spacers are formed adjacent to sidewalls of the gate. A height HG of the gate is lower than a height HS of the sidewall spacers. A...

06/19/14 - 20140167122 - Semiconductor device and manufacturing method thereof
A semiconductor device and method of manufacturing the semiconductor device are disclosed. The semiconductor device includes: a substrate including an active region and at least one groove isolation region formed on the substrate, wherein the at least one groove isolation region is formed adjoining the active region, a gate structure...

06/19/14 - 20140167123 - Power semiconductor device and method of manufacturing the same
There is provided a power semiconductor device including: a body region having a first conductivity; a well formed in an upper portion of the body region and having a second conductivity; and a conductive via formed in the body region while traversing the well....

06/12/14 - 20140159123 - Etch resistant raised isolation for semiconductor devices
A method including providing fins etched from a semiconductor substrate, the fins covered by an oxide layer and a nitride layer, the oxide layer located between the fins and the nitride layer, removing a portion of the fins to form an opening, and forming a spacer on a sidewall of...

06/12/14 - 20140159124 - Epitaxial grown extremely shallow extension region
A method to scale a MOSFET structure while maintaining gate control is disclosed. The extension regions of the MOSFET are formed by epitaxial growth and can be formed after the completion of high temperature processing. The extensions can be extremely shallow and have an abrupt interface with the channel. A...

06/12/14 - 20140159125 - Contact landing pads for a semiconductor device and methods of making same
One device herein includes first and second spaced-apart active regions, a transistor formed in and above the first active region, wherein the transistor has a gate electrode, a conductive contact landing pad that is coupled to the second active region, wherein the contact landing pad is made of the same...

06/12/14 - 20140159126 - Methods of forming a finfet semiconductor device with undoped fins
One method disclosed herein includes, prior to forming an isolation region in a semiconducting substrate for the device, forming a doped well region and a doped punch-stop region in the substrate, introducing a dopant material that is adapted to retard diffusion of boron or phosphorous into the substrate to form...

06/12/14 - 20140159127 - Semiconductor device and method of manufacturing the same
A semiconductor device having reduced contact region area achieved at least in part by forming pad portions of the word lines using an asymmetric stair shape separately formed in first and second pad structures. Contact region area is reduced when compared with manufacturing processes known in the art. This leads...

06/05/14 - 20140151756 - Fin field effect transistors including complimentarily stressed channels
A stressed single crystalline epitaxial semiconductor layer having a first type stress is formed on a single crystalline substrate layer. First and second semiconductor fins are formed by patterning the stressed single crystalline epitaxial semiconductor layer. A center portion of each first semiconductor fin is undercut to form a recessed...

06/05/14 - 20140151757 - Substrate-templated epitaxial source/drain contact structures
Single crystalline semiconductor fins are formed on a single crystalline buried insulator layer. After formation of a gate electrode straddling the single crystalline semiconductor fins, selective epitaxy can be performed with a semiconductor material that grows on the single crystalline buried insulator layer to form a contiguous semiconductor material portion....

06/05/14 - 20140151758 - Semiconductor device and method of manufacturing a semiconductor device
A semiconductor device includes a transistor, formed in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode being adjacent to the channel region, the gate electrode configured to control a conductivity of...

06/05/14 - 20140151759 - Facet-free strained silicon transistor
The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been...

06/05/14 - 20140151760 - Doped flowable pre-metal dielectric
A method of filling gaps between gates with doped flowable pre-metal dielectric (PMD) and the resulting device are disclosed. Embodiments include forming at least two dummy gates on a substrate, each dummy gate being surrounded by spacers; filling a gap between adjacent spacers of the at least two dummy gates...

06/05/14 - 20140151761 - Fin-like field effect transistor (finfet) channel profile engineering method and associated device
A FinFET device and method for fabricating a FinFET device are disclosed. An exemplary method includes providing a substrate; forming a fin over the substrate; forming an isolation feature over substrate; forming a gate structure including a dummy gate over a portion of the fin, the gate structure traversing the...

06/05/14 - 20140151762 - Semiconductor device and method of forming the same
A method of forming a semiconductor device includes forming a NMOS gate structure over a substrate. The method further includes forming an amorphized region in the substrate adjacent to the NMOS gate structure. The method also includes forming a lightly doped source/drain (LDD) region in the amorphized region. The method...

06/05/14 - 20140151763 - Semiconductor structure having contact plug and method of making the same
The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD...

06/05/14 - 20140151764 - Semiconductor and manufacturing method thereof
A semiconductor element and a manufacturing method thereof are provided. The semiconductor element includes a base, an epitaxy layer, a first well, a second well, a third well, a first heavily doping region, a second heavily doping region, a implanting region and a conductive layer. The epitaxy layer is disposed...

06/05/14 - 20140151765 - Gate-all-around carbon nanotube transistor with selectively doped spacers
A method of fabricating a semiconducting device is disclosed. A carbon nanotube is formed on a substrate. A portion of the substrate is removed to form a recess below a section of the carbon nanotube. A doped material is applied in the recess to fabricate the semiconducting device. The recess...

06/05/14 - 20140151766 - Finfet device with dual-strained channels and method for manufacturing thereof
A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least...

06/05/14 - 20140151767 - Method for producing semiconductor device and semiconductor device
A method for producing a semiconductor device includes a step of forming a first insulating film around a fin-shaped silicon layer and forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer; a step of implanting an impurity into upper portions of the pillar-shaped silicon layer...

05/29/14 - 20140145247 - Fin isolation in multi-gate field effect transistors
A method for fabricating a field effect transistor (FET) device includes forming a plurality of semiconductor fins on a substrate, removing a semiconductor fin of the plurality of semiconductor fins from a portion of the substrate, forming an isolation fin that includes a dielectric material on the substrate on the...

05/29/14 - 20140145248 - Dummy fin formation by gas cluster ion beam
FinFET structures with dielectric fins and methods of fabrication are disclosed. A gas cluster ion beam (GCIB) tool is used to apply an ion beam to exposed fins, which converts the fins from a semiconductor material such as silicon, to a dielectric such as silicon nitride or silicon oxide. Unlike...

05/29/14 - 20140145249 - Diode structure compatible with finfet process
An embodiment integrated circuit (e.g., diode) and method of making the same. The embodiment integrated circuit includes a well having a first doping type formed over a substrate having the first doping type, the well including a fin, a source formed over the well on a first side of the...

05/22/14 - 20140138750 - Jog design in integrated circuits
A device includes an active region in a semiconductor substrate, a gate strip over and crossing the active region, and a jog over the active region and connected to the gate strip to form a continuous region. The jog is on a side of the gate strip. A first contact...

05/22/14 - 20140138751 - Metal gate structures for cmos transistor devices having reduced parasitic capacitance
A method of forming a field effect transistor (FET) device includes forming a gate structure over a substrate, the gate structure including a wide bottom portion and a narrow portion formed on top of the bottom portion; the wide bottom portion comprising a metal material and having a first width...

05/15/14 - 20140131776 - Fin recess last process for finfet fabrication
A method includes forming isolation regions extending from a top surface of a semiconductor substrate into the semiconductor substrate, and forming a hard mask strip over the isolation regions and a semiconductor strip, wherein the semiconductor strip is between two neighboring ones of the isolation regions. A dummy gate strip...

05/15/14 - 20140131777 - Integrated circuits and methods for fabricating integrated circuits with salicide contacts on non-planar source/drain regions
Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a fin over a semiconductor substrate. The method further includes selectively epitaxially growing a silicon-containing material on the fin and providing the fin with a diamond-shaped cross-section and...

05/08/14 - 20140124840 - Prevention of fin erosion for semiconductor devices
A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior...

05/08/14 - 20140124841 - Methods of forming replacement gate structures on semiconductor devices and the resulting device
One method includes forming first sidewall spacers adjacent opposite sides of a sacrificial gate structure and a gate cap layer, removing the gate cap layer and a portion of the first sidewall spacers to define reduced-height first sidewall spacers, forming second sidewall spacers, removing the sacrificial gate structure to thereby...

05/08/14 - 20140124842 - Contact structure of semiconductor device
The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material...