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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode)

Having Insulated Electrode (e.g., Mosfet, Mos Diode)

Having Insulated Electrode (e.g., Mosfet, Mos Diode) patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

10/23/14 - 20140312393 - Fin-fet transistor with punchthrough barrier and leakage protection regions
A method of forming a field effect transistor includes forming a punchthrough region having a first conductivity type in a substrate, forming an epitaxial layer having the first conductivity type on the substrate, patterning the epitaxial layer to form a fin that protrudes from the substrate, forming a dummy gate...

10/23/14 - 20140312394 - Semiconductor device including a material to absorb thermal energy
A semiconductor device includes a semiconductor chip and a first material including molecules that are configured to absorb thermal energy by reversibly changing a spatial molecular structure of the molecules....

10/23/14 - 20140312395 - Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact
A photo-patternable dielectric material is provided to a structure which includes a substrate having at least one gate structure. The photo-patternable dielectric material is then patterned forming a plurality of sacrificial contact structures adjacent the at least one gate structure. A planarized middle-of-the-line dielectric material is then provided in which...

10/23/14 - 20140312396 - Split multi-gate field-effect transistor
A semiconductor device based on split multi-gate field-effect transistor radio frequency devices is provided. The semiconductor device includes a substrate and a gate structure above the substrate and orthogonal to a channel axis. The semiconductor device also includes a semiconductor fin structure above the substrate along the channel axis. The...

10/23/14 - 20140312397 - Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact
A photo-patternable dielectric material is provided to a structure which includes a substrate having at least one gate structure. The photo-patternable dielectric material is then patterned forming a plurality of sacrificial contact structures adjacent the at least one gate structure. A planarized middle-of-the-line dielectric material is then provided in which...

10/23/14 - 20140312398 - Recessing sti to increase fin height in fin-first process
A method includes forming a gate stack over top surfaces of a semiconductor strip and insulation regions on opposite sides of the semiconductor strip. The insulation regions include first portions overlapped by the gate stack, and second portions misaligned from the gate stack. An end portion of the semiconductor strip...

10/23/14 - 20140312399 - Semiconductor device and method of manufacturing the same
A gate insulating film of a conventional semiconductor device is subjected to dielectric breakdown at a low electric field strength and thus its service life is short. This is because since the size of the asperity of at least one of a semiconductor layer-side interface and an electrode-side interface is...

10/16/14 - 20140306271 - Unltra-shallow junction semiconductor field-effect transistor and method of making
An ultra-shallow junction semiconductor field-effect transistor and its methods of making are disclosed. In the present disclosure, a mixture film is formed on a semiconductor substrate with a gate structure formed thereon using a physical vapor deposition (PVD) process, which employs a mixture of metal and semiconductor dopants as a...

10/16/14 - 20140306272 - Method of forming a finfet structure
A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed...

10/16/14 - 20140306273 - Structure of metal gate structure and manufacturing method of the same
A manufacturing method of a metal gate structure is provided. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate...

10/16/14 - 20140306274 - Self-aligned structure for bulk finfet
A FinFET structure which includes a bulk semiconductor substrate; semiconductor fins extending from the bulk semiconductor substrate, each of the semiconductor fins having a top portion and a bottom portion such that the bottom portion of the semiconductor fins is doped and the top portion of the semiconductor fins is...

10/16/14 - 20140306275 - Semiconductor device and method of manufacturing semiconductor device
A semiconductor device is disclosed. The semiconductor device includes an insulating layer formed selectively on a semiconductor layer; a lower electrode, formed on the insulating layer, having an end portion at a position spaced apart by a predetermined distance inward from a periphery of the insulating layer; a dielectric film...

10/09/14 - 20140299923 - Field effect transistor
A field effect transistor includes a semiconductor substrate having a protrusion with at least one inclined surface, a gate insulator disposed at least on a portion of the inclined surface, and a gate conductor disposed on the gate insulator, wherein the semiconductor substrate comprises doped regions sandwiching a channel region,...

10/09/14 - 20140299924 - Formation of the dielectric cap layer for a replacement gate structure
Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a...

10/02/14 - 20140291734 - Thin channel mosfet with silicide local interconnect
A semiconductor structure and method of manufacturing the same are provided. The semiconductor structure includes a semiconductor substrate having an isolated area comprising a first region and a second region. A first raised RSD region is formed in the first region and a second RSD region is formed in the...

10/02/14 - 20140291735 - Double patterning via triangular shaped sidewall spacers
An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers for mandrels of a filler material substantially different...

10/02/14 - 20140291736 - Semiconductor device and method of manufacturing the same
In one embodiment, a first main terminal region of a first conductivity type and a second main terminal region of a second conductivity type, which is an opposite conductivity type of the first conductivity type, formed in the semiconductor substrate so as to sandwich a gate electrode, a diffusion layer...

10/02/14 - 20140291737 - Transistor architecture having extended recessed spacer and source/drain regions and method of making same
Techniques are disclosed for forming transistor architectures having extended recessed spacer and source/drain (S/D) regions. In some embodiments, a recess can be formed, for example, in the top of a fin of a fin-based field-effect transistor (finFET), such that the recess allows for forming extended recessed spacers and S/D regions...

10/02/14 - 20140291738 - Semiconductor device and manufacturing method therefor
A semiconductor electronic device structure includes an active area array disposed in a substrate, an isolation structure, a plurality of recessed gate structures, a plurality of word lines, and a plurality of bit lines. The active area array a plurality of active area columns and a plurality of active area...

10/02/14 - 20140291739 - Junction-less transistor having reverse polarity structure
A junction-less transistor having an reverse polarity structure includes a substrate, a semiconductor body, a gate and a gate insulation layer. The substrate has a first polarity. The semiconductor body is disposed on the substrate, and includes a drain, a source and a channel section connected between the drain and...

10/02/14 - 20140291740 - Perforated channel field effect transistor
A device including a plurality of perforations to a semiconductor channel is provided. The device includes a semiconductor structure forming the semiconductor channel. Additionally, the device includes a source contact, a drain contact, and a gate contact to the semiconductor channel. The plurality of perforations can be located in the...

10/02/14 - 20140291741 - Semiconductor device and fabrication method thereof
A method of fabricating a semiconductor device includes forming a first metal gate electrode over a substrate, forming a second metal gate electrode over the substrate, removing at least a part of the first metal gate electrode to form a first opening, and filling the first opening with a non-conductive...

10/02/14 - 20140291742 - Pixel structure and fabricating method thereof
A fabrication method of a pixel structure and a pixel structure are provided. A first patterned metal layer including scan lines and a gate is formed on a substrate. A first insulation layer, a semiconductor layer, an etching stop pattern and a metal layer are formed sequentially on the first...

09/25/14 - 20140284667 - Finfet with reduced capacitance
An improved finFET structure, and method forming the same, including a plurality of fins etched from a semiconductor substrate, a plurality of gates above and perpendicular to the plurality of fins, each comprising a pair of spacers on opposing sides of the gates, and a gap fill material above the...

09/25/14 - 20140284668 - Semiconductor device and method for manufacturing the same
An object of the present invention is to provide a semiconductor device having a conductive film, which sufficiently serves as an antenna, and a method for manufacturing thereof. The semiconductor device has an element formation layer including a transistor, which is provided over a substrate, an insulating film provided on...

09/18/14 - 20140264478 - Interface for metal gate integration
A metal oxide semiconductor field effect transistor (MOSFET) includes a semiconductor substrate and a interlayer dielectric (ILD) over the semiconductor substrate. A gate structure is formed within the ILD and disposed on the semiconductor substrate, wherein the gate structure includes a high-k dielectric material layer and a metal gate stack....

09/18/14 - 20140264479 - Methods of increasing space for contact elements by using a sacrificial liner and the resulting device
One method includes forming a sidewall spacer adjacent a gate structure, forming a first liner layer on the sidewall spacer, forming a second liner layer on the first liner layer, forming a first layer of insulating material above the substrate and adjacent the second liner layer, selectively removing at least...

09/18/14 - 20140264480 - Semiconductor device and method of forming the same
A method of forming a semiconductor device includes the following steps. At first, a semiconductor substrate is provided, and a metal gate structure and a first dielectric layer are disposed on the semiconductor substrate, wherein a top surface of the metal gate structure is aligned with a top surface of...

09/18/14 - 20140264481 - Plug structure and process thereof
A plug structure including a first dielectric layer, a second dielectric layer, a barrier layer and a second plug is provided. The first dielectric layer having a first plug therein is located on a substrate, wherein the first plug physically contacts a source/drain in the substrate. The second dielectric layer...

09/18/14 - 20140264482 - Carbon-doped cap for a raised active semiconductor region
After formation of a disposable gate structure, a raised active semiconductor region includes a vertical stack, from bottom to top, of an electrical-dopant-doped semiconductor material portion and a carbon-doped semiconductor material portion. A planarization dielectric layer is deposited over the raised active semiconductor region, and the disposable gate structure is...

09/18/14 - 20140264483 - Metal gate structures for field effect transistors and method of fabrication
The present invention relates to combinations of materials and fabrication techniques which are useful in the fabrication of filled, metal-comprising gates for use in planar and 3D Field Effect Transistor (FET) structures. The FET structures described are of the kind needed for improved performance in semiconductor device structures produced at...

09/18/14 - 20140264484 - Fluorine-doped channel silicon-germanium layer
Methods for forming P-type channel metal-oxide-semiconductor field effect transistors (PMOSFETs) with improved interface roughness at the channel silicon-germanium (cSiGe) layer and the resulting devices are disclosed. Embodiments may include designating a region in a substrate as a channel region, forming a cSiGe layer above the designated channel region, and implanting...

09/18/14 - 20140264485 - Fin-type semiconductor device
An apparatus comprises a substrate and a fin-type semiconductor device extending from the substrate. The fin type semiconductor device comprises a fin that comprises a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second...

09/18/14 - 20140264486 - Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
One method includes forming a recessed gate/spacer structure that partially defines a spacer/gate cap recess, forming a gate cap layer in the spacer/gate cap recess, forming a gate cap protection layer on an upper surface of the gate cap layer, and removing portions of the gate cap protection layer, leaving...

09/18/14 - 20140264487 - Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned...

09/18/14 - 20140264488 - Methods of forming low defect replacement fins for a finfet semiconductor device and the resulting devices
One illustrative device disclosed herein includes a substrate fin formed in a substrate comprised of a first semiconductor material, wherein at least a sidewall of the substrate fin is positioned substantially in a <100> crystallographic direction of the crystalline structure of the substrate, a replacement fin structure positioned above the...

09/18/14 - 20140264489 - Wrap around stressor formation
For the formation of a stressor on one or more of a source and drain defined on a fin of FINFET semiconductor structure, a method can be employed including performing selective epitaxial growth (SEG) on one or more of the source and drain defined on the fin, separating the fin...

09/18/14 - 20140264490 - Replacement gate electrode with a self-aligned dielectric spacer
A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions....

09/18/14 - 20140264491 - Semiconductor strips with undercuts and methods for forming the same
An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first...

09/18/14 - 20140264492 - Counter-doped low-power finfet
FinFETs and methods for making FinFETs are disclosed. A fin is formed on a substrate, wherein the fin has a height greater than 2 to 6 times of its width, a length defining a channel between source and drain ends, and the fin comprises a lightly doped semiconductor. A conformally...

09/18/14 - 20140264493 - Semiconductor device and fabricating the same
A semiconductor device includes a substrate, a gate stack having at least one gate vertex directed to an area in the substrate below the gate stack. The semiconductor device also includes a source structure having at least one vertex directed toward the area in the substrate and a drain structure...

09/18/14 - 20140264494 - Metal-oxide-semiconductor field-effect transistor with metal-insulator semiconductor contact structure to reduce schottky barrier
A method includes depositing a first metal layer on a native SiO2 layer that is disposed on at least one of a source and a drain of a metal-oxide-semiconductor field-effect transistor (MOSFET). A metal oxide layer is formed from the native SiO2 layer and the first metal layer, wherein the...

09/18/14 - 20140264495 - Self-aligned liner method of avoiding pl gate damage
A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The...

09/18/14 - 20140264496 - Stress enhanced finfet devices
A non-planar semiconductor with enhanced strain includes a substrate and at least one semiconducting fin formed on a surface of the substrate. A gate stack is formed on a portion of the at least one semiconducting fin. A stress liner is formed over at least each of a plurality of...

09/18/14 - 20140264497 - Self-aligned approach for drain diffusion in field effect transistors
A method for doping terminals of a field-effect transistor (FET), the FET including a drain region, a source region, and a surround gate surrounding a channel region, the method including depositing a dopant-containing layer, such that the surround gate prevents the dopant-containing layer from contacting the channel region of the...

09/18/14 - 20140264498 - Memory device and method of manufacturing the same
A memory device includes a gate structure, a contact plug, and a spacer. The gate structure includes first and second conductive layer patterns sequentially stacked on a substrate. The contact plug passes through the second conductive layer pattern, and a sidewall of the contact plug directly contacts at least a...

09/18/14 - 20140264499 - Semiconductor devices having dielectric caps on contacts and related fabrication methods
Semiconductor device structures are provided. An exemplary semiconductor device structure includes a substrate of a semiconductor material and a gate structure overlying the substrate. The semiconductor substrate further includes a doped region formed in the substrate proximate the gate structure and a first dielectric material overlying the doped region. The...

09/11/14 - 20140252423 - Semiconductor device having metal gate and manufacturing method thereof
A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench and the second semiconductor device includes a second gate trench. A first work...

09/11/14 - 20140252424 - Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
One method discloses performing an etching process to form a contact opening in a layer of insulating material above at least a portion of a source/drain, region wherein, after the completion of the etching process, a portion of a gate structure of the transistor is exposed, selectively forming an oxidizable...

09/11/14 - 20140252425 - Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
One method includes performing a first etching process to form a contact opening in a layer of insulating material that exposes a portion of a gate structure of the transistor, performing a second etching process on the exposed portion of the gate structure to thereby define a gate recess, selectively...

09/11/14 - 20140252426 - Semiconductor structure with dielectric-sealed doped region
Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are...

09/11/14 - 20140252427 - Self-aligned contacts for replacement metal gate transistors
Embodiments of the invention include methods of forming gate caps. Embodiments may include providing a semiconductor device including a gate on a semiconductor substrate and a source/drain region on the semiconductor substrate adjacent to the gate, forming a blocking region, a top surface of which extends above a top surface...

09/11/14 - 20140252428 - Semiconductor fin structures and methods for forming the same
An integrated circuit structure includes a semiconductor substrate, an insulation region extending into the semiconductor substrate, and a semiconductor strip between two opposite portions of the insulation region. The semiconductor strip includes an upper portion higher than top surfaces of the insulation regions and a lower portion in the insulation...

09/11/14 - 20140252429 - Contact geometry having a gate silicon length decoupled from a transistor length
Methods for forming a semiconductor device are provided. In one embodiment, a gate structure having a gate insulating layer and a gate electrode structure formed on the gate insulating layer is provided. The methods provide reducing a dimension of the gate electrode structure relative to the gate insulating layer along...

09/11/14 - 20140252430 - Electronic device including a dielectric layer having a non-uniform thickness and a process of forming the same
An electronic device can include a transistor having a drain region, a source region, a dielectric layer, and a gate electrode. The dielectric layer can have a first portion and a second portion, wherein the first portion is relatively thicker and closer to the drain region; the second portion is...

09/11/14 - 20140252431 - Semiconductor device structure and method of forming same
An embodiment is a semiconductor device comprising a first gate structure over a semiconductor substrate, a first etch stop layer (ESL) over the semiconductor substrate and the first gate, the first ESL having a curved top surface, and a first inter-layer dielectric (ILD) on the first ESL, the first ILD...

09/11/14 - 20140252432 - Semiconductor device and method for forming the same
A semiconductor device includes a substrate and a gate structure formed over the substrate. The semiconductor device further includes an insulator feature formed in the substrate. The insulator feature includes an insulating layer and a capping layer over the insulating layer....

09/11/14 - 20140252433 - Multi-layer metal contacts
A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, the first-layer contact extending to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the...

09/11/14 - 20140252434 - Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device includes forming isolation layers in a first direction at trenches at isolation regions defined at a semiconductor substrate and forming gate lines in a second direction crossing the first direction over the isolation layers and active regions defined between the isolation layers, performing...

09/11/14 - 20140252435 - Semiconductor device
A semiconductor device concerning an embodiment is provided with a plate-like semiconductor substrate, electrode pads, electrode connecting conductors, and a source electrode back pad. The semiconductor substrate has a first cutout section in a first side, and has a second cutout section and a third cutout section in a second...

09/11/14 - 20140252436 - Semiconductor device
There is provided a semiconductor device with basic electronic elements in a three-dimensional structure. The semiconductor device has a source region and a drain region each of which includes an electrode and a silicide region, and is formed with a plurality of different crystal planes. The silicide regions on different...