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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode)

Having Insulated Electrode (e.g., Mosfet, Mos Diode)

Having Insulated Electrode (e.g., Mosfet, Mos Diode) patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

09/18/14 - 20140264478 - Interface for metal gate integration
A metal oxide semiconductor field effect transistor (MOSFET) includes a semiconductor substrate and a interlayer dielectric (ILD) over the semiconductor substrate. A gate structure is formed within the ILD and disposed on the semiconductor substrate, wherein the gate structure includes a high-k dielectric material layer and a metal gate stack....

09/18/14 - 20140264479 - Methods of increasing space for contact elements by using a sacrificial liner and the resulting device
One method includes forming a sidewall spacer adjacent a gate structure, forming a first liner layer on the sidewall spacer, forming a second liner layer on the first liner layer, forming a first layer of insulating material above the substrate and adjacent the second liner layer, selectively removing at least...

09/18/14 - 20140264480 - Semiconductor device and method of forming the same
A method of forming a semiconductor device includes the following steps. At first, a semiconductor substrate is provided, and a metal gate structure and a first dielectric layer are disposed on the semiconductor substrate, wherein a top surface of the metal gate structure is aligned with a top surface of...

09/18/14 - 20140264481 - Plug structure and process thereof
A plug structure including a first dielectric layer, a second dielectric layer, a barrier layer and a second plug is provided. The first dielectric layer having a first plug therein is located on a substrate, wherein the first plug physically contacts a source/drain in the substrate. The second dielectric layer...

09/18/14 - 20140264482 - Carbon-doped cap for a raised active semiconductor region
After formation of a disposable gate structure, a raised active semiconductor region includes a vertical stack, from bottom to top, of an electrical-dopant-doped semiconductor material portion and a carbon-doped semiconductor material portion. A planarization dielectric layer is deposited over the raised active semiconductor region, and the disposable gate structure is...

09/18/14 - 20140264483 - Metal gate structures for field effect transistors and method of fabrication
The present invention relates to combinations of materials and fabrication techniques which are useful in the fabrication of filled, metal-comprising gates for use in planar and 3D Field Effect Transistor (FET) structures. The FET structures described are of the kind needed for improved performance in semiconductor device structures produced at...

09/18/14 - 20140264484 - Fluorine-doped channel silicon-germanium layer
Methods for forming P-type channel metal-oxide-semiconductor field effect transistors (PMOSFETs) with improved interface roughness at the channel silicon-germanium (cSiGe) layer and the resulting devices are disclosed. Embodiments may include designating a region in a substrate as a channel region, forming a cSiGe layer above the designated channel region, and implanting...

09/18/14 - 20140264485 - Fin-type semiconductor device
An apparatus comprises a substrate and a fin-type semiconductor device extending from the substrate. The fin type semiconductor device comprises a fin that comprises a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second...

09/18/14 - 20140264486 - Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
One method includes forming a recessed gate/spacer structure that partially defines a spacer/gate cap recess, forming a gate cap layer in the spacer/gate cap recess, forming a gate cap protection layer on an upper surface of the gate cap layer, and removing portions of the gate cap protection layer, leaving...

09/18/14 - 20140264487 - Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned...

09/18/14 - 20140264488 - Methods of forming low defect replacement fins for a finfet semiconductor device and the resulting devices
One illustrative device disclosed herein includes a substrate fin formed in a substrate comprised of a first semiconductor material, wherein at least a sidewall of the substrate fin is positioned substantially in a <100> crystallographic direction of the crystalline structure of the substrate, a replacement fin structure positioned above the...

09/18/14 - 20140264489 - Wrap around stressor formation
For the formation of a stressor on one or more of a source and drain defined on a fin of FINFET semiconductor structure, a method can be employed including performing selective epitaxial growth (SEG) on one or more of the source and drain defined on the fin, separating the fin...

09/18/14 - 20140264490 - Replacement gate electrode with a self-aligned dielectric spacer
A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions....

09/18/14 - 20140264491 - Semiconductor strips with undercuts and methods for forming the same
An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first...

09/18/14 - 20140264492 - Counter-doped low-power finfet
FinFETs and methods for making FinFETs are disclosed. A fin is formed on a substrate, wherein the fin has a height greater than 2 to 6 times of its width, a length defining a channel between source and drain ends, and the fin comprises a lightly doped semiconductor. A conformally...

09/18/14 - 20140264493 - Semiconductor device and fabricating the same
A semiconductor device includes a substrate, a gate stack having at least one gate vertex directed to an area in the substrate below the gate stack. The semiconductor device also includes a source structure having at least one vertex directed toward the area in the substrate and a drain structure...

09/18/14 - 20140264494 - Metal-oxide-semiconductor field-effect transistor with metal-insulator semiconductor contact structure to reduce schottky barrier
A method includes depositing a first metal layer on a native SiO2 layer that is disposed on at least one of a source and a drain of a metal-oxide-semiconductor field-effect transistor (MOSFET). A metal oxide layer is formed from the native SiO2 layer and the first metal layer, wherein the...

09/18/14 - 20140264495 - Self-aligned liner method of avoiding pl gate damage
A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The...

09/18/14 - 20140264496 - Stress enhanced finfet devices
A non-planar semiconductor with enhanced strain includes a substrate and at least one semiconducting fin formed on a surface of the substrate. A gate stack is formed on a portion of the at least one semiconducting fin. A stress liner is formed over at least each of a plurality of...

09/18/14 - 20140264497 - Self-aligned approach for drain diffusion in field effect transistors
A method for doping terminals of a field-effect transistor (FET), the FET including a drain region, a source region, and a surround gate surrounding a channel region, the method including depositing a dopant-containing layer, such that the surround gate prevents the dopant-containing layer from contacting the channel region of the...

09/18/14 - 20140264498 - Memory device and method of manufacturing the same
A memory device includes a gate structure, a contact plug, and a spacer. The gate structure includes first and second conductive layer patterns sequentially stacked on a substrate. The contact plug passes through the second conductive layer pattern, and a sidewall of the contact plug directly contacts at least a...

09/18/14 - 20140264499 - Semiconductor devices having dielectric caps on contacts and related fabrication methods
Semiconductor device structures are provided. An exemplary semiconductor device structure includes a substrate of a semiconductor material and a gate structure overlying the substrate. The semiconductor substrate further includes a doped region formed in the substrate proximate the gate structure and a first dielectric material overlying the doped region. The...

09/11/14 - 20140252423 - Semiconductor device having metal gate and manufacturing method thereof
A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench and the second semiconductor device includes a second gate trench. A first work...

09/11/14 - 20140252424 - Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
One method discloses performing an etching process to form a contact opening in a layer of insulating material above at least a portion of a source/drain, region wherein, after the completion of the etching process, a portion of a gate structure of the transistor is exposed, selectively forming an oxidizable...

09/11/14 - 20140252425 - Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
One method includes performing a first etching process to form a contact opening in a layer of insulating material that exposes a portion of a gate structure of the transistor, performing a second etching process on the exposed portion of the gate structure to thereby define a gate recess, selectively...

09/11/14 - 20140252426 - Semiconductor structure with dielectric-sealed doped region
Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are...

09/11/14 - 20140252427 - Self-aligned contacts for replacement metal gate transistors
Embodiments of the invention include methods of forming gate caps. Embodiments may include providing a semiconductor device including a gate on a semiconductor substrate and a source/drain region on the semiconductor substrate adjacent to the gate, forming a blocking region, a top surface of which extends above a top surface...

09/11/14 - 20140252428 - Semiconductor fin structures and methods for forming the same
An integrated circuit structure includes a semiconductor substrate, an insulation region extending into the semiconductor substrate, and a semiconductor strip between two opposite portions of the insulation region. The semiconductor strip includes an upper portion higher than top surfaces of the insulation regions and a lower portion in the insulation...

09/11/14 - 20140252429 - Contact geometry having a gate silicon length decoupled from a transistor length
Methods for forming a semiconductor device are provided. In one embodiment, a gate structure having a gate insulating layer and a gate electrode structure formed on the gate insulating layer is provided. The methods provide reducing a dimension of the gate electrode structure relative to the gate insulating layer along...

09/11/14 - 20140252430 - Electronic device including a dielectric layer having a non-uniform thickness and a process of forming the same
An electronic device can include a transistor having a drain region, a source region, a dielectric layer, and a gate electrode. The dielectric layer can have a first portion and a second portion, wherein the first portion is relatively thicker and closer to the drain region; the second portion is...

09/11/14 - 20140252431 - Semiconductor device structure and method of forming same
An embodiment is a semiconductor device comprising a first gate structure over a semiconductor substrate, a first etch stop layer (ESL) over the semiconductor substrate and the first gate, the first ESL having a curved top surface, and a first inter-layer dielectric (ILD) on the first ESL, the first ILD...

09/11/14 - 20140252432 - Semiconductor device and method for forming the same
A semiconductor device includes a substrate and a gate structure formed over the substrate. The semiconductor device further includes an insulator feature formed in the substrate. The insulator feature includes an insulating layer and a capping layer over the insulating layer....

09/11/14 - 20140252433 - Multi-layer metal contacts
A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, the first-layer contact extending to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the...

09/11/14 - 20140252434 - Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device includes forming isolation layers in a first direction at trenches at isolation regions defined at a semiconductor substrate and forming gate lines in a second direction crossing the first direction over the isolation layers and active regions defined between the isolation layers, performing...

09/11/14 - 20140252435 - Semiconductor device
A semiconductor device concerning an embodiment is provided with a plate-like semiconductor substrate, electrode pads, electrode connecting conductors, and a source electrode back pad. The semiconductor substrate has a first cutout section in a first side, and has a second cutout section and a third cutout section in a second...

09/11/14 - 20140252436 - Semiconductor device
There is provided a semiconductor device with basic electronic elements in a three-dimensional structure. The semiconductor device has a source region and a drain region each of which includes an electrode and a silicide region, and is formed with a plurality of different crystal planes. The silicide regions on different...

09/04/14 - 20140246709 - Semiconductor device having a spacer and a liner overlying a sidewall of a gate structure and method of forming the same
A semiconductor device includes a gate structure over a substrate. The device further includes an isolation feature in the substrate and adjacent to an edge of the gate structure. The device also includes a spacer overlying a sidewall of the gate structure. The spacer has a bottom lower than a...

09/04/14 - 20140246710 - Cyclic deposition etch chemical vapor deposition epitaxy to reduce epi abnormality
A semiconductor substructure with an improved source/drain structure is described. The semiconductor substructure can include an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structure is disposed over...

09/04/14 - 20140246711 - Semiconductor device, method of manufacturing the same, method of manufacturing display unit, and method of manufacturing electronic apparatus
A semiconductor device includes: a gate electrode and a wiring; a first insulating film covering the gate electrode and the wiring; a semiconductor film opposed to the gate electrode with the first insulating film in between; a first concave section located in a position adjacent to the semiconductor film; a...

09/04/14 - 20140246712 - Integrated circuit metal gate structure having tapered profile
A device having a gate where the profile of the gate provides a first width at a top region and a second width at a bottom region is described. The gate may include tapered sidewalls. The gate may be a metal gate structure....

08/28/14 - 20140239354 - Finfets and methods for forming the same
A finFET and methods for forming a finFET are disclosed. A structure comprises a substrate, a fin, a gate dielectric, and a gate electrode. The substrate comprises the fin. The fin has a major surface portion of a sidewall, and the major surface portion comprises at least one lattice shift....

08/28/14 - 20140239355 - Fin field-effect transistors and fabrication method thereof
A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate; and forming a plurality of fins on top of the semiconductor substrate. The method also includes forming isolation structures between adjacent fins; and forming doping sidewall spacers in top portions of the isolation...

08/28/14 - 20140239356 - Semiconductor device
A semiconductor device concerning an embodiment is provided with a semiconductor layer, an impurity-doped layer selectively formed on the semiconductor layer, and a drain electrode formed on the impurity-doped layer. The semiconductor device is further provided with a source electrode which is formed and isolated from the drain electrode, and...

08/28/14 - 20140239357 - Thin film transistor on fiber and manufacturing method of the same
Provided is a thin film transistor on fiber and a method of manufacturing the same. The thin film transistor includes a fiber; a first electrode, a second electrode and a gate electrode formed on fiber; a channel formed between the first and second electrodes; an encapsulant encapsulating the fiber, the...

08/28/14 - 20140239358 - Nonplanar device with thinned lower body portion and method of fabrication
A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top...

08/28/14 - 20140239359 - Semiconductor device
A gate electrode (4) and a source electrode (5) of a semiconductor chip (3) are connected to a gate terminal (7) and a source terminal (9), respectively, via electric conductors (11a and 11b). A portion of the gate terminal (7) which portion is joined to the electric conductor (11a) is...

08/21/14 - 20140231885 - Integrated circuits and methods for fabricating integrated circuits having metal gate electrodes
Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a sacrificial gate structure over a semiconductor substrate. The sacrificial gate structure includes two spacers and sacrificial gate material between the two spacers. The method recesses a portion...

08/14/14 - 20140225168 - Methods of forming a three-dimensional semiconductor device with a dual stress channel and the resulting device
One method includes forming first and second spaced-apart trenches extending at least partially into a semiconducting substrate defining a fin structure for the device, forming a stress-inducing material having a first type of stress in the first trench, forming a second stress-inducing material in the second trench, the second stress-inducing...

08/14/14 - 20140225169 - Gate all around semiconductor device
A gate all around (GAA) type semiconductor device is provided. The GAA type semiconductor device includes source/drain layers formed to be spaced apart from each other, a channel layer connecting the source/drain layers, and a gate electrode formed along the periphery of at least a portion of the channel layer,...

08/14/14 - 20140225170 - Semiconductor device and method of manufacturing the same
In one embodiment, a semiconductor device includes a first diffusion layer of a first conductivity type and a second diffusion layer of a second conductivity type that are provided in a semiconductor layer at a distance, the second conductivity type being an opposite conductivity type of the first conductivity type,...

08/14/14 - 20140225171 - Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device
Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device are disclosed. The techniques may be realized as a semiconductor memory device. The semiconductor memory device may comprise a substrate comprising an upper layer, an array of dummy pillars formed on the upper layer of...