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Having Insulated Electrode (e.g., Mosfet, Mos Diode)

Having Insulated Electrode (e.g., Mosfet, Mos Diode) patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

Related Categories:

Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)


Field Effect Device > Having Insulated Electrode (e.g., Mosfet, Mos Diode)



Transistor and method for forming the same
04/23/15 - 20150108550 - A method for forming a transistor is provided. The method includes: forming a channel layer over a substrate; patterning the channel layer to form a recess; and forming a source layer in the recess, such that at least a portion of the channel layer protrudes to form the fin-type channel....

Method of making a finfet device
04/23/15 - 20150108551 - A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. The method includes forming a mandrel features over a substrate, the mandrel feature and performing a coarse cut to remove one or more mandrel features to form a coarse space. After the coarse cut, the substrate is etched...

Semiconductor device
04/23/15 - 20150108552 - In a cross section in a channel width direction, a semiconductor layer includes a first region of which one end portion is in contact with an insulating layer and which is positioned at one side portion of the semiconductor layer; a second region of which one end portion is in...

Semiconductor device
04/23/15 - 20150108553 - A manufacturing method for a semiconductor device includes providing a substrate having at least agate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on...

Advanced forming method and structure of local mechanical strained transistor
04/23/15 - 20150108554 - Embodiments of the invention provide a semiconductor fabrication method and a structure for strained transistors. A method comprises forming a stressor layer over a MOS transistor. The stressor layer is selectively etched over the gate electrode, thereby affecting strain conditions within the MOSFET channel region. An NMOS transistor may have...

Finfets and methods for forming the same
04/16/15 - 20150102392 - A FinFET and methods for forming a FinFET are disclosed. A method includes forming a semiconductor fin on a substrate, implanting the semiconductor fin with dopants, and forming a capping layer on a top surface and sidewalls of the semiconductor fin. The method further includes forming a dielectric on the...

Fin-type field effect transistor and manufacturing method thereof
04/16/15 - 20150102393 - A FinFET device includes a gate dielectric layer on a substrate, a fin on the gate dielectric layer having a middle section and source and drain regions at opposite ends, and a gate structure on the middle section of the fin. The FinFET device also includes a trench in a...

Semiconductor attenuated fins
04/09/15 - 20150097217 - A semiconductor device includes a semiconductor substrate and attenuated semiconductor fins (e.g. FinFET fins) that include an outer portion that is a composite of a first material and a second material, an inner portion that is the second material, and an attenuation portion that is an attenuated composite of the...

Semiconductor device with non-linear surface
04/09/15 - 20150097218 - A semiconductor device includes a first channel having a first linear surface and a first non-linear surface. The semiconductor device includes a first dielectric region surrounding the first channel. The semiconductor device includes a second channel having a third linear surface and a third non-linear surface. The semiconductor device includes...

Hybrid phase field effect transistor
04/02/15 - 20150091067 - An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is...

Gate electrode with a shrink spacer
04/02/15 - 20150091068 - A method of forming a semiconductor device including forming a dielectric material layer on a semiconductor layer, forming a gate electrode material layer on the dielectric material layer, forming mask features on the gate electrode material layer, forming a spacer layer on and at sidewalls of the mask features and...

Multi-fin finfets with merged-fin source/drains and replacement gates
03/26/15 - 20150084101 - A semiconductor structure including semiconductor fins, a gate over a middle portion of the semiconductor fins, and faceted semiconductor regions outside of the gate separated from gaps may be formed. The semiconductor structure may be formed by forming fins on a semiconductor substrate where each fin has a pair of...

Semiconductor device
03/26/15 - 20150084102 - The semiconductor device including: a semiconductor layer extending in a first direction, the semiconductor layer including a pair of source/drain regions and a channel region, a gate extending on the semiconductor layer to cover the channel region, and a gate dielectric layer interposed between the channel region and the gate,...

Semiconductor device and method for manufacturing the same
03/26/15 - 20150084103 - A semiconductor device includes: a Si substrate having first and second major surfaces facing in opposite directions; a buffer layer of AlxGa1-xN (0≦x≦1) on the first major surface of the Si substrate; an epitaxially grown crystalline layer of AlyGa1-yN (0≦y≦1, x≠y) on the buffer layer; a transistor on the epitaxially...

Method of manufacturing a semiconductor device and the semiconductor device
03/26/15 - 20150084104 - Characteristics of a high electron mobility transistor are improved. A stack having an n-type contact layer (n-type AlGaN layer), an electron supply layer (undoped AlGaN layer), and a channel layer (undoped GaN layer) is formed in a growth mode over a Ga plane parallel with a [0001] crystal axis direction....

Method for manufacturing insulated gate field effect transistor
03/26/15 - 20150084105 - An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above...

Semiconductor device
03/19/15 - 20150076569 - A semiconductor device is provided. The semiconductor device includes an active fin region, at least a gate strip, and a dummy fin region. The active fin region comprises at least an active fin. The gate strip is formed on the active fin region and extending across the active fin. The...

Semiconductor module and method for manufacturing the same
03/19/15 - 20150076570 - There is provided a semiconductor module and a method for manufacturing the same which make it possible to joint the electrode of the bare-chip transistor and the wiring pattern on the substrate by solder mounting operation, in the same process of solder mounting operation for mounting the bare-chip transistor or...

Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processes
03/19/15 - 20150076571 - A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator....

Transistor fabrication technique including sacrificial protective layer for source/drain at contact location
03/12/15 - 20150069473 - Techniques are disclosed for transistor fabrication including a sacrificial protective layer for source/drain (S/D) regions to minimize contact resistance. The sacrificial protective layer may be selectively deposited on S/D regions after such regions have been formed, but prior to the deposition of an insulator layer on the S/D regions. Subsequently,...

Isolation structure of fin field effect transistor
03/12/15 - 20150069474 - The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material,...

Semiconductor device with reduced electrical resistance and capacitance
03/12/15 - 20150069475 - A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The channel region is separated a...

Semiconductor device and manufacturing method of the same
03/05/15 - 20150060958 - A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate and a stacked structure vertically formed on the substrate. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers, and the conductive layers and the insulating layers...

Eliminating fin mismatch using isolation last
03/05/15 - 20150060959 - An embodiment fin field-effect transistor (FinFET) includes an inner fin, and outer fin spaced apart from the inner fin by a shallow trench isolation (STI) region, an isolation fin spaced apart from the outer fin by the STI region, the isolation fin including a body portion, an isolation oxide, and...

Methods of forming contact structures on finfet semiconductor devices and the resulting devices
03/05/15 - 20150060960 - A method includes forming a raised isolation structure with a recess above a substrate, forming a gate structure above the fin, forming a plurality of spaced-apart buried fin contact structures within the recess that have an outer perimeter surface that contacts at least a portion of an interior perimeter surface...

Finfet device and method of forming fin in the same
03/05/15 - 20150060961 - A method for manufacturing a fin for a FinFET device includes providing a semiconductor substrate, forming a plurality of implanted regions in the semiconductor substrate, and epitaxially forming fins between two adjacent implanted regions. The method also includes forming an insulating structure between two adjacent fins....

Finfet device with channel epitaxial region
02/26/15 - 20150054039 - The present disclosure relates to a Fin field effect transistor (FinFET) device having epitaxial enhancement structures, and an associated method of fabrication. In some embodiments, the FinFET device has a semiconductor substrate having a plurality of isolation regions overlying the semiconductor substrate. A plurality of three-dimensional fins protrude from a...

Finfets with strained well regions
02/26/15 - 20150054040 - A device includes a substrate, insulation regions extending into the substrate, a first semiconductor region between the insulation regions and having a first valence band, and a second semiconductor region over and adjoining the first semiconductor region. The second semiconductor region has a compressive strain and a second valence band...

Method of manufacturing a semiconductor device using source/drain epitaxial overgrowth for forming self-aligned contacts without spacer loss and a semiconductor device formed by same
02/19/15 - 20150048428 - A method for manufacturing a semiconductor device comprises growing a source/drain epitaxy region over a plurality of gates on a substrate, wherein a top surface of the source/drain epitaxy region is at a height above a top surface of each of the plurality of gates, forming at least one opening...

Sidewall image transfer with a spin-on hardmask
02/19/15 - 20150048429 - Semiconductor devices and sidewall image transfer methods with a spin on hardmask. Methods for forming fins include forming a trench through a stack of layers that includes a top and bottom insulator layer, and a layer to be patterned on a substrate; isotropically etching the top and bottom insulator layers;...

Sidewall image transfer with a spin-on hardmask
02/19/15 - 20150048430 - Semiconductor devices include a first and a second set of parallel fins, each set of fins having a same number of fins and a pitch between adjacent fins below a minimum pitch of an associated lithography process, where a spacing between the first and second set of fins is greater...

Method for forming a contact on a semiconductor substrate and semiconductor device
02/19/15 - 20150048431 - A method for forming a contact on a semiconductor substrate includes: applying a metal to an exposed partial area of an outer side of the semiconductor substrate and/or of a layer applied to the semiconductor substrate, the partial area being surrounded by at least one edge region of an insulating...

Fin field effect transistor and method for forming the same
02/12/15 - 20150041867 - Various embodiments provide FinFETs and methods for forming the same. In an exemplary method, a semiconductor substrate having sacrificial layers formed thereon is provided. First sidewall spacers and second sidewall spacers are sequentially formed on both sides of each sacrificial layer. The sacrificial layers can be removed. A first width...

Self aligned contact with improved robustness
02/12/15 - 20150041868 - A semiconductor device is provided that includes a gate structure that is present on a channel portion of a semiconductor substrate that is present between a source region and a drain region. The gate structure includes at least a gate conductor and a gate sidewall spacer that is adjacent to...

Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
02/12/15 - 20150041869 - One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned...

Nitride spacer for protecting a fin-shaped field effect transistor (finfet) device
02/05/15 - 20150035016 - Approaches for protecting a semiconductor device (e.g., a fin field effect transistor device (FinFET)) using a nitride spacer are provided. Specifically, a nitride spacer is formed over an oxide and a set of fins of the FinFET device to mitigate damage during subsequent processing. The nitride spacer is deposited before...

Contact structure of semiconductor device
02/05/15 - 20150035017 - The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface; a fin structure extending upward from the substrate major surface, wherein the fin structure comprises a first fin, a second fin, and a third fin...

Devices and methods of forming bulk finfets with lateral seg for source and drain on dielectrics
02/05/15 - 20150035018 - Devices and methods for forming semiconductor devices with FinFETs are provided. One intermediate semiconductor device includes, for instance: a substrate with at least one fin with at least one channel; at least one gate over the channel; at least one hard-mask over the gate; and at least one spacer disposed...

Method of forming fins from different materials on a substrate
02/05/15 - 20150035019 - A method of forming fins of different materials includes providing a substrate with a layer of a first material having a top surface, masking a first portion of the substrate leaving a second portion of the substrate exposed, etching a first opening at the second portion, forming a body of...

Systems and methods for fabricating semiconductor devices at different levels
02/05/15 - 20150035020 - Systems and methods are provided for fabricating semiconductor device structures on a substrate. For example, a substrate including a first region and a second region is provided. One or more first semiconductor device structures are formed on the first region. One or more semiconductor fins are formed on the second...

Misfet device and method of forming the same
02/05/15 - 20150035021 - Embodiments of the present disclosure include a method for forming a semiconductor device, a method for forming a MISFET device, and a MISFET device. An embodiment is a method for forming a semiconductor device, the method including forming a source/drain over a substrate, forming a first etch stop layer on...

Semiconductor device having passing gate and method for fabricating the same
02/05/15 - 20150035022 - A semiconductor device includes passing gates. In the semiconductor device, a passing gate formed in a device isolation film is vertically positioned at a deeper and lower level than an operation gate formed in an active region defined by the device isolation film such that the passing gate does not...

Semiconductor device and method for fabricating the same
02/05/15 - 20150035023 - A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the...

Transistor and method of manufacturing the same
02/05/15 - 20150035024 - A transistor includes a substrate, a gate structure and impurity regions. The substrate is divided into a field region and an active region by an isolation layer pattern. The field region has the isolation layer pattern thereon, and the active region has no isolation layer pattern thereon. The gate structure...

Semiconductor integrated circuit devices including gates having connection lines thereon
02/05/15 - 20150035025 - Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are...

Middle-of-line borderless contact structure and method of forming
02/05/15 - 20150035026 - Various embodiments disclosed include semiconductor structures and methods of forming such structures. In one embodiment, a method includes: providing a semiconductor structure including: a substrate; at least one gate structure overlying the substrate; and an interlayer dielectric overlying the substrate and the at least one gate structure; removing the ILD...

Zram heterochannel memory
01/29/15 - 20150028397 - Approaches for zero capacitance memory cells are provided. A method of manufacturing a semiconductor structure includes forming a channel region by doping a first material with a first type of impurity. The method includes forming source/drain regions by doping a second material with a second type of impurity different than...

Dielectric filler fins for planar topography in gate level
01/29/15 - 20150028398 - An array of stacks containing a semiconductor fins and an oxygen-impermeable cap is formed on a semiconductor substrate with a substantially uniform areal density. Oxygen-impermeable spacers are formed around each stack, and the semiconductor substrate is etched to vertically extend trenches. Semiconductor sidewalls are physically exposed from underneath the oxygen-impermeable...

Semiconductor devices and methods of manufacturing the same
01/29/15 - 20150028399 - Provided are semiconductor devices and methods of manufacturing the same. The methods include providing a substrate including a first region and a second region, forming first mask patterns in the first region, and forming second mask patterns having an etch selectivity with respect to the first mask patterns in the...

Semiconductor device
01/29/15 - 20150028400 - A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE...

Charge compensation semiconductor devices
01/22/15 - 20150021670 - A field-effect semiconductor device includes a semiconductor body having a first surface and an edge, an active area, and a peripheral area between the active area and the edge, a source metallization on the first surface and a drain metallization. In the active area, first conductivity type drift portions alternate...

Field-effect transistor and method of manufacturing thereof
01/22/15 - 20150021671 - According to this GaN-based HFET, resistivity ρ of a semi-insulating film forming a gate insulating film is 3.9×109 Ωcm. The value of this resistivity ρ is a value derived when the current density is 6.25×10−4 (A/cm2). By inclusion of the gate insulating film by a semi-insulating film having a resistivity...

Contact for high-k metal gate device
01/22/15 - 20150021672 - An integrated circuit having an improved gate contact and a method of making the circuit are provided. In an exemplary embodiment, the method includes receiving a substrate. The substrate includes a gate stack disposed on the substrate and an interlayer dielectric disposed on the gate stack. The interlayer dielectric is...

Semiconductor device and manufacturing method thereof
01/22/15 - 20150021673 - A semiconductor device includes a substrate that has a surface. The semiconductor further includes a fin disposed on the surface and including a semiconductor member. The semiconductor further includes a spacer disposed on the surface, having a type of stress, and overlapping the semiconductor member in a direction parallel to...

Uniform height replacement metal gate
01/08/15 - 20150008488 - A method of manufacturing a semiconductor structure includes forming a raised source-drain region in a semiconductor substrate adjacent to a dummy gate and forming a chemical mechanical polish (CMP) stop layer over the gate structure and above a top surface of the semiconductor substrate. A first ILD layer is formed...

Fin-type field effect transistor and method of fabricating the same
01/08/15 - 20150008489 - A fin-type field effect transistor includes a first fin including a first source, a first drain, and a first channel. The fin-type field effect transistor includes a second fin including a second source, a second drain, and a second channel. The fin-type field effect transistor includes a first semiconductor region...

Fluctuation resistant finfet
01/08/15 - 20150008490 - This improved, fluctuation resistant FinFET, with a doped core and lightly doped epitaxial channel region between that core and the gate structure, is confined to the active-gate span because it is based on a channel structure having a limited extent. The improved structure is capable of reducing FinFET random doping...

Metal gate structure
01/08/15 - 20150008491 - A device comprises a metal gate structure in a trench and over a substrate, wherein the gate structure comprises a first metal sidewall in the trench, wherein the first metal sidewall becomes progressively thinner towards an upper portion of the first metal sidewall, a second metal sidewall in the trench,...

Semiconductor device and method of manufacturing same
01/08/15 - 20150008492 - According to one embodiment, a semiconductor device of a junctionless structure includes a semiconductor layer of a first conductivity type. A pair of source/drain electrodes at a distance is on the semiconductor layer. A gate insulating film is on the semiconductor layer between the source/drain electrodes. A gate electrode is...

Bulk finfet with partial dielectric isolation featuring a punch-through stopping layer under the oxide
01/01/15 - 20150001591 - A bulk finFET with partial dielectric isolation is disclosed. The dielectric isolation is disposed underneath the channel, and essentially bounded by the channel, such that it does not extend laterally beyond the channel under the source and drain regions. This allows increased volume of SiGe source and drain stressor regions...

Semiconductor device with self-protecting fuse and method of fabricating the same
01/01/15 - 20150001592 - A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature...

Method for forming multi-gate device with dual channel
01/01/15 - 20150001593 - The present disclosure relates a Fin field effect transistor (FinFET) device having large effective oxide thickness that mitigates hot carrier injection, and an associated method of formation. In some embodiments, the FinFET device has a conductive channel of a first fin protruding from a planar substrate. The conductive channel has...

Forming tunneling field-effect transistor with stacking fault and resulting device
01/01/15 - 20150001594 - Methods for forming stacking faults in sources, or sources and drains, of TFETs to improve tunneling efficiency and the resulting devices are disclosed. Embodiments may include designating areas within a substrate that will subsequently correspond to a source region and a drain region, selectively forming a stacking fault within the...

Finfet with multiple concentration percentages
01/01/15 - 20150001595 - An apparatus of a semiconductor is provided wherein the apparatus comprises a substrate, a stack, and a fin. The substrate supports the stack and the substrate comprises a first material. The stack provides for the fin and the stack comprises: a strain induced in the stack via the substrate; the...

Radiation tolerant dummy gate-assisted n-mosfet, and method and apparatus for modeling channel of semiconductor device
01/01/15 - 20150001596 - The DGA n-MOSFET layout of the present invention can properly operate in a radioactive environment by blocking leakage current paths that may be created by radiation. Hence, the DGA n-MOSFET layout can be applied to design of electronic components operable in radioactive environments, such as outer space, planetary exploration, and...

Substantially planar electronic devices and circuits
01/01/15 - 20150001597 - A method of manufacturing a substantially planar electronic device is disclosed. The method employs a resist having three different thicknesses used for defining different structures in a single masking step. Exemplary structures are substantially planar transistors having side-gates and diodes....

Divot-free planarization dielectric layer for replacement gate
01/01/15 - 20150001598 - After formation of a silicon nitride gate spacer and a silicon nitride liner overlying a disposable gate structure, a dielectric material layer is deposited, which includes a dielectric material that is not prone to material loss during subsequent exposure to wet or dry etch chemicals employed to remove disposable gate...

Power semiconductor package with non-contiguous, multi-section conductive carrier
01/01/15 - 20150001599 - In one implementation, a power semiconductor package includes a non-contiguous, multi-section conductive carrier. A control transistor with a control transistor terminal is coupled to a first section of the multi-section conductive carrier, while a sync transistor with a sync transistor terminal is coupled to a second section of the multi-section...

Semiconductor structure and manufacturing method thereof
12/25/14 - 20140374805 - A manufacturing method for a semiconductor device first provides a substrate having at least a first transistor formed thereon. The first transistor includes a first conductivity type. The first transistor further includes a first metal gate and a protecting layer covering sidewalls of the first metal gate. A portion of...

Four terminal transistor
12/25/14 - 20140374806 - A transistor includes a substrate, a first electrically conductive material layer positioned on the substrate, and a first electrically insulating material layer is positioned on the first electrically conductive material layer. A gate includes a second electrically conductive material and a reentrant profile in which a first portion of the...

Method of device isolation in cladding si through in situ doping
12/25/14 - 20140374807 - Aspects of the present invention relate to an approach for forming an integrated circuit having a set of fins on a silicon substrate, with the set of fins being formed according to a predetermined pattern. In situ doping of the fins with an N-type dopant prior to deposition of an...