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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device Field Effect DeviceField Effect Device patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/17/08 - 20080012047 - Two-terminal nanotube devices and systems and methods of making same A two terminal switching device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes a stimulus circuit in electrical communication with at least one ... 12/13/07 - 20070284622 - Phase-change memory device Disclosed is a phase-change memory device including a phase-change material pattern, a diffusion barrier layer, a bottom electrode and a top electrode. The phase-change material pattern is placed on the bottom electrode, and the diffusion barrier layer containing tellurium is placed on the phase-change material pattern. The top electrode containing ... 11/22/07 - 20070267660 - Method and apparatus for forming a semiconductor substrate with a layer structure of activated dopants Methods of forming semiconductor devices with a layered structure of thin and well defined layer of activated dopants, are disclosed. In a preferred method, a region in a semiconductor substrate is amorphized, after which the region is implanted with a first dopant at a first doping concentration. Then a solid ... 11/15/07 - 20070262353 - Semiconductor device and method of fabricating the same A semiconductor device according to an embodiment of the present invention includes: a square pole-shaped channel portion made from a first semiconductor layer formed on a substrate, and surrounded with four side faces; a gate electrode formed on a first side face of the channel portion, and a second side ... 11/01/07 - 20070252175 - Floating body transistor constructions, semiconductor constructions, and methods of forming semiconductor constructions The invention includes floating body transistor constructions containing U-shaped semiconductor material slices. The U-shapes have a pair of prongs joined to a central portion. Each of the prongs contains a source/drain region of a pair of gatedly-coupled source/drain regions, and the floating bodies of the transistors are within the central ... 10/11/07 - 20070235770 - Semiconductor structure and fabricating method thereof A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor ... 10/11/07 - 20070235769 - Structure and method for thermally stressing or testing a semiconductor device A structure is provided which includes at least one semiconductor device and a diffusion heater in a continuous active semiconductor area of a substrate. One or more semiconductor devices are provided in a first region of the active semiconductor area and a diffusion heater is disposed adjacent thereto which consists ... 10/04/07 - 20070228421 - Semiconductor device using semiconductor nanowire and display apparatus and image pick-up apparatus using the same A semiconductor device, comprising a semiconductor nanowire having a first region with one of a PN junction and a PIN junction and a second region with a field effect transistor structure, a pair of electrodes connected to both ends of the semiconductor nanowire, and a gate electrode provided in at ... 09/27/07 - 20070221960 - Semiconductor memory device and manufacturing method thereof A semiconductor memory device includes: a semiconductor substrate; a first impurity region; a second impurity region; a channel region; a first gate formed on a main surface on a side of the first impurity region; a second gate formed on the main surface on a side of the second impurity ... 09/27/07 - 20070221959 - Structure and method for fabricating recessed channel mosfet with fanned out tapered surface raised source/drain A raised source/drain field effect transistor has a surface of a raised source/drain that tapers downward in a direction of a gate electrode that is also included within the field effect transistor. The downward tapered surface is preferably an end surface. Due to the downward taper, the field effect transistor ... 09/20/07 - 20070215908 - Electronic device including a semiconductor fin and a process for forming the electronic device An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can ... 09/13/07 - 20070210341 - Periphery design for charge balance power devices A charge balance semiconductor power device comprises an active area having strips of p pillars and strips of n pillars arranged in an alternating manner, the strips of p and n pillars extending along a length of the active area. A non-active perimeter region surrounds the active area, and includes ... 09/13/07 - 20070210340 - Gaas power transistor A GaAs power transistor unit cell is provided with one of its transistor contacts on its bottom surface, and its other two transistor contacts on its frontside surface. In one arrangement, the GaAs power transistor unit cell has a N+ GaAs substrate that cooperates with an N− GaAs material to ... 09/13/07 - 20070210339 - Shared contact structures for integrated circuits In one embodiment, a shared contact structure electrically connects a gate, a diffusion region, and another diffusion region. The shared contact structure may comprise a trench that exposes the gate, the diffusion region, and the other diffusion region. The trench may be filled with a metal to form electrical connections. ... 09/13/07 - 20070210338 - Charge storage structure formation in transistor with vertical channel region A semiconductor device includes a semiconductor structure having a first sidewall. A vertical channel region is formed in the semiconductor structure along the first sidewall between a first current electrode region and a second current electrode region. First and second charge storage structures are formed adjacent to the first sidewall ... 09/06/07 - 20070205437 - Method for the production of a semiconductor substrate comprising a plurality of gate stacks on a semiconductor substrate, and corresponding semiconductor structure A semiconductor structure having a plurality of gate stacks on a semiconductor substrate provided with a gate dielectric. The gate stacks have a lower first layer made of polysilicon, an overlying second layer made of a metal silicide, and an upper third layer made of an insulating material, and a ... 09/06/07 - 20070205436 - Flash memory cell with split gate structure and method for forming the same A split gate memory cell. A floating gate is disposed on and insulated from a substrate comprising an active area separated by a pair of isolation structures formed therein. The floating gate is disposed between the pair of isolation structures and does not overlap the upper surface thereof. A cap ... 08/09/07 - 20070181913 - Integrated circuit device A commercially mass-produced, integrated circuit including: a solid substrate of one conductivity type; at least one solid material pocket of a different conductivity type having a side surface and positioned on a selected top surface of the substrate to thereby form a signal-translating, electronic rectifying barrier between the at least ... 07/26/07 - 20070170469 - Ldmos device with improved esd performance A semiconductor device includes a first doped region disposed on a first well in a semiconductor substrate; a second doped region disposed on a second well adjacent to the first well in the semiconductor substrate, the second doped region having a dopant density higher than that of the second well; ... 07/19/07 - 20070164319 - Silicon pillars for vertical transistors In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas ... 07/12/07 - 20070158695 - System with meshed power and signal buses on cell array A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The ... 07/12/07 - 20070158692 - Semiconductor device The present invention provides a semiconductor device capable of suppressing current collapse, and also of preventing dielectric breakdown voltage and gain from lowering so as to perform high-voltage operation and realize an ideal high output. On a substrate (101), there are formed a buffer layer (102) made of a first ... 06/28/07 - 20070145418 - Devices without current crowding effect at the finger's ends ESD protection devices without current crowding effect at the finger's ends. It is applied under MM ESD stress in sub-quarter-micron CMOS technology. The ESD discharging current path in the NMOS or PMOS device structure is changed by the proposed new structures, therefore the MM ESD level of the NMOS and ... 06/28/07 - 20070145417 - High voltage semiconductor device having a lateral channel and enhanced gate-to-drain separation A semiconductor device having a lateral channel with contacts on opposing surfaces thereof. The semiconductor device includes a conductive substrate having a source contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes an isolation layer above the conductive substrate, a lateral channel above the ... 06/28/07 - 20070145416 - Semiconductor device A semiconductor device comprises on a surface of a first semiconductor layer of the first conduction type a second semiconductor layer of the first conduction type. A semiconductor base layer of the second conduction type is formed on the second semiconductor layer, and a semiconductor diffusion layer of the first ... 06/28/07 - 20070145415 - High-frequency semiconductor device A semiconductor device operating at a frequency between 0.8 GHz and 300 GHz includes an active region that is positioned on a semi-insulating GaAs substrate; a gate electrode that is positioned in the active region; and a source electrode and a drain electrode that are positioned on the surface of ... 06/14/07 - 20070131973 - Flash memory device and method of manufacturing the same Disclosed is a flash memory device. The flash memory device includes a plurality of trench lines in an isolation region of a semiconductor device, a common source region along a word line (WL) direction under a surface portion of the semiconductor substrate, a plurality of gate lines along a vertical ... 06/14/07 - 20070131972 - Semiconductor devices and methods of manufacture thereof Methods of forming transistors and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece, a gate dielectric disposed over the workpiece, and a thin layer of conductive material disposed over the gate dielectric. A layer of semiconductive material is disposed over the thin layer of ... 06/07/07 - 20070126032 - Fin field effect transistor and method for manufacturing fin field effect transistor The invention is directed to a method for manufacturing a fin field effect transistor including a fully silicidated gate electrode. The method is suitable for a substrate including a fin structure, a straddle gate, a source/drain region and a dielectric layer formed thereon, wherein the straddle gate straddles over the ... 06/07/07 - 20070126031 - Semiconductor integrated circuit and method of manufacturing the same Conventional capacitors constituted of a FET incur degradation in frequency response. A semiconductor integrated circuit includes a semiconductor substrate, an N-type FET, a P-type FET, and capacitors. The N-type FET includes N-type impurity diffusion layers, a P-type impurity-implanted region, a gate insulating layer, and a gate electrode. The P-type FET ... 05/31/07 - 20070120151 - Non-volatile memory A NVM including a substrate, a control gate layer, a charge storage layer, a tunneling layer, a charge barrier layer, a gate dielectric layer and a first doping region is described. The control gate layer is disposed in a first trench of the substrate; the charge storage layer is disposed ... 05/31/07 - 20070120150 - Semiconductor component arrangement and method for fabricating it A semiconductor component arrangement is disclosed. In one embodiment, the semiconductor component arrangement includes a power transistor formed within a semiconductor layer in at least one first region and further semiconductor components formed at least in a second region, an effective thickness of the semiconductor layer being smaller in the ... 05/24/07 - 20070114572 - Gate structure including multi-tunneling layer and method of fabricating the same, non-volatile memory device and method of fabricating the same Provided is a gate structure including a multi-tunneling layer and method of fabricating the same. Also provided is a nanodot semiconductor memory device including such gate structure and method of fabricating the same. The gate structure may include a first insulation layer, a second insulation layer, a charge storage layer ... 05/24/07 - 20070114571 - Semiconductor chip and semiconductor device A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according ... 05/17/07 - 20070108474 - Semiconductor device and method of fabricating the same A semiconductor device includes a semiconductor substrate formed with a plurality of trenches, a plurality of trench capacitor type DRAM unit cells including capacitors formed in the trenches and cell transistors formed to be adjacent to the trenches respectively, a plurality of impurity doped regions including boundaries connecting the trenches ... 05/17/07 - 20070108473 - Semiconductor optical sensors An optical sensor and method for forming the same. The optical sensor structure includes (a) a semiconductor substrate, (b) first, second, third, fourth, fifth, and sixth electrodes and (c) first, second, and third semiconducting regions. The first and fourth electrodes are at a first depth. The second and fifth electrodes ... 05/10/07 - 20070102732 - Metal oxide semiconductor device A MOS device includes: a semiconductor substrate; an insulator layer formed on the semiconductor substrate, and including a fluorine-containing titanium dioxide film that has grain boundary defects passivated by fluorine; and upper and lower electrodes formed on the insulator layer and the semiconductor substrate, respectively. ... 05/03/07 - 20070096158 - Pattern layout and layout data generation method A transistor layout including a diffusion region and a gate line. The gate line intersects part of the diffusion region in an overlapping manner. The layout includes an L-shaped bent portion included in the diffusion region. An auxiliary pattern is included in the diffusion region opposite to the L-shaped bent ... 05/03/07 - 20070096157 - Semiconductor device and manufacturing method of the same An object of the present invention is to simplify manufacturing process of an n channel MIS transistor and a p channel MIS transistor with gate electrodes formed of a metal material. For its achievement, gate electrodes of each of the n channel MIS transistor and the p channel MIS transistor ... 04/26/07 - 20070090409 - Semiconductor device comprising an undoped oxide barrier The present invention relates to a semiconductor device comprising at least one gate located in each of a memory array area and a periphery circuit area of a substrate, respectively, wherein the pattern density in the memory array area is higher than that in the periphery circuit area. The semiconductor ... 04/26/07 - 20070090408 - Narrow-body multiple-gate fet with dominant body transistor for high performance A field-effect transistor for a narrow-body, multiple-gate transistor such as a FinFET, tri-gate or Ω-FET is described. The corners of the channel region disposed beneath the gate are rounded n, for instance, oxidation steps, to reduce the comer effect associated with conduction initiating in the corners of the channel region. ... 04/26/07 - 20070090407 - Thin film transistor array substrate and manufacturing method thereof A thin film transistor array substrate and a manufacturing method thereof are provided. Wherein, scan lines and data lines are disposed on a substrate to define a plurality of pixel regions. Thin film transistors are disposed in the pixel regions correspondingly and driven by the scan lines and the data ... 04/26/07 - 20070090406 - Structure and method for manufacturing high performance and low leakage field effect transistor There is provided a field effect transistor (FET) including a source side semiconductor; a drain side semiconductor; and a gate. The source side semiconductor is made of a high mobility semiconductor material, and the drain side semiconductor is made of a low leakage semiconductor material. In one embodiment, the FET ... 04/12/07 - 20070080374 - Semiconductor device Since a power source voltage is generated from a communication signal in a wireless chip, there is a risk that a large amount of voltage be generated in the wireless chip to electrically destroy a circuit in the case of supplying a strong communication signal. Therefore, the present invention is ... 03/29/07 - 20070069244 - Transistor including paramagnetic impurities and having anti-parallel ferromagnetic contacts A transistor device may comprise a source having a first ferromagnetic contact thereto, a drain having a second ferromagnetic contact thereto, an electrically conductive gate positioned over a channel region separating the source and the drain, and an electrically insulating layer disposed between the gate and the channel region. The ... 03/29/07 - 20070069243 - Forming closely spaced electrodes The present invention provides an apparatus and a method of fabricating the apparatus. The apparatus comprises a substrate having a planar surface and first and second electrodes located on the planar surface. The first electrode has a top surface and a lateral surface, and the lateral surface has an edge ... 03/22/07 - 20070063227 - Transistor and cvd apparatus used to deposit gate insulating film thereof In a transistor adapted to suppress characteristic degradation resulting from fluorine contained in a deposited film, the concentration of fluorine contained in a gate insulating film (3) is reduced to 1.0×1020 atoms/cm3 or less. As a result, the transistor can provide excellent reliability even when it is continuously driven for ... 03/22/07 - 20070063226 - Laser irradiation apparatus and laser irradiation method It is an object of the present invention to provide a laser irradiation apparatus and a laser irradiation method which can conduct a laser process homogeneously to the whole surface of a semiconductor film. A laser beam oscillated from a laser crystal having a wide wavelength range and a beam ... 03/15/07 - 20070057292 - Sonos type non-volatile semiconductor devices and methods of forming the same A SONOS type non-volatile semiconductor device includes a semiconductor substrate, source/drain regions doped with impurities formed in the semiconductor substrate, a channel region formed in the semiconductor substrate between the source/drain regions, a tunnel insulation layer formed on the channel region, a charge-trapping layer formed on the tunnel insulation layer, ... 03/15/07 - 20070057291 - Reference voltage generation circuit, and constant voltage circuit using the reference voltage generation circuit A reference voltage generation circuit includes: a first field-effect transistor that is an n channel-type field-effect transistor of a depletion-type, wherein one terminal of the first field-effect transistor is connected to a predetermined power source voltage; a second field-effect transistor including a concentrated n-type gate, wherein one terminal of the ... 03/15/07 - 20070057290 - Field effect transistor An object of the present invention is to provide a normally-off type field effect transistor which includes: a first semiconductor layer which is made of a first hexagonal crystal with 6 mm symmetry and has a main surface including a C-axis of the first hexagonal crystal; a second semiconductor layer ... 02/22/07 - 20070040191 - Nanowire structures and electrical devices The present invention provides structures and devices comprising conductive segments and conductance constricting segments of a nanowire, such as metallic, superconducting or semiconducting nanowire. The present invention provides structures and devices comprising conductive nanowire segments and conductance constricting nanowire segments having accurately selected phases including crystalline and amorphous states, compositions, ... 02/08/07 - 20070029577 - Field effect transistor and method of manufacturing the same A field effect transistor includes a first semiconductor region of a first conduction type, a gate electrode formed on the channel region of the first semiconductor region via a gate insulating film, source and drain electrodes formed to interpose the channel region, second semiconductor regions of a second conduction type ... 01/25/07 - 20070018202 - High performance mosfet comprising stressed phase change material and method of fabricating the same The present invention relates to semiconductor devices that each comprises at least one field effect transistor (FET) containing an intrinsically stressed phase change material layer. The intrinsically stressed phase change material layer is arranged and constructed for creating stress in the channel region of the FET. Preferably, the intrinsically stressed ... 01/18/07 - 20070012952 - Segmented magnetic shielding elements A second shield layer, under the master shielding layer, is added to a segmented MRAM array. This additional shielding is patterned so as to provide one shield per bit slice. The placement of longitudinal biasing tabs at the ends of these segmented shields ensures that each segmented shield is a ... 01/04/07 - 20070001198 - Semiconductor device and method for forming the same The present invention is related to semiconductor device and method for manufacturing the same. In accordance with the semiconductor device and method for manufacturing the same, at least one opening extending between LDD regions and exposing a buried insulating layer is formed so that a gate electrode surrounds the surface ... 12/21/06 - 20060284214 - Thin film fuse phase change cell with thermal isolation layer and manufacturing method A memory device comprising a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first electrode ... 11/23/06 - 20060261375 - Power semiconductor component with plate capacitor structure A power semiconductor component (1) contains a weakly doped drift zone (9), a drain zone (10) and a MOS structure (12) situated at the front side (2) of the power semiconductor component (1). An edge plate (6) of the first conductivity type is provided at its edge (8) above the ... 11/16/06 - 20060255368 - Single electron transistor having memory function and method of manufacturing the same A single electron transistor having a memory function and a fabrication method thereof are disclosed. In the single electron transistor, a first substrate and an insulation film are sequentially stacked, a second substrate is stacked on the insulation film and includes a source region, a channel region, and a drain ... 11/02/06 - 20060244014 - Nonvolatile memory device and method of forming same In a method of forming a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory device, a plurality of first gates may be formed on a semiconductor substrate. A plurality of charge storage spacers may be formed on the plurality of first gates so that a given charge storage spacer may be disposed on ... 10/26/06 - 20060237750 - Field effect transistor structures An embodiment of the present invention provides a structure comprising a field effect transistor (FET) comprising: at least one source rail with at least one source finger; at least one drain rail with at least one drain finger; and at least one serpentine gate having a plurality of gate fingers, ... 10/19/06 - 20060231866 - Method and circuit arrangement for setting an initial value on a charge-storage element A method is provided for setting an initial value on a charge-storage element. A circuit includes at least one charge-storage element with at least one signal node coupled to at least one reset circuit that is associated with the charge-storage element. A diode can be included between the charge-storage element ... 09/28/06 - 20060214193 - Field effect transistor A FET includes a nitride semiconductor in which leak current is reduced and breakdown voltage is improved. The FET is formed from a substrate, a buffer layer made of a nitride semiconductor, a first semiconductor layer made of a nitride semiconductor, and a second semiconductor layer made of a nitride ... 09/28/06 - 20060214192 - Field effect transistor, electrical device array and method for manufacturing those A field effect transistor of the present invention includes: a gate electrode formed on a substrate; a gate insulation layer formed on the gate electrode: a source electrode and a drain electrode that are formed on the gate insulation layer; a n-type semiconductor layer including carbon nanotube, formed between the ... 09/14/06 - 20060202234 - Semiconductor device and manufacturing method thereof A semiconductor device includes a field effect transistor and a strain generating layer to apply a stress to a channel region of the field effect transistor. The strain generating layer contains at least one of oxygen and nitrogen of 1.0×1018 cm−3 to 5.0×1019 cm−3, or alternatively, the strain generating layer ... 09/14/06 - 20060202233 - Semiconductor device and manufacturing method thereof A semiconductor device is disclosed. The semiconductor device includes a semiconductor layer having a channel region, a strain generating layer to cause strain in the channel region by applying a stress to the channel region, a gate insulating film formed on the channel region, and a gate electrode formed on ... 09/07/06 - 20060197112 - Optical coupling device In various aspects, an optical coupling device may include a light emitting element configured to emit an optical signal; a photo receiving element having a serial connected of photo diodes, the photo receiving element configured to receive the optical signal and generate an electrical signal; and a control circuit having ... 08/03/06 - 20060170006 - Semiconductor device and method of manufacturing the same An MIS transistor includes a gate electrode located to intersect a device region of a semiconductor substrate isolated by a device isolation region, and source and drain regions formed in the semiconductor substrate at both sides of the gate electrode region and elevated source and drain located above the source ... 07/20/06 - 20060157743 - Borderless contact structures A borderless contact structure and method of fabricating the structure, the method including: (a) providing a substrate; (b) forming a polysilicon line on the substrate, the polysilicon line having sidewalls; (c) forming an insulating sidewall layer on the sidewalls of the polysilicon line; (d) removing a portion of the polysilicon ... 07/20/06 - 20060157742 - Semiconductor device with epitaxial c49-titanium silicide (tisi2) layer and method for fabricating the same The present invention relates to a semiconductor device with an epitaxially grown titanium silicide layer having a phase of C49 and a method for fabricating the same. This titanium silicide layer has a predetermined interfacial energy that does not transform the phase of the titanium layer, and thus, occurrences of ... 07/20/06 - 20060157741 - Semiconductor device including gate insulation film that is formed of pyroceramics, and method of manufacturing the same A semiconductor device includes a gate insulation film that is formed of pyroceramics including an amorphous matrix layer, which is provided on a major surface of a silicon substrate, and crystalline phases lines with a high dielectric constant, which are dispersed in the amorphous matrix layer. The semiconductor device further ... 07/13/06 - 20060151811 - Floating gate memory device and method of manufacturing the same Disclosed herein is a method of forming a floating gate in a non-volatile memory device having a self-aligned shallow trench isolation (SA-STI) structure. First, a tunnel oxide layer is formed on a semiconductor substrate having a SA-STI structure. Next, a first floating gate layer is formed on the tunnel oxide ... 07/06/06 - 20060145195 - Backgated finfet having different oxide thicknesses A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, which may be introduced ... 07/06/06 - 20060145194 - Method for creating a functional interface between a nanoparticle, nanotube or nanowire, and a biological molecule or system A field effect transistor and a method for making the same. In one embodiment, the field effect transistor comprises a source; a drain; a gate; at least one carbon nanotube on the gate; and a dielectric layer that coats the gate and a portion of the at least one carbon ... 06/29/06 - 20060138469 - Semiconductor device and fabricating method thereof A semiconductor device and fabricating method thereof can prevent an electrical characteristic degradation of the semiconductor device when a boarderless type contact is formed. The device may include a transistor on a semiconductor substrate, an oxynitride layer on the semiconductor sustrate,an insulating interlayer on the oxynitride layer, a metal line ... 06/29/06 - 20060138468 - Semiconductor device with increased channel length and method for fabricating the same A semiconductor device with an increased channel length and a method for fabricating the same are provided. The semiconductor device includes: a substrate with an active region including a planar active region and a prominence active region formed on the planar active region; a gate insulation layer formed over the ... 06/08/06 - 20060118829 - Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern Disclosed is a method of fabricating a field effect transistor. In the method, a gate stack on a top surface of a semiconductor substrate is formed, and then a first spacer is formed on a sidewall of the gate stack. Next, a silicide self-aligned to the first spacer is deposited ... 06/08/06 - 20060118828 - In plane switching mode liquid crystal display device A method for fabricating an in-plane switching LCD device includes forming a data line and a light-shielding layer on a substrate, forming a pixel electrode line and an active region with a polycrystalline silicon thin film, forming a first insulating layer on the substrate, forming a gate electrode and a ... 06/01/06 - 20060113570 - Implanting carbon to form p-type source drain extensions The use of a carbon implant, in addition to the conventional fluorine implant, may significantly reduce the transient enhanced diffusion in P-type source drain extension regions. As a result, resistivity may be reduced, and dopant density may be increased, increasing current drive in some embodiments. ... 06/01/06 - 20060113569 - Control of threshold voltage in organic field effect transistors A field effect transistor (FET) includes a substrate, and a gate layer formed on the substrate. An oxygen plasmarized polymeric gate dielectric is formed on the gate layer so as to increase the threshold voltage of the OFET. A semiconductor layer is formed on the oxygen plasmarized polymeric gate dielectric. ... 05/25/06 - 20060108610 - Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer ... 05/25/06 - 20060108609 - Barrier dielectric stack for seam protection The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal dielectric passivation stack positioned on at least the gate conductor sidewalls, the conformal dielectric ... 05/25/06 - 20060108608 - Hetero bipolar transistor The invention relates to a heterobipolar transistor, comprising an emitter which includes a first semiconductor layer (8) made of a first semiconductor material and a second semiconductor layer (9) made of a second semiconductor material, a band gap value of the first semiconductor material being smaller than a band gap ... 05/11/06 - 20060097289 - Method of forming ultra shallow junctions A method of forming ultra shallow junctions in p-type devices uses aluminum ion to implant n-doped silicon, followed a low temperature anneal to activate and diffuse the aluminum. The use of aluminum provides numerous advantages over boron such as the ability to form shallower junctions, lower resistivity, and the ability ... 05/04/06 - 20060091428 - Structure and method for forming the gate electrode in a multiple-gate transistor In a method of forming semiconductor device, a semiconductor fin is formed on a semiconductor-on-insulator substrate. A gate dielectric is formed over at least a portion of the semiconductor fin. A first gate electrode material is formed over the gate dielectric and a second gate electrode material is formed over ... 05/04/06 - 20060091427 - Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device A semiconductor device comprising a substrate having a first crystal orientation and an insulating layer overlying the substrate is provided. A plurality of silicon layers are formed overlying the insulating layer. A first silicon layer comprises silicon having the first crystal orientation and a second silicon layer comprises silicon having ... 04/27/06 - 20060086954 - Multi-layer film stack for extinction of substrate reflections during patterning A method including introducing a dielectric layer over a substrate between an interconnection line and the substrate, the dielectric layer comprising a plurality of alternating material layers; and patterning an interconnection to the substrate. An apparatus comprising a substrate comprising a plurality of devices formed thereon; and an interlayer dielectric ... 04/27/06 - 20060086953 - Twin-ono-type sonos memory A twin-ONO-type SONOS memory includes a semiconductor substrate having a source region, a drain region and a channel region between the source and drain regions, twin silicon oxide-silicon nitride-silicon oxide (ONO) dielectric layers, a first ONO dielectric layer being on the channel region and the source region and as second ... 04/20/06 - 20060081886 - Method, system and apparatus for gating configurations and improved contacts in nanowire-based electronic devices Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and ... 04/20/06 - 20060081885 - Field effect transistor with electroplated metal gate Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate ... 04/13/06 - 20060076580 - Image sensor with vertically integrated thin-film photodiode An image sensor with a vertically integrated thin-film photodiode includes a bottom doped layer of a PIN photodiode imbedded in a dielectric layer, wherein a bottom surface of the bottom doped layer completely contacts its corresponding underlying pixel electrode. The bottom doped layers of the PIN photodiodes are formed by ... 04/13/06 - 20060076579 - Semiconductor transistor having structural elements of differing materials A transistor is formed using a semiconductor substrate and forming a control electrode overlying the semiconductor substrate. A first current electrode is formed within the semiconductor substrate and adjacent the control electrode. The first current electrode has a first predetermined semiconductor material. A second current electrode is formed within the ... 03/16/06 - 20060054937 - Semiconductor devices having an interfacial dielectric layer and related methods A semiconductor device includes a semiconductor substrate including silicon and an oxide layer on the substrate. The oxide layer includes silicon. An interfacial dielectric layer is disposed on the oxide layer opposite the substrate. The interfacial dielectric layer includes HfO2, ZrO2, a zirconium silicate alloy, and/or a hafnium silicate alloy ... 03/09/06 - 20060049430 - Field-effect transistor, complementary field-effect transistor, and method of manufacturing field-effect transistor For this purpose, on a single-crystal silicon substrate 101 having a {100} plane as a principal surface are formed a gate electrode 107 extending substantially in a <010> crystal axis direction of the single-crystal silicon or an axis direction equivalent to the <010> crystal axis direction, and in both sides ... 03/09/06 - 20060049429 - Field effect transistor (fet) having wire channels and method of fabricating the same In a field effect transistor (FET), and a method of fabricating the same, the FET includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a plurality of wire channels electrically connecting the source and drain regions, the plurality of wire channels being arranged in two columns ... 03/09/06 - 20060049428 - Tft electronic devices and their manufacture An electronic device (70) comprises a thin film transistor (TFT) (9,59), the TFT including a channel (16) defined in a layer of polycrystalline semiconductor material (10,48). The polycrystalline semiconductor material is produced by crystallising amorphous semiconductor material (2) using metal atoms (6) to promote the crystallisation process. The polycrystalline semiconductor ... 03/02/06 - 20060043431 - Memory array with overlapping buried digit line and active area and method for forming same A memory cell, array and device include an active area formed in the substrate with a vertical transistor including a first end disposed over a first portion of the active area. The vertical transistor is formed as an epitaxial post on the substrate surface, extends from the surface of the ... 03/02/06 - 20060043430 - Transistor having an asymmetric source/drain and halo implantation region and a method of forming the same By providing an asymmetric design of a halo region and extension regions of a field effect transistor, the transistor performance may significantly be enhanced for a given basic transistor architecture. In particular, a large overlap area may be created at the source side with a steep concentration gradient of the ... 03/02/06 - 20060043429 - Contact structure and contact liner process A contact structure and a method of forming thereof for semiconductor devices or assemblies are described. The method provides process steps to create a contact structure encompassed by a sacrificial contact medium having an opening therein that is lined with a conductive spacer liner that effectively prevents the contact structure ... 02/16/06 - 20060033125 - Transistor with nitrogen-hardened gate oxide An improved surface P-channel transistor includes providing a semiconductor substrate, forming a gate oxide layer over the semiconductor substrate, subjecting the gate oxide layer to a remote plasma nitrogen hardening treatment followed by an oxidative anneal, and forming a polysilicon layer over the resulting gate oxide layer. Significantly, the present ... 01/26/06 - 20060017071 - Semiconductor integrated circuit There is provided a high-performance semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a switch block for switching connections among a plurality of signal lines by means of a plurality ... 01/26/06 - 20060017070 - Semiconductor device A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region ... 01/05/06 - 20060001052 - Dual-sided capacitor and method of formation A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of hemispherical grained polysilicon (HSG) as part of a dual-sided lower capacitor electrode. Prior to the dielectric formation, the lower capacitor electrode may be ... 01/05/06 - 20060001051 - Thin film semiconductor circuit, manufacturing method thereof, and image display apparatus utilizing the same thin film semiconductor circuit Agglomeration of a polycrystalline silicon film is eliminated at the time of obtaining a high quality polycrystalline silicon film by forming a silicon layer on an insulating film substrate and conducting long-term melting and re-crystallization. For this purpose, a layer or a plurality of layers of an underlayer UCL are ... 01/05/06 - 20060001050 - High voltage fet gate structure A FET device for operation at high voltages includes a substrate, a first well and a second well within the substrate that are doped with implants of a first type and second type, respectively. The first and second wells define a p-n junction. A field oxide layer within the second ... 12/29/05 - 20050285151 - Active matrix type display apparatus and a driving device of a load An active matrix type display device having a plurality of pixel circuits (1) arranged in a matrix shape. The pixel circuit has: a display device (EL); a drive transistor (M1) of a first conductivity type for controlling a current flowing in the display device; a capacitor (C1) provided at a ... 12/29/05 - 20050285150 - Field effect transistor, transistor arrangement and method for producing a semiconducting monocrystalline substrate and a transistor arrangement In order to insulate active areas of n-type FETs (91) and p-type FETs (92), insulator structures (21n, 21p, 22n, 22p) which due to production exert a tensile stress or a compressive stress on the respectively neighboring active areas (11n, 11p), and which stress them accordingly, are provided in the semiconductor ... 12/22/05 - 20050280041 - Device manufacturing method and device, electro-optic device, and electronic equipment A device manufacturing method, including: a first process for providing the plural elements on the original substrate via a separation layer in a condition where terminal sections are exposed to a surface on an opposite side to the separation layer; a second process for adhering the surface where the terminal ... 12/22/05 - 20050280040 - Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof. At least the top magnetic material layer of a magnetic stack is patterned using a hard mask, and a conformal insulating material is deposited over the patterned top magnetic material layer and hard mask. The conformal ... 12/15/05 - 20050274986 - Solution processed devices A method for forming a transistor, comprising: depositing a first material from solution in a first solvent to form a first layer of the transistor; and subsequently whilst the first material remains soluble in the first solvent, forming a second layer of the transistor by depositing over the first material ... 12/15/05 - 20050274985 - Rf decoupled field plate for fets A field effect transistor structure having a field effect transistor; a field plate disposed between a gate electrode of the transistor and a drain electrode of the transistor; and a resistive interconnect electrically connected between the gate electrode and the field plate. With such an arrangement, the field plate is ... 12/08/05 - 20050269601 - Semiconductor device The semiconductor device comprises: a semiconductor substrate (N+ substrate 110) containing a first conductivity type impurity implanted therein; a second conductivity type impurity-implanted layer (P+ implanted layer 114) at relatively high concentration, formed on the semiconductor substrate (N+ substrate 110); a second conductivity type impurity epitaxial layer (P− epitaxial layer ... 12/08/05 - 20050269600 - Integrated field-effect transistor comprising two control regions, use of said field-effect transistor and method for producing the same An integrated field-effect transistor is described in which a substrate region is surrounded by: two terminal regions (a source region and a drain region), two electrically insulating insulating layers, two electrically insulating regions, and an electrically conductive connecting region. The insulating layers are arranged at mutually opposite sides of the ... 12/01/05 - 20050263795 - Semiconductor device having a channel layer and method of manufacturing the same In a method of forming a semiconductor device having an improved channel layer, the channel layer is formed on a surface of a semiconductor substrate and comprises a material of high carrier mobility such as silicon germanium (SiGe), germanium (Ge) and silicon carbide (SiC) using a selective epitaxial growth process. ... 11/24/05 - 20050258456 - Memory with integrated programmable controller An internal processing capability is added to a computer memory by adding a small processor, a small amount of processor RAM memory, a small amount of non-volatile memory, and some logic. During wafer testing the internal processor system allows the memory to be tested at full speed and substantially simultaneously ... 11/24/05 - 20050258455 - Semiconductor component A semiconductor component has a first and a second contact-making region, and a semiconductor volume arranged between the first and the second contact-making region. Within the semiconductor volume, it is possible to generate a current flow that runs from the first contact-making region to the second contact-making region, or vice ... 11/10/05 - 20050247961 - Chemical sensor using semiconducting metal oxide nanowires Indium oxide nanowires are used for determining information about different chemicals or Biologics. Chemicals are absorbed to the surface of the nanowires, and cause the semiconducting characteristics of the Nanowires to change. These changed characteristics are sensed, and used to determine either the presence of the materials and/or the concentration ... 10/27/05 - 20050236652 - Mfs type field effect transistor, its manufacturing method, ferroelectric memory and semiconductor device A MFS type field effect transistor includes a semiconductor layer, a PZT system ferroelectric layer formed on the semiconductor layer, a gate electrode formed on the PZT system ferroelectric layer, and an impurity layer composing a source or a drain, formed in the semiconductor layer. The PZT system ferroelectric layer ... 10/20/05 - 20050230713 - Single-electron transistor for detecting biomolecules A single-electron transistor includes a projecting feature, such as a pyramid, that projects from a face of a substrate. A first electrode is provided on the substrate face that extends onto the projecting feature. A second electrode is provided on the substrate face that extends onto the projecting feature and ... 09/29/05 - 20050212014 - Semiconductor device and semiconductor sensor A semiconductor device includes a substrate; a gate electrode formed on the substrate; a gate insulating film covering the gate electrode; a carbon nanotube disposed above the gate electrode and coming in contact with the gate insulating film; and a source electrode and a drain electrode formed apart from one ... 09/22/05 - 20050205897 - High voltage insulated-gate transistor An insulated-gate transistor, includes a semiconductor material layer having a front surface, a body region, an insulated gate disposed over the body region with interposition of a gate dielectric, and a source and drain region, the source region formed in the body region and the drain region formed in the ... 09/22/05 - 20050205896 - Transistor with dopant-bearing metal in source and drain A transistor and method of manufacturing thereof. A gate dielectric and gate are formed over a workpiece, and the source and drain regions of a transistor are recessed. The recesses are filled with a dopant-bearing metal, and a low-temperature anneal process is used to form doped regions within the workpiece ... 09/15/05 - 20050199915 - Semiconductor integrated circuit and method of redesigning same A semiconductor integrated circuit has a first functional block, a second functional block, and a signal line routed from the first functional block to the second functional block in a metal interconnection layer. A complementary pair of metal-oxide-semiconductor circuits with source, gate, and drain terminals are located near the signal ... 09/08/05 - 20050194616 - Transistor and method of forming the same According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover ... 09/08/05 - 20050194615 - Organic thin-film transistor and method for manufacturing the same An organic thin-film transistor and a method for manufacturing the same are described. The method forms a gate layer on a substrate, an insulator layer on the substrate, forming a semiconductor layer on the insulator layer, and a strip for defining a channel length on the semiconductor layer. An electrode ... 09/01/05 - 20050189571 - Ferroelectric memory A ferroelectric memory includes a memory cell array in which memory cells having a ferroelectric capacitor are arranged in a matrix shape. The memory cell array includes a ferroelectric layer formed out of a thin film made of a Bi layer-structured ferroelectric single crystal having a (001) orientation and which ... 08/25/05 - 20050184316 - Fin field effect transistors having multi-layer fin patterns and methods of forming the same A fin field effect transistor has a fin pattern protruding from a semiconductor substrate. The fin pattern includes first semiconductor patterns and second semiconductor patterns which are stacked. The first and second semiconductor patterns have lattice widths that are greater than a lattice width of the substrate in at least ... 08/18/05 - 20050179063 - Image sensor with vertically integrated thin-film photodiode An image sensor with a vertically integrated thin-film photodiode includes a bottom doped layer of a PIN photodiode imbedded in a dielectric layer, wherein a bottom surface of the bottom doped layer completely contacts its corresponding underlying pixel electrode. The bottom doped layers of the PIN photodiodes are formed by ... 07/28/05 - 20050161707 - Esd-robust power switch and method of using same A power switch comprising a field effect transistor (FET) including an active area in a semiconductor body, a channel formed in said active area and having a periodic structure, source diffusion zones and drain diffusion zones in the active area, a source diffusion zone being separated from a drain diffusion ... 07/21/05 - 20050156204 - Semiconductor device The present invention enhances voltage conversion efficiency of a semiconductor device. In a non-isolated DC-DC converter that includes a high-side switch power MOSFET and a low-side switch power MOSFET, which are series-connected, the high-side switch power MOSFET and driver circuits for driving the high-side and low-side switch power MOSFETs are ... 07/21/05 - 20050156203 - Vertical carbon nanotube-field effect transistor and method of manufacturing the same Provided are a vertical carbon nanotube field effect transistor (CNTFET) and a method of manufacturing the same. The method includes: forming a first electrode on a substrate; forming a stack of multiple layers (“multi-layer stack”) on the first electrode, the multiple layers including first and second buried layers and a ... 07/21/05 - 20050156202 - At least penta-sided-channel type of finfet transistor An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five ... 07/21/05 - 20050156201 - Semiconductor device According to the present invention, there is provided a semiconductor device including a trench gate IGBT, having: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type which is formed on one surface of the first semiconductor layer; a base layer of ... 06/30/05 - 20050139868 - Field effect transistor and method of manufacturing the same There is provided a field effect transistor which is suitable for a power amplifier application or the like, and have a double recess structure with superior repeatability. A film thickness of an AlGaAs layer can determine a depth of a second step of a recess uniquely by using the AlGaAs ... 06/30/05 - 20050139867 - Field effect transistor and manufacturing method thereof The Mott transistor capable of operating at a room temperature can be realized by using a self-organized nanoparticle array for the channel portion. The nanoparticle used in the present invention comprises metal and organic molecules, and the size thereof is extremely small, that is, about a few nm. Therefore, the ... 06/23/05 - 20050133827 - Large-scale trimming for ultra-narrow gates Large-scale trimming for forming ultra-narrow gates for semiconductor devices is disclosed. A hard mask layer on a semiconductor wafer below a patterned soft mask layer on the semiconductor wafer is etched to narrow a width of the hard mask layer. The hard mask layer is trimmed to further narrow the ... 06/16/05 - 20050127407 - Asymmetric field effect transistor A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region formed with the first dopant doping ... 06/09/05 - 20050121699 - Dynamic threshold voltage mosfet on soi Provision of a body control contact adjacent a transistor and between the transistor and a contact to the substrate or well in which the transistor is formed allows connection and disconnection of the substrate of the transistor to and from a zero (ground) or substantially arbitrary low voltage in accordance ... 06/02/05 - 20050116257 - Field effect transister structures A structure comprising a field effect transistor (FET) comprising at least one source rail with at least one source finger, at least one drain rail with at least one drain finger, and at least one serpentine gate having a plurality of gate fingers, said serpentine gate serpentining between said at ... ### FreshPatents.com Support |