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Field Effect Device

Field Effect Device patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)


Field Effect Device



Conformal doping
06/12/14 - 20140159120 - Methods for doping a three-dimensional semiconductor structure are disclosed. A conformal coating is formed on the three-dimensional semiconductor structure by Atomic Layer Deposition, and subsequent annealing causes dopant atoms to migrate into the three-dimensional semiconductor structure. Any residual conformal coating is then removed by etching. The semiconductor can be a...

Semiconductor packages having multiple lead frames and methods of formation thereof
01/09/14 - 20140008702 - In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead frame, which has a second die paddle and a plurality of leads. The second die paddle is disposed over the first die paddle. A...

Nisi rework procedure to remove platinum residuals
09/12/13 - 20130234213 - The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing a rework including applying SPM at a temperature of 130° C. in a SWC tool, if Pt residue is detected. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer,...

Integrated circuits including copper local interconnects and methods for the manufacture thereof
08/01/13 - 20130193489 - Embodiments of a method for manufacturing an integrated circuit are provided. In one embodiment, a partially-fabricated integrated circuit is produced including a semiconductor substrate having source/drain regions, and a plurality of transistors including a plurality of gate conductors formed over the semiconductor substrate and between the source/drain regions. Device-level contacts...

Multi-fin device by self-aligned castle fin formation
05/09/13 - 20130113023 - The present disclosure provides a method includes forming a multi-fin device. The method includes forming a patterned mask layer on a semiconductor substrate. The patterned mask layer includes a first opening having a first width W1 and a second opening having a second width W2 less than the first width....

Circuit simulation method and semiconductor integrated circuit
03/07/13 - 20130056799 - A simulation method of a circuit in which a transistor is formed of a material (e.g., SiGe, etc.) having a lattice constant different from that of a semiconductor substrate, on source and drain regions, an adjacent active region is formed near the transistor, and a gate electrode is formed in...

Semiconductor device and manufacturing method thereof
01/31/13 - 20130026543 - A semiconductor device includes a plurality of active areas disposed on a semiconductor substrate. A manufacturing method of the semiconductor device includes performing a first annealing process on the semiconductor substrate by emitting a first laser alone a first scanning direction, and performing a second annealing process on the semiconductor...

Tsv structure and method for forming the same
01/17/13 - 20130015504 - A TSV structure includes a wafer including a first side and a second side, a through via connecting the first side and the second side, a through via dielectric layer covering the inner wall of the through via, a conductive layer which fills up the through via and consists of...

Multiplying pattern density by single sidewall imaging transfer
11/08/12 - 20120280283 - A method for fabricating an integrated circuit includes patterning a mandrel over a layer to be patterned. Dopants are implanted into exposed sidewalls of the mandrel to form at least two doped layers having at least one undoped region adjacent to the doped layers. The doped layers are selectively etched...

Transistor including reduced channel length
07/12/12 - 20120175684 - A transistor includes a substrate. A first electrically conductive material layer, having a thickness, is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. The second electrically conductive material layer overhangs the first electrically conductive material...

Integrated heat pillar for hot region cooling in an integrated circuit
06/21/12 - 20120153358 - The thermal energy transfer techniques of the disclosed embodiments utilize passive thermal energy transfer techniques to reduce undesirable side effects of trapped thermal energy at the circuit level. The trapped thermal energy may be transferred through the circuit with thermally conductive structures or elements that may be produced as part...

Nickel-silicide formation with differential pt composition
06/21/12 - 20120153359 - Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is...

Interposer and semiconductor device
06/07/12 - 20120139010 - An interposer includes a substrate includes a plurality of penetrating electrodes, and a wiring portion formed on the substrate, in which the wiring portion includes a wiring layer electrically connected to the penetrating electrodes and an insulating layer covering the wiring layer. The interposer includes a plurality of first UBM...

Multi-fin device by self-aligned castle fin formation
04/19/12 - 20120091511 - The present disclosure provides a method includes forming a multi-fin device. The method includes forming a patterned mask layer on a semiconductor substrate. The patterned mask layer includes a first opening having a first width W1 and a second opening having a second width W2 less than the first width....

Soi substrate, method for manufacturing the same, and semiconductor device
02/02/12 - 20120025274 - An SOI substrate having an SOI layer that can be used in practical applications even when a substrate with low upper temperature limit, such as a glass substrate, is used, is provided. A semiconductor device using such an SOI substrate, is provided. In bonding a single-crystal semiconductor layer to a...

Formation of finfet gate spacer
08/18/11 - 20110198673 - Gate spacers are formed in FinFETS having a bottom portion of a first material extending to the height of the fins, and a top portion of a second material extending above the fins. An embodiment includes forming a fin structure on a substrate, the fin structure having a height and...

Non-direct bond copper isolated lateral wide band gap semiconductor device
07/28/11 - 20110180855 - Non-direct bond copper isolated lateral wide band gap semiconductor devices are provided. One semiconductor device includes a heat sink, a buffer layer directly overlying the heat sink, and an epitaxial layer formed of a group-III nitride overlying the buffer layer. Another semiconductor device includes a heat sink, a substrate directly...

Multiplying pattern density by single sidewall imaging transfer
06/02/11 - 20110127582 - A method for fabricating an integrated circuit includes patterning a mandrel over a layer to be patterned. Dopants are implanted into exposed sidewalls of the mandrel to foam at least two doped layers having at least one undoped region adjacent to the doped layers. The doped layers are selectively etched...

Semiconductor device having silicon on stressed liner (sol)
04/14/11 - 20110084315 - A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the...

Embedded silicon germanium source drain structure with reduced silicide encroachment and contact resistance and enhanced channel mobility
03/17/11 - 20110062498 - Semiconductor devices with embedded silicon germanium source/drain regions are formed with enhanced channel mobility, reduced contact resistance, and reduced silicide encroachment. Embodiments include embedded silicon germanium source/drain regions with a first portion having a relatively high germanium concentration, e.g., about 25 to about 35 at. %, an overlying second portion...

Hybrid plasma-semiconductor optoelectronic devices and transistors
02/17/11 - 20110037102 - The invention provides combination semiconductor and plasma devices, including transistors and phototransistors. A preferred embodiment hybrid plasma semiconductor device has active solid state semiconductor regions; and a plasma generated in proximity to the active solid state semiconductor regions. Devices of the invention are referred to as hybrid plasma-semiconductor devices, in...

Forming uniform silicide on 3d structures
01/06/11 - 20110001169 - By using a non-conformal diffusion barrier in conjunction with a similarly deposited non-conformal initial deposition of siliciding material, a substantially uniform and conformal silicide can be formed in a 3D structure such as the fin of a FinFET. The siliciding material may be nickel (Ni), the diffusion barrier may be...

Structure and method of fabricating finfet
09/30/10 - 20100244103 - A CMOS FinFET device and a method of manufacturing the same using a three dimensional doping process is provided. The method of forming the CMOS FinFET includes forming fins on a first side and a second side of a structure and forming spacers of a dopant material having a first...

Design structure for heavy ion tolerant device, method of manufacturing the same and structure thereof
09/23/10 - 20100237389 - The invention relates to a design structure, and more particularly, to a design structure for a heavy ion tolerant device, method of manufacturing the same and a structure thereof. The structure includes a first device having a diffusion comprising a drain region and source region and a second device having...

Electric circuit with vertical contacts
09/16/10 - 20100230727 - An electrical circuit includes at least two unit cells configured on a planar substrate which extends in one plane. The unit cells respectively have at least two contact points with a different function and include at least one dielectric layer disposed on the substrate and/or on the unit cells and...

Nanotube device
09/02/10 - 20100219453 - A device includes a nanotube source electrode located on a surface of a substrate between nanotube gate and nanotube drain electrodes....

Silicon based opto-electric circuits
07/22/10 - 20100181601 - A semiconductor structure, comprising: a substrate; a seed layer over an upper surface of the substrate; a semiconductor layer disposed over the seed layer; a transistor device in the semiconductor layer; wherein the substrate has an aperture therein, such aperture extending from a bottom surface of the substrate and terminating...

Methods and devices for forming nanostructure monolayers and devices including such monolayers
06/24/10 - 20100155786 - Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also...

Optimized device isolation
05/13/10 - 20100117122 - A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the...

Pattern formation in semiconductor fabrication
05/06/10 - 20100109054 - Provided is a semiconductor device. The device includes a substrate having a photo acid generator (PAG) layer on the substrate. The PAG layer is exposed to radiation. A photoresist layer is formed on the exposed PAG layer. The exposed PAG layer generates an acid. The acid decomposes a portion of...

Semiconductor device having a contact plug and manufacturing method thereof
02/25/10 - 20100044757 - There is provided a semiconductor device that includes: a transistor having a gate electrode, a source region, arid a drain region; a first inter-layer insulation film covering the transistor; a first contact plug formed penetrating through the first inter-layer insulation film and connected to either the source region or the...

Field-effect transistor
02/04/10 - 20100025737 - A field-effect transistor according to the present invention includes a source electrode that is formed in an active region, and a drain electrode that is formed in the active region. Further, the field-effect transistor includes a gate electrode that is formed in the active region and disposed between the source...

Semiconductor device
01/07/10 - 20100001322 - The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) comprising silicon which is provided with at least one semiconductor element (T), wherein an epitaxial semiconductor layer (1) comprising silicon is grown on top of a first semiconductor substrate...

Field effect transistor and method of manufacture thereof
12/17/09 - 20090309137 - A field effect transistor comprising a semiconductor substrate comprising an electrically conducting channel layer therein; a plurality of source and drain fingers on a first face of the substrate, each finger separated from the adjacent finger by a gate channel; the gate channels comprising at least one active gate channel...

Methods and devices for fabricating and assembling printable semiconductor elements
12/03/09 - 20090294803 - The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials....

High-efficiency thinned imager with reduced boron updiffusion
12/03/09 - 20090294804 - A method for fabricating a back-illuminated semiconductor imaging device on an ultra-thin semiconductor-on-insulator wafer (UTSOI) is disclosed. The UTSOI wafer includes a mechanical substrate, an insulator layer, and a seed layer. At least one dopant is applied to the semiconductor substrate. A first portion of an epitaxial layer is grown...

Method of doping transistor comprising carbon nanotube, method of controlling position of doping ion, and transistors using the same
10/15/09 - 20090256175 - Provided are a method of doping a carbon nanotube (CNT) of a field effect transistor and a method of controlling the position of doping ions. The method may include providing a source, a drain, the CNT as a channel between the source and the drain, and a gate, applying a...

Super junction semiconductor device
10/08/09 - 20090250727 - In the specification and drawing a super junction semiconductor device is disclosed. The super junction semiconductor device comprises a P-type layer, a N+ substrate, a N-type layer, a silicon dioxide layer and a P+ layer. The N+ substrate is disposed under the P-type layer. The N-type layer is disposed on...

Isolation structure, non-volatile memory having the same, and method of fabricating the same
07/23/09 - 20090184343 - A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the...

Wiring substrate, semiconductor device and manufacturing method thereof
07/16/09 - 20090179230 - The present invention provides a method for forming a wiring having a minute shape on a large substrate with a small number of steps, and further a wiring substrate formed by the method. Moreover, the present invention provides a semiconductor device in which cost reduction and throughput improvement are possible...

Integrated circuitry
07/16/09 - 20090179231 - This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen...

Patterning techniques
05/21/09 - 20090127588 - A method of forming a patterned layer, including the steps of: (i) depositing via a liquid medium a first material onto a substrate to form a first body on said substrate; (ii) depositing via a liquid medium a second material onto said substrate to form a second body, wherein said...

Method for achieving uniform etch depth using ion implantation and a timed etch
05/07/09 - 20090114953 - A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to...