FREE patent keyword monitoring and additional FREE benefits. http://images1.freshpatents.com/images/triangleright (1K) REGISTER now for FREE triangleleft (1K)
FreshPatents.com Logo    FreshPatents.com icons
Monitor Keywords Patent Organizer File a Provisional Patent Browse Inventors Browse Industry Browse Agents

Doping On Side Of Heterojunction With Lower Carrier Affinity (e.g., High Electron Mobility Transistor (hemt))

Doping On Side Of Heterojunction With Lower Carrier Affinity (e.g., High Electron Mobility Transistor (hemt)) patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

Related Categories:

Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)


Heterojunction Device > Field Effect Transistor > Doping On Side Of Heterojunction With Lower Carrier Affinity (e.g., High Electron Mobility Transistor (hemt))



Normally-off-type heterojunction field-effect transistor
12/18/14 - 20140367742 - A normally-off-type HFET includes: an undoped AlwGa1-wN layer of t1 thickness, an undoped AlxGa1-xN layer of t2 thickness and an undoped GaN channel layer of tch thickness that are sequentially stacked; a source electrode and a drain electrode separated from each other and electrically connected to the channel layer; an...

Field effect transistor, and multilayered epitaxial film for use in preparation of field effect transistor
12/18/14 - 20140367743 - In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a...

Cascode structures for gan hemts
12/11/14 - 20140361341 - A multi-stage transistor device is described. One embodiment of such a device is a dual-gate transistor, where the second stage gate is separated from a barrier layer by a thin spacer layer and is grounded through a connection to the source. In one embodiment the thin spacer layer and the...

Recessed field plate transistor structures
12/11/14 - 20140361342 - A transistor device including a field plate is described. One embodiment of such a device includes a field plate separated from a semiconductor layer by a thin spacer layer. In one embodiment, the thickness of spacer layer separating the field plate from the semiconductor layers is less than the thickness...

Cascode structures with gan cap layers
12/11/14 - 20140361343 - A transistor device including a cap layer is described. One embodiment of such a device includes cap layer between a gate and a semiconductor layer. In one embodiment, the thickness of the cap layer is between 5 nm and 100 nm. In another embodiment, the cap layer can be doped,...

High electron mobility bipolar transistor
12/11/14 - 20140361344 - The lattice during the process of epitaxy growth is stabilized and it is possible to prevent the dopants, the elements, the vacancies or the defects from diffusing into the neighboring layers, thereby improving the problem of mobility degradation and resistance increase, and sustaining the stability of the manufacturing process....

Graphene capped hemt device
12/04/14 - 20140353722 - A graphene capped HEMT device and a method of fabricating same are disclosed. The graphene capped HEMT device includes one or more graphene caps that enhance device performance and/or reliability of an exemplary AlGaN/GaN heterostructure transistor used in high-frequency, high-energy applications, e.g., wireless telecommunications. The HEMT device disclosed makes use...

High voltage durability iii-nitride device
12/04/14 - 20140353723 - A high voltage durability III-nitride semiconductor device comprises a support substrate including a first silicon body, an insulator body over the first silicon body, and a second silicon body over the insulator body. The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body characterized by a majority...

Contact metallurgy for self-aligned high electron mobility transistor
11/27/14 - 20140346566 - A metallization scheme employing a first refractory metal barrier layer, a Group IIIA element layer, a second refractory metal barrier layer, and an oxidation-resistant metallic layer is employed to form a source region and a drain region that provide electrical contacts to a compound semiconductor material layer. The first and...

Elemental semiconductor material contactfor high electron mobility transistor
11/27/14 - 20140346567 - Portions of a top compound semiconductor layer are recessed employing a gate electrode as an etch mask to form a source trench and a drain trench. A low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material in the source trench and...

Low temperature ohmic contacts for iii-n power devices
11/27/14 - 20140346568 - The disclosure relates to a method for manufacturing an Au-free ohmic contact for an III-nitride (III-N) device on a semiconductor substrate and to a III-N device obtainable therefrom. The III-N device includes a buffer layer, a channel layer, a barrier layer, and a passivation layer. A 2DEG layer is formed...

Group iii-v device with a selectively reduced impurity concentration
11/20/14 - 20140339605 - There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a...

Method and apparatus for reduced parasitics and improved multi-finger transistor thermal impedance
11/13/14 - 20140332853 - A transistor, a method and an apparatus for forming multiple connections to a transistor for reduced gate (FET/HEMT) or base (BJT/HBT) parasitics, and improved multi-finger transistor thermal impedance. Providing for a method and an apparatus that reduces a transistor's parasitics and reduces a transistor's thermal impedance, resulting in higher device...

Fet dielectric reliability enhancement
11/06/14 - 20140327047 - A semiconductor device may be formed by forming a silicon-containing gate dielectric layer over a semiconductor layer. A gate metal layer is formed over the gate dielectric layer; the gate metal layer includes 2 atomic percent to 10 atomic percent silicon during formation. The gate metal layer is patterned to...

Field-effect transistor
10/30/14 - 20140319582 - A field-effect transistor includes a channel layer in which a two-dimensional electron gas is formed, an electron supply layer located on the channel layer, a source electrode located on the electron supply layer, a drain electrode located on the electron supply layer, a gate electrode located on the electron supply...

High electron mobility transistor and method of forming the same
10/30/14 - 20140319583 - A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is greater than the first band gap. A crystalline interfacial layer is...

Group iii nitride high electron mobility transistor (hemt) device
10/30/14 - 20140319584 - A group III nitride high electron mobility transistor (HEMT) device comprises a source electrode (112), a drain electrode (111), a main gate (116), a top gate (118), an insulating dielectric layer (117) and a heterostructure, wherein the source electrode (112) and the drain electrode (111) are electrically connected via two-dimensional...

Power device chip and method of manufacturing the power device chip
10/02/14 - 20140291728 - According to example embodiments, a power device chip includes a plurality of unit power devices classified into a plurality of sectors, a first pad and a second pad. At least one of the first and second pads is divided into a number of pad parts equal to a number of...

Method of forming a gate contact
09/18/14 - 20140264448 - A method is provided for forming a gate contact for a compound semiconductor device. The gate contact is formed from a gate contact portion and a top or wing contact portion. The method allows for the tunablity of the size of the wing contact portion, while retaining the size of...

Method of forming hemt semiconductor devices and structure therefor
09/18/14 - 20140264449 - In one embodiment, a HEMT semiconductor device includes an isolation region that may include oxygen wherein the isolation region may extend thorough an ALGaN and GaN layer into an underlying layer....

Semiconductor device and manufcturing method thereof
09/18/14 - 20140264450 - A semiconductor device including a substrate, a heterojunction body, a passivation layer, a source contact, a drain contact, and a gate contact. The heterojunction body disposed on or above the substrate includes a first semiconductor layer, a mask layer, a regrowth layer, and a second semiconductor layer. The first semiconductor...

Semiconductor device and method for producing the same, power supply device, and high-frequency amplifier
09/18/14 - 20140264451 - A semiconductor device includes: a nitride semiconductor multilayer; an insulating film disposed on the nitride semiconductor multilayer; and a gate electrode disposed on the insulating film, wherein the nitride semiconductor multilayer has a first oxidized region near an interface with a region of the insulating film below the gate electrode,...

Method of forming a hemt semiconductor device and structure therefor
09/18/14 - 20140264452 - In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality...

Method of forming a high electron mobility semiconductor device and structure therefor
09/18/14 - 20140264453 - In one embodiment, a method of forming a semiconductor device can comprise; forming a HEM device on a semiconductor substrate. The semiconductor substrate provides a current carrying electrode for the semiconductor device and one or more internal conductor structures provide a vertical current path between the semiconductor substrate and regions...

Ohmic contact structure for semiconductor device and method
09/18/14 - 20140264454 - In one embodiment, a high electron mobility device structure includes heterostructure with a Group III-nitride channel layer and a Group III-nitride barrier layer that forms a two-dimensional electron gas layer at an interface between the two layers. At least one current carrying electrode includes a recess-structured conductive contact adjoining and...

Carbon doping semiconductor devices
09/18/14 - 20140264455 - A method of fabricating a semiconductor device can include forming a III-N semiconductor layer in a reactor and injecting a hydrocarbon precursor into the reactor, thereby carbon doping the III-N semiconductor layer and causing the III-N semiconductor layer to be insulating or semi-insulating. A semiconductor device can include a substrate...

Method of forming a high electron mobility semiconductor device
09/18/14 - 20140264456 - In an embodiment, a semiconductor device is formed by a method that includes, providing a base substrate of a first semiconductor material, and forming a layer that is one of SiC or a III-V series material on the base substrate. In a different embodiment, the base substrate may be one...

High mobility, thin film transistors using semiconductor/insulator transition-metaldichalcogenide based interfaces
09/11/14 - 20140252415 - Electronic devices and methods of forming an electronic device are disclosed herein. An electronic device may include a first 2D atomic crystal layer; a second 2D atomic crystal layer disposed atop the first 2D atomic crystal layer; and an interface comprising van-der-Waals bonds between the first 2D atomic crystal layer...

Field effect transitor and semiconductor device using the same
09/11/14 - 20140252416 - An field effect transistor has a plurality of cells provided on a first straight line. Each cell has a plurality of multi-finger electrodes and is connected to a gate terminal electrode and a drain terminal electrode. The multi-finger electrode has at least two finger gate electrodes, a finger drain electrode,...

Semiconductor device and electronic apparatus
09/11/14 - 20140252417 - A semiconductor device includes: a device region having a semiconductor layer that includes a channel section; a device peripheral region adjoining the device region; a gate electrode provided within the device region, and having a boundary section that spans the device region and the device peripheral region; a conductive layer...

Tunnel junction field effect transistors having self-aligned source and gate electrodes and methods of forming the same
09/04/14 - 20140246699 - Methods of forming a transistor include providing a semiconductor epitaxial structure including a channel layer and barrier layer on the channel layer, forming a gate electrode on the barrier layer, etching the semiconductor epitaxial structure using the gate electrode as an etch mask to form a trench in the semiconductor...

Nitride semiconductor device and method for manufacturing same
09/04/14 - 20140246700 - According to one embodiment, a nitride semiconductor device includes a first semiconductor, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a first electrode, a second electrode and a third electrode. The first, second and fourth semiconductor layers include a nitride semiconductor. The second semiconductor layer is...

Methods, devices, and systems related to forming semiconductor power devices with a handle substrate
08/28/14 - 20140239348 - Methods of manufacturing device assemblies, as well as associated semiconductor assemblies, devices, systems are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a semiconductor device assembly that includes a handle substrate, a semiconductor structure having a first side and a second side opposite...

Drain pad having a reduced termination electric field
08/28/14 - 20140239349 - In an exemplary implementation, a semiconductor device includes a drain pad on a semiconductor substrate, the drain pad being coupled to a plurality of drain fingers. The semiconductor device further includes a source pad on the semiconductor substrate, the source pad being coupled to a plurality of source fingers. The...

Nitride semiconductor device
08/21/14 - 20140231873 - A nitride semiconductor device includes a semiconductor multilayer formed on a substrate, a first ohmic electrode and a Schottky electrode spaced apart from each other on the semicnductor multilayer; and a passivation film covering a top of the semiconductor multilayer. The semiconductor multilayer 102 includes a first nitride semiconductor layer,...

Semiconductor device
08/21/14 - 20140231874 - A semiconductor device includes a HEMT and a diode. The HEMT includes: a substrate having a GaN layer as a channel layer generating a two-dimensional electron gas and an AlGaN layer as a barrier layer on the GaN layer; a source electrode on the AlGaN layer ohmic contacting the AlGaN...

Method for fabricating mesa sidewall with spin coated dielectric material and semiconductor element thereof
08/07/14 - 20140217472 - A method for fabricating a mesa sidewall with a spin coated dielectric material and a semiconductor element fabricated by the same are provided in the present invention. The method includes the steps of: disposing an object on a semiconductor substrate; performing a spin coating process to coat with a liquid...

Metamorphic growth of iii-v semiconductor on silicon substrate by mocvd for high speed iii-v transistors
07/31/14 - 20140209979 - A III-V semiconductor device on a silicon substrate is constructed with a silicon (Si) substrate onto which gallium arsenide (GaAs) indium phosphide (InP) and aluminum indium arsenide (AlInAs) to form a structure of AlInAs over InP over GaAs over Si. The GaAs is applied in at least one layer over...

Semiconductor device and method for manufacturing the same
07/31/14 - 20140209980 - A method for manufacturing a semiconductor device includes forming a buffer layer made of a nitride semiconductor, forming a channel layer made of a nitride semiconductor over the buffer layer, forming a barrier layer made of a nitride semiconductor over the channel layer, forming a cap layer made of a...

Nitride electronic device and method for fabricating nitride electronic device
07/24/14 - 20140203329 - Provided is a nitride electronic device having a structure that allows the reduction of leakage by preventing the carrier concentration from increasing in a channel layer. An inclined surface and a primary surface of a semiconductor stack extend along first and second reference planes R1, R2, respectively. The primary surface...

Semiconductor device
07/17/14 - 20140197459 - Semiconductor device comprising a source electrode, a drain electrode and a semiconducting layer consisting of a single or double 2-dimensional layer(s) made from one of the following materials: MoS2, MoSe2, WS2, WSe2, MoTe2 or WTe2....

Semiconductor device, method for manufacturing the same, power supply device, and high-frequency amplifier
07/17/14 - 20140197460 - A semiconductor device includes: a compound semiconductor stack structure including a plurality of compound semiconductor layers stacked over a semiconductor substrate; and a first insulating film covering the surface of the compound semiconductor stack structure, the first insulating film being a silicon nitride film including, on the top side, a...

Semiconductor structure including a spatially confined dielectric region
07/17/14 - 20140197461 - There are disclosed herein various implementations of semiconductor structures including one or more spatially confined dielectric regions. In one exemplary implementation, such a semiconductor structure includes a III-Nitride field-effect transistor (FET) having a drain, a source, and a gate, fabricated over a substrate. A spatially confined dielectric region is formed...

Iii-nitride transistor with high resistivity substrate
07/17/14 - 20140197462 - There are disclosed herein various implementations of semiconductor structures including high resistivity substrates. In one exemplary implementation, such a semiconductor structure includes a substrate having a resistivity of greater than or approximately equal to one kiloohm-centimeter (1 kΩ-cm), and a III-N high electron mobility transistor (HEMT) having a drain, a...

Compressive strained iii-v complementary metal oxide semiconductor (cmos) device
07/10/14 - 20140191286 - A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first...

Compressive strained iii-v complementary metal oxide semiconductor (cmos) device
07/10/14 - 20140191287 - A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first...

Semiconductor device and method for manufacturing semiconductor device
07/10/14 - 20140191288 - A method for manufacturing a semiconductor device includes forming an electron transit layer on a semiconductor substrate, forming an electron supply layer on the electron transit layer, forming a cap layer on the electron supply layer, forming a protection layer on the cap layer, the protection layer having an opening...

Ring-shaped transistors providing reduced self-heating
06/26/14 - 20140175514 - A ring-shaped transistor includes a set of gates. Each gate of the set is disposed between a corresponding source and a corresponding drain. The set of gates are arranged such that all of the set of gates cannot be aligned with fewer than three imaginary straight lines drawn through the...

Nonplanar iii-n transistors with compositionally graded semiconductor channels
06/26/14 - 20140175515 - A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least...

Two-dimensional electron gas sensor and methods for making and using the sensor
06/26/14 - 20140175516 - The disclosed technology generally relates to a sensor and methods for making and using the same, and more particularly relates to a sensor configured to sense the presence of at least one fluidum. In one aspect, a sensor for sensing a fluidum in a space adjoining the sensor comprises a...

Field effect transistor
06/26/14 - 20140175517 - A field effect transistor (FET) disclosed herein comprising a substrate, a C-doped semiconductor layer disposed on the substrate, a channel layer disposed on the C-doped semiconductor layer, and an electron supply layer disposed on the channel layer. The FET further comprises a diffusion barrier layer disposed between the C-doped semiconductor...

Iii-v hemt devices
06/26/14 - 20140175518 - A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band...

Transistor and method of fabricating the same
06/19/14 - 20140167111 - A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a...

Cascode circuit integration of group iii-n and group iv devices
06/19/14 - 20140167112 - In an exemplary implementation, an integrated assembly includes a printed circuit board, and a depletion mode III-Nitride transistor die and a group IV transistor die coupled to the printed circuit board. The depletion mode III-Nitride transistor die is situated on one side of the printed circuit board and the group...

Gallium nitride based semiconductor devices and methods of manufacturing the same
06/19/14 - 20140167113 - Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a heat dissipation substrate (that is, a thermal conductive substrate); a GaN-based multi-layer arranged on the heat dissipation substrate and having N-face polarity; and a heterostructure field effect transistor (HFET) or a...

Method for growing iii-v epitaxial layers
06/19/14 - 20140167114 - Disclosed are methods of growing III-V epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer. A...

Transistor and method of fabricating the same
06/12/14 - 20140159115 - A high electron mobility transistor includes a T-type gate electrode disposed on a substrate between source and drain electrodes and insulating layers disposed between the substrate and the T-type gate electrode. The insulating layers include first, second, and third insulating layers. The third insulating layer is disposed between the substrate...

Iii-nitride device having an enhanced field plate
06/12/14 - 20140159116 - In an exemplary implementation, a semiconductor device includes a III-nitride heterojunction including a III-nitride barrier layer situated over a III-nitride channel layer to form a conduction channel including a two-dimensional electron gas. The semiconductor device further includes a gate electrode coupled to a field plate. The field plate includes a...

Semiconductor device and method of manufacturing the semiconductor device
06/12/14 - 20140159117 - A semiconductor device includes a channel layer; and a high resistance layer that is provided on the channel layer, and is made of a semiconductor with high resistance which has a conduction band position higher than that of the semiconductor which forms the channel layer. The semiconductor device includes a...

Iii-nitride transistor with source-connected heat spreading plate
06/12/14 - 20140159118 - Disclosed are semiconductor devices and methods for manufacturing them. An example device may include a III-nitride stack having a front side surface and a back side surface. The III-nitride stack may be formed of at least a first layer and a second layer, between which a heterojunction may be formed,...

Method for growing iii-v epitaxial layers and semiconductor structure
06/12/14 - 20140159119 - Disclosed are methods of growing III-V epitaxial layers on a substrate, a semiconductor structure comprising a substrate, a device comprising such a semiconductor structure, and an electronic circuit. Group III-nitride devices, such as, for example, high-electron-mobility transistors, may include a two-dimensional electron gas (2DEG) between two active layers. For example,...

High electron mobility transistor including plurality of gate electrodes
06/05/14 - 20140151747 - According to example embodiments, a high electron mobility transistor includes: a channel layer including a first semiconductor material; a channel supply layer on the channel layer and configured to generate a 2-dimensional electron gas (2DEG) in the channel layer, the channel supply layer including a second semiconductor material; source and...

Compound semiconductor device and manufacturing method of the same
06/05/14 - 20140151748 - The compound semiconductor device includes a first-compound-semiconductor-layer, a second-compound-semiconductor-layer formed on an upper side of the first-compound-semiconductor-layer and having a band gap larger than the band gap of the first-compound-semiconductor-layer, a p-type third-compound-semiconductor-layer formed on an upper side of the second-compound-semiconductor-layer, an electrode formed on an upper side of the...

High electron mobility transistor and method of manufacturing the same
06/05/14 - 20140151749 - According to example embodiments, a high electron mobility transistor (HEMT) includes a channel layer; a channel supply layer on the channel layer; a source electrode and a drain electrode spaced apart from each other on one of the channel layer and the channel supply layer; a gate electrode on a...

Group iii-nitride-based transistor with gate dielectric including a fluoride - or chloride- based compound
05/29/14 - 20140145243 - Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device may include a buffer layer disposed on a substrate, the buffer layer including gallium (Ga) and nitrogen (N) and a barrier layer disposed on the buffer layer, the barrier layer including...

Pseudomorphic high electron mobility transistor comprising doped low temperature buffer layer
05/22/14 - 20140138746 - A pseudomorphic high electron mobility transistor (PHEMT) comprises a substrate comprising a Group III-V semiconductor material, a buffer layer disposed over the substrate, wherein the buffer layer comprises microprecipitates of a Group V semiconductor element and is doped with an N-type dopant, and a channel layer disposed over the buffer...

Hetero junction field effect transistor and method for manufacturing the same
05/22/14 - 20140138747 - Hetero junction field effect transistors and methods of fabricating such transistors are disclosed wherein: a first compound semiconductor layer is provided on a substrate; a second compound semiconductor layer is provided on the first compound semiconductor layer; a gate insulating layer is provided on the second compound semiconductor layer; and...

Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof
05/15/14 - 20140131771 - A structure comprises a semiconductor substrate, a semiconductor-on-insulator region and a bulk region. The semiconductor-on-insulator region comprises a first semiconductor region, a dielectric layer provided between the semiconductor substrate and the first semiconductor region, and a first transistor comprising an active region provided in the first semiconductor region. The dielectric...

Power semiconductor device
05/08/14 - 20140124836 - A power semiconductor device is disclosed. The power semiconductor device includes a substrate, a first semiconductor layer disposed on the substrate, a second semiconductor layer disposed on the first semiconductor layer, a third semiconductor layer disposed on the second semiconductor layer and exposing a portion of the second semiconductor layer,...

Nitride semiconductor device and method for manufacturing same
05/08/14 - 20140124837 - A nitride semiconductor device includes an undoped GaN layer (1) and an undoped AlGaN layer (2) that are formed on an Si substrate (10), and ohmic electrodes (a source electrode (11) and a drain electrode (12)) that are formed on the undoped GaN layer (1) and the undoped AlGaN layer...

Semiconductor device
05/01/14 - 20140117410 - A semiconductor device includes: a first semiconductor layer formed on a substrate and formed of a nitride-based semiconductor; a second semiconductor layer formed on a surface of the first semiconductor layer and formed of a nitride-based semiconductor having a wider band-gap than the first semiconductor layer; first and second electrodes...