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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Heterojunction Device > Field Effect Transistor

Field Effect Transistor

Field Effect Transistor patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

07/31/14 - 20140209977 - Doped and strained flexible thin-film transistors
Semiconductor trilayer structures that are doped and strained are provided. Also provided are mechanically flexible transistors, including radiofrequency transistors, incorporating the trilayer structures and methods for fabricating the trilayer structures and transistors. The trilayer structures comprise a first layer of single-crystalline semiconductor material, a second layer of single-crystalline semiconductor material...

07/31/14 - 20140209978 - Devices with strained source/drain structures
A device includes a substrate, a gate structure over the substrate, and source/drain (S/D) features in the substrate and interposed by the gate structure. At least one of the S/D features includes a first semiconductor material, a second semiconductor material over the first semiconductor material, and a third semiconductor material...

07/24/14 - 20140203327 - Deep gate-all-around semiconductor device having germanium or group iii-v active layer
Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure...

07/24/14 - 20140203328 - Method and system for a gallium nitride vertical jfet with self-aligned gate metallization
A semiconductor device includes a III-nitride substrate and a first III-nitride epitaxial layer coupled to the III-nitride substrate and comprising a drift region, a channel region, and an extension region. The channel region is separated from the III-nitride substrate by the drift region. The channel region is characterized by a...

07/17/14 - 20140197455 - Semiconductor substructure having elevated strain material-sidewall interface and method of making the same
A semiconductor substructure with improved performance and a method of forming the same is described. In one embodiment, the semiconductor substructure includes a substrate, having an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed...

07/17/14 - 20140197456 - Semiconductor device and fabricating the same
The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a gate region, source and drain (S/D) regions separated by the gate region and a first fin structure in a gate region in the N-FET region. The first fin structure is formed by a first semiconductor...

07/17/14 - 20140197457 - Finfet device and method of fabricating same
The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having isolation regions, a gate region, source and drain regions separated by the gate region, a first fin structure in a gate region. The first fin structure includes a first semiconductor material layer as a lower portion...

07/17/14 - 20140197458 - Finfet device and method of fabricating same
An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin,...

07/03/14 - 20140183600 - Novel fin structure of finfet
A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa. The mesa has a first semiconductor material, and the channel...

06/26/14 - 20140175513 - Structure and method for integrated devices on different substartes with interfacial engineering
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first semiconductor material and a first reactivity; and a low reactivity capping layer of disposed on the semiconductor substrate, wherein the low reactivity capping layer includes a second semiconductor material and...

06/19/14 - 20140167110 - Partial poly amorphization for channeling prevention
Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate,...

06/12/14 - 20140159114 - Vertical nanowire based hetero-structure split gate memory
A memory cell is disclosed. The memory cell includes a vertical base disposed on a substrate. The vertical base includes first and second channels between top and bottom terminals. The memory cell also includes a first gate surrounding the first channel and a second gate surrounding the second channel. The...

06/05/14 - 20140151746 - Finfet device with isolated channel
Despite improvements in FinFETs and strained silicon devices, transistors continue to suffer performance degradation as device dimensions shrink. These include, in particular, leakage of charge between the semiconducting channel and the substrate. An isolated channel FinFET device prevents channel-to-substrate leakage by inserting an insulating layer between the channel (fin) and...

05/29/14 - 20140145242 - Fin-last finfet and methods of forming same
Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate...

05/22/14 - 20140138744 - Tunneling field effect transistors (tfets) for cmos architectures and approaches to fabricating n-type and p-type tfets
Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel...

05/22/14 - 20140138745 - Semiconductor devices including a stressor in a recess and methods of forming the same
Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in...

05/15/14 - 20140131770 - Co-integration of elemental semiconductor devices and compound semiconductor devices
First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one...

05/01/14 - 20140117409 - Method and structure for body contacted fet with reduced body resistance and source to drain contact leakage
A semiconductor device and method of making same. The device includes a substrate comprising a semiconductor layer on an insulating layer, the semiconductor layer including a semiconductor body having a body contact region and an abutting switching region; a bridged gate over the semiconductor body, the bridged gate having a...

04/24/14 - 20140110755 - Apparatus and method for forming semiconductor contacts
A method for forming semiconductor contacts comprises forming a germanium fin structure over a silicon substrate, depositing a doped amorphous silicon layer over the first drain/source region and the second drain/source region at a first temperature, wherein the first temperature is lower than a melting point of the germanium fin...

04/24/14 - 20140110756 - Semiconductor devices and methods for manufacturing the same
Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: sequentially forming a sacrificial layer and a semiconductor layer on a substrate; forming a first cover layer on the semiconductor layer; forming an opening extending into the substrate with the first cover layer as...

04/24/14 - 20140110757 - Fabricating method of semiconductor device and semiconductor device fabricated using the same method
A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality...

04/17/14 - 20140103395 - Semiconductor element
According to one embodiment, the semiconductor element includes a semi-insulating substrate which has a first first-conductivity-type layer. The semiconductor element includes a first semiconductor layer. The first semiconductor layer contains non-doped AlXGa1-XN (0≦X<1). The semiconductor element includes a second semiconductor layer. The second semiconductor layer contains non-doped or second-conductivity-type AlYGa1-YN...

04/17/14 - 20140103396 - Strain-inducing semiconductor regions
A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice...

04/17/14 - 20140103397 - Techniques for forming non-planar germanium quantum well devices
Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure...

04/10/14 - 20140097468 - Nitride semiconductor device and method for manufacturing same
A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer (1) located over the substrate; a second nitride semiconductor layer (2) located over the first nitride semiconductor layer (1), having a larger band gap than the first nitride semiconductor layer (1), and having a recess (11) penetrating into...

03/27/14 - 20140084342 - Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates
Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side...

03/27/14 - 20140084343 - Non-planar semiconductor device having group iii-v material active region with multi-dielectric gate stack
Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the...

03/20/14 - 20140077264 - Semiconductor device and manufacturing method thereof
A semiconductor device and method of fabricating the semiconductor device are disclosed. The method includes forming a plurality of gates on a surface of a substrate, forming sidewalls on side surfaces of the gates, forming a Sigma-shaped recess in the substrate between adjacent gates, forming a SiGe seed layer on...

03/20/14 - 20140077265 - Gateless switch with capacitively-coupled contacts
A switch includes an input contact and an output contact to a conducting channel. At least one of the input and output contacts is capacitively coupled to the conducting channel. A control contact is located outside of a region between the input and output contacts, and can be used to...

03/13/14 - 20140070276 - Source/drain re-growth for manufacturing iii-v based transistors
A method of forming an integrated circuit structure includes providing a substrate, and epitaxially growing a first semiconductor layer over the substrate. The first semiconductor layer includes a first III-V compound semiconductor material formed of group III and group V elements. The method further includes forming a gate structure on...

03/13/14 - 20140070277 - Epitaxial growth of smooth and highly strained germanium
A smooth germanium layer which can be grown directly on a silicon semiconductor substrate by exposing the substrate to germanium precursor in the presence of phosphine at temperature of about 350 C. The germanium layer formation can be achieved with or without a SiGe seed layer. The process to form...

03/06/14 - 20140061722 - Transistors, semiconductor devices, and methods of manufacture thereof
Transistors, semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a transistor over a workpiece. The transistor includes a sacrificial gate material comprising a group III-V material. The method includes combining a metal (Me) with the group III-V...

03/06/14 - 20140061723 - Mos transistor
A MOS transistor including a U-shaped channel-forming semiconductor region and source and drain regions having the same U shape located against the channel-forming region on either side thereof, the internal surface of the channel-forming semiconductor region being coated with a conductive gate, a gate insulator being interposed....

02/27/14 - 20140054648 - Needle-shaped profile finfet device
Structures and methods are presented relating to formation of finFET semiconducting devices. A finFET device is presented comprising fin(s) formed on a substrate, wherein the fin(s) has a needle-shaped profile. The needle-shaped profile, in conjunction with at least a buffer layer or a doped layer, epitaxially formed on the fin(s),...

02/27/14 - 20140054649 - Semiconductor devices and methods of forming the semiconductor devices including a retrograde well
Semiconductor devices and methods of forming semiconductor devices are provided herein. In an embodiment, a semiconductor device includes a semiconductor substrate. A source region and a drain region are disposed in the semiconductor substrate. A channel region is defined in the semiconductor substrate between the source region and the drain...

02/27/14 - 20140054650 - Method for increasing fin density
The present disclosure is directed to a method of manufacturing a FinFET structure in which at least one initial set of fin structures is formed by photolithographic processes, followed by forming an additional fin structure by epitaxial growth of a semiconductor material between the initial set of fin structures. The...

02/20/14 - 20140048849 - Package configurations for low emi circuits
An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural...

02/13/14 - 20140042494 - Metal nanoparticle monolayer
This disclosure generally relates to a device with a monolayer of metal nanoparticles and a method for making the same. The nanoparticles of the monolayer of metal nanoparticles are grouped in an ultrahigh density with an average distance between each neighboring metal nanoparticle less than or equal to about 3...

02/06/14 - 20140035000 - Source and drain doping profile control employing carbon-doped semiconductor material
Carbon-doped semiconductor material portions are formed on a subset of surfaces of underlying semiconductor surfaces contiguously connected to a channel of a field effect transistor. Carbon-doped semiconductor material portions can be formed by selective epitaxy of a carbon-containing semiconductor material layer or by shallow implantation of carbon atoms into surface...

02/06/14 - 20140035001 - Compound semiconductor structure
A semiconductor structure (1) comprises a dielectric layer (2) including a dielectric material having a dielectric constant higher than that of silicon oxide; a channel region (3) including a compound semiconductor material; a passivation layer (4) including a passivation material between the channel region (3) and the dielectric layer (2);...

02/06/14 - 20140035002 - High breakdown voltage semiconductor device
Semiconductor regions are alternately arranged in a parallel pn layer in which an n-type region and a p-type region are alternately arranged parallel to the main surface of a semiconductor substrate. Pitch between n drift region and p partition region of a second parallel pn layer in an edge termination...

01/30/14 - 20140027816 - High mobility strained channels for fin-based transistors
Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although...

01/30/14 - 20140027817 - Hybrid transistor
A hybrid transistor (58) has a substrate (42) with a first (e.g., P type) well region (46) and a second (e.g., N type) well region (44) with an NP or PN junction (43) therebetween. A MOS portion (70-3) of the hybrid transistor (58) has an (e.g., N type) source region...

01/30/14 - 20140027818 - Gate recessed fdsoi transistor with sandwich of active and etch control layers
The structure and the fabrication methods herein implement a fully depleted, recessed gate silicon-on-insulator (SOI) transistor with reduced access resistance, reduced on-current variability, and strain-increased performance. This transistor is based on an SOI substrate that has an epitaxially grown sandwich of SiGe and Si layers that are incorporated in the...

01/16/14 - 20140015009 - Tunnel transistor with high current by bipolar amplification
A tunnel-effect transistor the drain region of which includes a first zone doped with a doping of a first type, and a second zone doped with a doping of a second type forming a junction with the first zone....

01/16/14 - 20140015010 - Drain extended field effect transistors and methods of formation thereof
In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping...

01/09/14 - 20140008699 - Iii-v compound semiconductor device having metal contacts and method of making the same
semiconductor device comprises a semiconductor substrate; a channel layer of at least a first III-V semiconductor compound above the semiconductor substrate; a gate stack structure above a first portion of the channel layer; a source region and a drain region comprising at least a second III-V semiconductor compound above a...

01/09/14 - 20140008700 - Semiconductor device having germanium active layer with underlying diffusion barrier layer
Semiconductor devices having germanium active layers with underlying diffusion barrier layers are described. For example, a semiconductor device includes a gate electrode stack disposed above a substrate. A germanium active layer is disposed above the substrate, underneath the gate electrode stack. A diffusion barrier layer is disposed above the substrate,...

01/02/14 - 20140001515 - Static discharge system
A semiconductor circuit includes a three-terminal high voltage semiconductor device, a charge distribution structure and a static discharge system. The charge distribution structure has a plurality of conductors with a floating potential. The charge distribution structure is capacitively coupled to a first terminal of the semiconductor device. The static discharge...

12/26/13 - 20130341677 - Gan vertical superjunction device structures and fabrication methods
A semiconductor device includes a III-nitride substrate of a first conductivity type, a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate, and a first III-nitride epitaxial structure coupled to a first portion of a surface of the first III-nitride epitaxial layer. The first III-nitride...

12/26/13 - 20130341678 - Semiconductor device with selectively etched surface passivation
A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer...

12/26/13 - 20130341679 - Semiconductor device with selectively etched surface passivation
A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and...

12/26/13 - 20130341680 - Field effect transistor
A field effect transistor includes a stacked body, a source electrode, a drain electrode, a gate electrode, a dielectric layer and a silicon nitride layer. The stacked layer has a heterojunction made of a nitride semiconductor. The source and drain electrodes are provided on a surface of the stacked body....