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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Heterojunction Device > Field Effect Transistor

Field Effect Transistor

Field Effect Transistor patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

10/30/14 - 20140319581 - High performance strained source-drain structure and method of fabricating the same
A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch...

10/23/14 - 20140312387 - Semiconductor device and method for fabricating the same
A semiconductor device includes a base layer of a group III-V compound, a channel layer disposed on the base layer and including a group IV element, a nitride layer disposed on the channel layer, a gate insulation layer disposed on the nitride layer and a gate electrode disposed on the...

10/23/14 - 20140312388 - Apparatus and method for forming semiconductor contacts
A method for forming semiconductor contacts comprises forming a germanium fin structure over a silicon substrate, depositing a doped amorphous silicon layer over the first drain/source region and the second drain/source region at a first temperature, wherein the first temperature is lower than a melting point of the germanium fin...

10/23/14 - 20140312389 - Reacted conductive gate electrodes and methods of making the same
A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion...

10/16/14 - 20140306269 - Vertical pmos field effect transistor and manufacturing method thereof
A PMOS field effect transistor includes a substrate, a first nitride layer, a mesa structure, two gate oxide films, a gate stack layer and a second nitride layer. The substrate has a oxide layer and a first doping area. The first nitride layer is located on the oxide layer. The...

10/09/14 - 20140299918 - Semiconductor substrate and fabrication method thereof, and semiconductor apparatus using the same and fabrication method thereof
A semiconductor substrate and a fabrication method thereof, and a semiconductor apparatus using the same and a fabrication method thereof are provided. The semiconductor substrate includes a semiconductor wafer, a silicon germanium (SiGe)-based impurity doping region formed on the semiconductor wafer, and a protection layer formed on the SiGe-based impurity...

10/09/14 - 20140299919 - Semiconductor device and method for manufacturing the same
A semiconductor device and a method for manufacturing the same are provided. In one embodiment, the method comprises: growing a first epitaxial layer on a substrate; forming a sacrificial gate stack on the first epitaxial layer; selectively etching the first epitaxial layer; growing and in-situ doping a second epitaxial layer...

10/02/14 - 20140291727 - Method for forming semiconductor gate structure and semiconductor gate structure
A method for forming a semiconductor gate structure and a semiconductor gate structure are provided. The method includes: providing a substrate with a Ge layer as a surface thereof; forming a Sn layer on the Ge layer, in which an interface between the Ge layer and the Sn layer is...

09/25/14 - 20140284661 - Monolithic integrated circuit (mmic) structure and method for forming such structure
A method for forming a semiconductor structure having a transistor device with a control electrode for controlling a flow of carriers between a first electrode and a second electrode. A passivation layer is deposited over the first electrode, the second electrode and the control electrode. An etch stop layer is...

09/18/14 - 20140264443 - Sige surface passivation by germanium cap
The present disclosure relates to a transistor device having a germanium cap layer that is able to provide for a low interface trap density, while meeting effective oxide thickness scaling requirements, and a related method of fabrication. In some embodiments, the disclosed transistor device has a channel layer disposed within...

09/18/14 - 20140264444 - Stress-enhancing selective epitaxial deposition of embedded source and drain regions
Shallow trench isolation structures are formed within a semiconductor layer of a substrate to define an active area. The active area is recessed relative to a top surface of the shallow trench isolation structure. A shallow trench isolation (STI) spacer is formed on sidewalls of the shallow trench isolation structure...

09/18/14 - 20140264445 - Source/drain structure of semiconductor device
The disclosure relates to a semiconductor device. An exemplary structure for a field effect transistor comprises a substrate comprising a major surface and a cavity below the major surface; a gate stack on the major surface of the substrate; a spacer adjoining one side of the gate stack; a shallow...

09/18/14 - 20140264446 - Iii-v finfets on silicon substrate
A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon...

09/18/14 - 20140264447 - Apparatuses and methods comprising a channel region having different minority carrier lifetimes
Apparatuses, such as memory devices, memory cell strings, and electronic systems, and methods of forming such apparatuses are shown. One such apparatus includes a channel region that has a minority carrier lifetime that is lower at one or more end portions, than in a middle portion. Other apparatuses and methods...

09/11/14 - 20140252412 - Strained and uniform doping technique for finfets
The present disclosure relates to a device and method of forming enhanced channel carrier mobility within a transistor. Silicon carbon phosphorus (SiCP) source and drain regions are formed within the transistor with cyclic deposition etch (CDE) epitaxy, wherein both resistivity and strain are controlled by substitutional phosphorus. A carbon concentration...

09/11/14 - 20140252413 - Silicon-germanium fins and silicon fins on a bulk substrate
A first silicon-germanium alloy layer is formed on a semiconductor substrate including silicon. A stack of a first silicon layer and a second silicon-germanium alloy layer is formed over a first region of the first silicon-germanium alloy layer, and a second silicon layer thicker than the first silicon layer is...

09/11/14 - 20140252414 - Passivated iii-v or ge fin-shaped field effect transistor
A semiconductor device includes a semiconductor substrate having a top surface, and at least one coated fin protruding perpendicularly from the surface and having a height h and side walls. The at least one coated fin further includes a core of one or more layers selected from the group consisting...

09/04/14 - 20140246697 - Semiconductor device with charge compensation structure
A semiconductor device is provided. The semiconductor device includes a semiconductor body having a main surface. In a vertical cross-section which is substantially orthogonal to the main surface the semiconductor body includes a vertical trench, an n-type silicon semiconductor region, and two p-type silicon semiconductor regions each of which adjoins...

09/04/14 - 20140246698 - Channel sige removal from pfet source/drain region for improved silicide formation in hkmg technologies without embedded sige
When forming sophisticated P-channel transistors, a semiconductor alloy layer is formed on the surface of the semiconductor layer including the transistor active region. When a metal silicide layer is formed contiguous to this semiconductor alloy layer, an agglomeration of the metal silicide layer into isolated clusters is observed. In order...

08/28/14 - 20140239346 - Mishfet and schottky device integration
A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a...

08/28/14 - 20140239347 - Structure and method for defect passivation to reduce junction leakage for finfet device
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate of a first semiconductor material; shallow trench isolation (STI) features formed in the semiconductor substrate; and a fin-like active region of a second semiconductor material epitaxy grown on the semiconductor substrate. The first...

08/21/14 - 20140231872 - Method for inducing strain in finfet channels
FinFETs in which a swelled material within the fin, typically an oxide of the fin semiconductor, causes strain that significantly increases charge carrier mobility within the FinFET channel. The concept can be applied to either p-type or n-type FinFETs. For p-type FinFETs the swelled material is positioned underneath the source...

08/14/14 - 20140225161 - Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer above the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a p-type nitride semiconductor layer above the second nitride semiconductor layer; two third nitride semiconductor layers...

08/07/14 - 20140217468 - Planar semiconductor growth on iii-v material
A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would...

08/07/14 - 20140217469 - Ga2o3 semiconductor element
A Ga2O3 semiconductor element includes: an n-type β-Ga2O3 single crystal film, which is formed on a high-resistance β-Ga2O3 substrate directly or with other layer therebetween; a source electrode and a drain electrode, which are formed on the n-type β-Ga2O3 single crystal film; and a gate electrode, which is formed on...

08/07/14 - 20140217470 - Ga2o3 semiconductor element
Provided is a high-quality Ga2O3 semiconductor element. Provided is, as one embodiment of the present invention, a Ga2O3 MISFET (10), which includes: an n-type α-(AlxGa1-x)2O3 single crystal film (3), which is formed on an α-Al2O3 substrate (2) directly or with other layer therebetween, and is composed of an α-(AlxGa1-x)2O3 single...

08/07/14 - 20140217471 - Ga2o3 semiconductor element
Provided is a high-quality Ga2O3 semiconductor element. Provided is, as one embodiment of the present invention, a Ga2O3 MESFET (10), which includes: an n-type α-(AlxGa1-x)2O3 single crystal film (3), which is formed on an α-Al2O3 substrate (2) directly or with other layer therebetween, and is composed of an α-(AlxGa1-x)2O3 single...

07/31/14 - 20140209977 - Doped and strained flexible thin-film transistors
Semiconductor trilayer structures that are doped and strained are provided. Also provided are mechanically flexible transistors, including radiofrequency transistors, incorporating the trilayer structures and methods for fabricating the trilayer structures and transistors. The trilayer structures comprise a first layer of single-crystalline semiconductor material, a second layer of single-crystalline semiconductor material...

07/31/14 - 20140209978 - Devices with strained source/drain structures
A device includes a substrate, a gate structure over the substrate, and source/drain (S/D) features in the substrate and interposed by the gate structure. At least one of the S/D features includes a first semiconductor material, a second semiconductor material over the first semiconductor material, and a third semiconductor material...

07/24/14 - 20140203327 - Deep gate-all-around semiconductor device having germanium or group iii-v active layer
Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure...

07/24/14 - 20140203328 - Method and system for a gallium nitride vertical jfet with self-aligned gate metallization
A semiconductor device includes a III-nitride substrate and a first III-nitride epitaxial layer coupled to the III-nitride substrate and comprising a drift region, a channel region, and an extension region. The channel region is separated from the III-nitride substrate by the drift region. The channel region is characterized by a...

07/17/14 - 20140197455 - Semiconductor substructure having elevated strain material-sidewall interface and method of making the same
A semiconductor substructure with improved performance and a method of forming the same is described. In one embodiment, the semiconductor substructure includes a substrate, having an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed...

07/17/14 - 20140197456 - Semiconductor device and fabricating the same
The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a gate region, source and drain (S/D) regions separated by the gate region and a first fin structure in a gate region in the N-FET region. The first fin structure is formed by a first semiconductor...

07/17/14 - 20140197457 - Finfet device and method of fabricating same
The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having isolation regions, a gate region, source and drain regions separated by the gate region, a first fin structure in a gate region. The first fin structure includes a first semiconductor material layer as a lower portion...

07/17/14 - 20140197458 - Finfet device and method of fabricating same
An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin,...

07/03/14 - 20140183600 - Novel fin structure of finfet
A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa. The mesa has a first semiconductor material, and the channel...

06/26/14 - 20140175513 - Structure and method for integrated devices on different substartes with interfacial engineering
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first semiconductor material and a first reactivity; and a low reactivity capping layer of disposed on the semiconductor substrate, wherein the low reactivity capping layer includes a second semiconductor material and...

06/19/14 - 20140167110 - Partial poly amorphization for channeling prevention
Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate,...

06/12/14 - 20140159114 - Vertical nanowire based hetero-structure split gate memory
A memory cell is disclosed. The memory cell includes a vertical base disposed on a substrate. The vertical base includes first and second channels between top and bottom terminals. The memory cell also includes a first gate surrounding the first channel and a second gate surrounding the second channel. The...

06/05/14 - 20140151746 - Finfet device with isolated channel
Despite improvements in FinFETs and strained silicon devices, transistors continue to suffer performance degradation as device dimensions shrink. These include, in particular, leakage of charge between the semiconducting channel and the substrate. An isolated channel FinFET device prevents channel-to-substrate leakage by inserting an insulating layer between the channel (fin) and...

05/29/14 - 20140145242 - Fin-last finfet and methods of forming same
Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate...

05/22/14 - 20140138744 - Tunneling field effect transistors (tfets) for cmos architectures and approaches to fabricating n-type and p-type tfets
Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel...

05/22/14 - 20140138745 - Semiconductor devices including a stressor in a recess and methods of forming the same
Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in...

05/15/14 - 20140131770 - Co-integration of elemental semiconductor devices and compound semiconductor devices
First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one...

05/01/14 - 20140117409 - Method and structure for body contacted fet with reduced body resistance and source to drain contact leakage
A semiconductor device and method of making same. The device includes a substrate comprising a semiconductor layer on an insulating layer, the semiconductor layer including a semiconductor body having a body contact region and an abutting switching region; a bridged gate over the semiconductor body, the bridged gate having a...

04/24/14 - 20140110755 - Apparatus and method for forming semiconductor contacts
A method for forming semiconductor contacts comprises forming a germanium fin structure over a silicon substrate, depositing a doped amorphous silicon layer over the first drain/source region and the second drain/source region at a first temperature, wherein the first temperature is lower than a melting point of the germanium fin...

04/24/14 - 20140110756 - Semiconductor devices and methods for manufacturing the same
Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: sequentially forming a sacrificial layer and a semiconductor layer on a substrate; forming a first cover layer on the semiconductor layer; forming an opening extending into the substrate with the first cover layer as...

04/24/14 - 20140110757 - Fabricating method of semiconductor device and semiconductor device fabricated using the same method
A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality...

04/17/14 - 20140103395 - Semiconductor element
According to one embodiment, the semiconductor element includes a semi-insulating substrate which has a first first-conductivity-type layer. The semiconductor element includes a first semiconductor layer. The first semiconductor layer contains non-doped AlXGa1-XN (0≦X<1). The semiconductor element includes a second semiconductor layer. The second semiconductor layer contains non-doped or second-conductivity-type AlYGa1-YN...

04/17/14 - 20140103396 - Strain-inducing semiconductor regions
A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice...

04/17/14 - 20140103397 - Techniques for forming non-planar germanium quantum well devices
Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure...