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Field Effect Transistor

Field Effect Transistor patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

Related Categories:

Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)


Heterojunction Device > Field Effect Transistor



Cmos devices with reduced leakage and methods of forming the same
05/28/15 - 20150145002 - A device includes a first semiconductor layer, and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer and the second semiconductor layer comprise different materials. A semiconductor region is overlying and contacting the second semiconductor layer, wherein a bottom surface of the semiconductor region contacts a...

Finfet semiconductor devices including recessed source-drain regions on a bottom semiconductor layer and methods of fabricating the same
05/28/15 - 20150145003 - FinFET semiconductor devices and methods of forming the same are provided. The finFET semiconductor devices may include an insulator layer, a bottom semiconductor layer on the insulator layer, a channel fin on the bottom semiconductor layer, a source region on the bottom semiconductor layer and adjacent a first side of...

Semiconductor device and a method for manufacturing a semiconductor device
05/28/15 - 20150145004 - The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged...

Stress inducing contact metal in finfet cmos
05/21/15 - 20150137181 - A method of forming a semiconductor structure includes forming a first plurality of fins in a first region of a semiconductor substrate and a second plurality of fins in a second region of a semiconductor substrate. A gate structure is formed covering a first portion of the first and second...

Semiconductor device having v-shaped region
05/21/15 - 20150137182 - Among other things, a semiconductor device or transistor and a method for forming the semiconductor device are provided for herein. The semiconductor device comprises one or more v-shaped recesses in which stressed monocrystalline semiconductor material, such as silicon germanium, is grown, to form at least one of a source or...

Controlling the shape of source/drain regions in finfets
05/21/15 - 20150137183 - An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from...

Systems and methods for a semiconductor structure having multiple semiconductor-device layers
05/14/15 - 20150129932 - A method of fabricating a semiconductor structure having multiple semiconductor device layers is provided. The method comprises providing a bulk substrate and growing a first channel material on the bulk substrate wherein the lattice constant of the channel material is different from the lattice constant of the bulk substrate to...

Tuck strategy in transistor manufacturing flow
05/14/15 - 20150129933 - When forming field effect transistors with a semiconductor alloy layer, e.g., SiGe, embedded in the source/drain regions, a strategy called tucking has been developed in order to improve formation of the semiconductor alloy layer. An improved tucking strategy is hereby proposed, wherein the interface between the isolation region and the...

Methods of forming substantially self-aligned isolation regions on finfet semiconductor devices and the resulting devices
05/14/15 - 20150129934 - One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the...

Methods of forming finfet devices with alternative channel materials
05/07/15 - 20150123166 - are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods and devices disclosed herein involve forming a doped silicon substrate fin and thereafter forming a layer of silicon/germanium around the substrate fin. The methods and devices also...

Method and gate structure for threshold voltage modulation in transistors
05/07/15 - 20150123167 - A method of fabricating a semiconductor device. A substrate (PMOS/NMOS regions) is prepared. A high-k dielectric layer is formed over the substrate. A threshold voltage modulation layer is formed over the dielectric layer of the NMOS region. A first work function layer is formed over the threshold voltage modulation layer...

Mishfet and schottky device integration
05/07/15 - 20150123168 - A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a...

Dual epitaxial process for a finfet device
04/30/15 - 20150115322 - A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the...

Semiconductor device
04/30/15 - 20150115323 - A semiconductor device including a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a band gap wider than that of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer to reach...

Fin spacer protected source and drain regions in finfets
04/23/15 - 20150108544 - An integrated circuit device includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, and a semiconductor fin protruding above the insulation regions. The insulation regions include a first portion and a second portion, with the first portion and second portion on opposite sides of the semiconductor fin. The...

Fin field effect transistors including multiple lattice constants and methods of fabricating the same
04/23/15 - 20150108545 - A Field Effect Transistor (FET) structure may include a fin on a substrate having a first lattice constant and at least two different lattice constant layers on respective different axially oriented surfaces of the fin, wherein the at least two different lattice constant layers each comprise lattice constants that are...

Method for improving transistor performance through reducing the salicide interface resistance
04/23/15 - 20150108546 - An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon...

Passivated and faceted for fin field effect transistor
04/16/15 - 20150102386 - A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of...

Semiconductor device with relaxation reduction liner and associated methods
04/09/15 - 20150097212 - A method for forming a semiconductor device includes forming a mask layer on a stressed semiconductor layer of a stressed, semiconductor-on-insulator wafer. An isolation trench bounding the stressed semiconductor layer is formed. The isolation trench extends through the mask layer and into the SOI wafer past an oxide layer thereof....

Vertical transistor devices for embedded memory and logic technologies
04/02/15 - 20150091058 - Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region disposed on a substrate, an epitaxial channel semiconductor region disposed on the source semiconductor region, an epitaxial drain semiconductor region disposed on the channel semiconductor region, and a gate electrode...

Process for fabricating fin-type field effect transistor (finfet) structure and product thereof
04/02/15 - 20150091059 - A process for fabricating a fin-type field effect transistor (FinFET) structure is described. A semiconductor substrate is patterned to form a fin. A spacer is formed on the sidewall of the fin. A portion of the fin is removed, such that the spacer and the surface of the remaining fm...

Method for producing a transistor
03/26/15 - 20150084095 - The invention concerns a method for producing a transistor. The gate of the transistor is produced after having produced source and drain electrodes of the transistor. From a substrate having a stack of layers comprising at least two surface layers with a first layer of a first semiconductor material intended...

Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels
03/26/15 - 20150084096 - A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material...

Silicon-on-nothing finfets
03/19/15 - 20150076561 - A semiconductor device includes an insulator formed within a void to electrically isolate a fin from an underlying substrate. The void is created by removing a doped sacrificial layer formed between the substrate and a fin layer. The sacrificial layer is doped to allow for a thicker layer relative to...

Strained source and drain (ssd) structure and method for forming the same
03/12/15 - 20150069466 - Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stacks. The semiconductor device structure includes doped regions formed...

Delta doping layer in mosfet source/drain region
03/12/15 - 20150069467 - A transistor includes a gate terminal, a source terminal and a drain terminal. At least one of the source and drain terminals has a layered configuration that includes a terminal layer and an intervening layer. The terminal layer has a top surface and a bottom surface. The intervening layer is...

Nitride-based transistors and methods of fabricating the same
03/05/15 - 20150060943 - A method of fabricating a nitride-based transistor includes sequentially forming a first nitride-based semiconductor layer doped with first type dopant, a second nitride-based semiconductor layer doped with at least one of a second type dopant, and a third nitride-based semiconductor layer doped with at least one of the first type...

Device structure with increased contact area and reduced gate capacitance
03/05/15 - 20150060944 - A FET structure including epitaxial source and drain regions includes large contact areas and exhibits both low resistivity and low parasitic gate to source/drain capacitance. The source and drain regions are laterally etched to provide recesses for accommodating low-k dielectric material without compromising the contact area between the source/drain regions...

Transistors with high concentration of boron doped germanium
03/05/15 - 20150060945 - Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the...

Tin doped iii-v material contacts
02/26/15 - 20150054031 - Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a metal contact such as one or more metals/alloys on silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example embodiment, an intermediate tin...

Methods for making a semiconductor device with shaped source and drain recesses and related devices
02/26/15 - 20150054032 - A method for making a semiconductor device includes forming at least one gate stack on a layer comprising a first semiconductor material and etching source and drain recesses adjacent the at least one gate stack. The method further includes shaping the source and drain recesses to have a vertical side...

Finfet with self-aligned punchthrough stopper
02/26/15 - 20150054033 - A finFET with self-aligned punchthrough stopper and methods of manufacture are disclosed. The method includes forming spacers on sidewalls of a gate structure and fin structures of a finFET device. The method further includes forming a punchthrough stopper on exposed sidewalls of the fin structures, below the spacers. The method...

Semiconductor device and method of manufacturing the same
02/19/15 - 20150048419 - A semiconductor device has a channel layer formed above a substrate, a barrier layer formed over the channel layer and having a band gap larger than that of the channel layer, a trench passing through the barrier layer as far as a midway of the channel layer, and a gate...

Semiconductor device
02/12/15 - 20150041855 - A semiconductor device includes at least two fin-shaped structures, a gate structure, at least two epitaxial structures and a silicon cap. The fin-shaped structures are disposed on a substrate and are covered by the gate structure. The epitaxial structures are disposed at one side of the gate structure and respectively...

Compound semiconductor integrated circuit and method to fabricate same
02/12/15 - 20150041856 - A structure includes a substrate having a surface and a first transistor disposed in a first region supported by the surface of the substrate. The first transistor has a channel formed in a first compound (Group III-V) semiconductor having a first energy bandgap. The structure further includes a second transistor...

Semiconductor structure having stressor
02/12/15 - 20150041857 - A semiconductor structure includes a substrate, a shallow trench isolation (STI) structure embedded in the substrate, a stressor embedded in the substrate, and a conductive plug over and electrically coupled with the stressor. A same-material region is sandwiched by the STI structure and an entire sidewall of the stressor, and...

3d transistor channel mobility enhancement
02/12/15 - 20150041858 - A method of forming a semiconductor structure includes growing an epitaxial doped layer over an exposed portion of a plurality of fins. The epitaxial doped layer combines the exposed portion of the fins to form a merged source and drain region. An implantation process occurs in the fins through the...

Iii-v fet device with overlapped extension regions using gate last
01/29/15 - 20150028387 - A structure and method for fabricating a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) with self-aligned and overlapped extensions using a gate last process is disclosed. The a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) structure may be formed by forming a III-V compound semiconductor-containing heterostructure having at least one...

Iii-v device with overlapped extension regions using replacement gate
01/29/15 - 20150028388 - A structure and method for fabricating a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) with self-aligned and overlapped extensions using a replacement gate process is disclosed. The a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) structure may be formed by forming a III-V compound semiconductor-containing heterostructure having multiple layers and...

Semiconductor devices comprising a fin
01/29/15 - 20150028389 - A semiconductor device may include a fin disposed over a workpiece. The fin may include: a first semiconductive material disposed over the workpiece; an oxide of the first semiconductive material disposed over the first semiconductive material; a second conductive material disposed over and spaced apart from the oxide of the...

Iii-v semiconductor device having self-aligned contacts
01/22/15 - 20150021662 - A method including forming a III-V compound semiconductor-containing heterostructure, forming a gate dielectric having a dielectric constant greater than 4.0 positioned within a gate trench, the gate trench formed within the III-V compound semiconductor-containing heterostructure, and forming a gate conductor within the gate trench on top of the gate dielectric,...

Finfet with insulator under channel
01/22/15 - 20150021663 - A FinFET has a structure including a semiconductor substrate, semiconductor fins and a gate spanning the fins. The fins each have a bottom region coupled to the substrate and a top active region. Between the bottom and top fin regions is a middle stack situated between a vertically elongated source...

Lateral/vertical semiconductor device with embedded isolator
01/22/15 - 20150021664 - A lateral/vertical device is provided. The device includes a device structure including a device channel having a lateral portion and a vertical portion. The lateral portion of the device channel can be located adjacent to a first surface of the device structure, and one or more contacts and/or a gate...

Semiconductor device and power conversion device
01/15/15 - 20150014746 - A switching device includes a power semiconductor chip, and a drive circuit which drives the power semiconductor chip. In the power semiconductor chip, a path through which a main current flows is connected to a first source terminal, and a ground terminal of the drive circuit is connected to a...

High mobility strained channels for fin-based transistors
01/08/15 - 20150008484 - Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although...

Novel embedded shape sige for nfet channel strain
01/01/15 - 20150001583 - An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress to the channel region of the NMOS transistors and compressive stress to the channel regions of the...

Replacement channel
01/01/15 - 20150001584 - The present disclosure relates to a device and method for strain inducing or high mobility channel replacement in a semiconductor device. The semiconductor device is configured to control current from a source to a drain through a channel region by use of a gate. A strain inducing or high mobility...

Tucked active region without dummy poly for performance boost and variation reduction
01/01/15 - 20150001585 - In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor...

Fin tunnel field effect transistor (fet)
12/25/14 - 20140374799 - A fin tunnel field effect transistor includes a seed region and a first type region disposed above the seed region. The first type region includes a first doping. The fin tunnel field effect transistor includes a second type region disposed above the first type region. The second type region includes...

Overlapped iii-v finfet with doped semiconductor extensions
12/25/14 - 20140374800 - A semiconductor structure that includes a semiconductor fin comprising an III-V compound semiconductor material. A functional gate structure straddles a portion of the semiconductor fin. A semiconductor channel material having an electron mobility greater than silicon and comprising a different semiconductor material than the semiconductor fin and is located beneath...

Reduced resistance sige finfet devices and method of forming same
12/11/14 - 20140361338 - A method for forming a fin field-effect transistor (FinFET) device, comprises forming a plurality of silicon fins on a substrate, depositing silicon germanium (SiGe) on the plurality of fins, forming a gate region by forming a dummy gate stack on a predetermined area of the fins including the SiGe, removing...

Pmos transistors and fabrication methods thereof
12/11/14 - 20140361339 - A method is provided for fabricating a PMOS transistor. The method includes providing a semiconductor substrate; and forming gate structures on a surface of the semiconductor substrate. The method also includes forming sidewall spacers around the gate structures; and forming a protection layer on the sidewall spacers. Further, the method...

Semiconductor device and fabrication method thereof
12/11/14 - 20140361340 - A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and...

Method of making a semiconductor device using a dummy gate
12/04/14 - 20140353716 - A method of making a semiconductor device includes forming a fin mask layer on a semiconductor layer, forming a dummy gate over the fin mask layer, and forming source and drain regions on opposite sides of the dummy gate. The dummy gate is removed and the underlying fin mask layer...

Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region
12/04/14 - 20140353717 - An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised...

Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region
12/04/14 - 20140353718 - An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating...

Semiconductor devices and fabricating methods thereof
12/04/14 - 20140353719 - Provided are semiconductor devices and fabricating methods thereof. The semiconductor device includes a field insulating layer formed in a substrate, an interlayer dielectric layer formed on the field insulating layer and including a trench exposing at least a portion of the field insulating layer, a deposition insulating layer formed in...

Semiconductor device and method of manufacturing semiconductor device
12/04/14 - 20140353720 - To provide a semiconductor device having improved characteristics. The semiconductor device has a substrate and thereon a buffer layer, a channel layer, a barrier layer, a trench penetrating therethrough and reaching the inside of the channel layer, a gate electrode placed in the trench via a gate insulating film, and...

Bulk finfet with controlled fin height and high-k liner
12/04/14 - 20140353721 - A method of forming a semiconductor device that includes forming a material stack on a semiconductor substrate, the material stack including a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, wherein the second...

Reduced short channel effect of iii-v field effect transistor via oxidizing aluminum-rich underlayer
11/13/14 - 20140332851 - In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present...

Non-planar semiconductor device having group iii-v material active region with multi-dielectric gate stack
11/13/14 - 20140332852 - Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the...

Method to make dual material finfet on same substrate
11/06/14 - 20140327044 - A method of fabricating a semiconductor device including proving a substrate having a germanium containing layer that is present on a dielectric layer, and etching the germanium containing layer of the substrate to provide a first region including a germanium containing fin structure and a second region including a mandrel...

Method to make dual material finfet on same substrate
11/06/14 - 20140327045 - A method of fabricating a semiconductor device including proving a substrate having a germanium containing layer that is present on a dielectric layer, and etching the germanium containing layer of the substrate to provide a first region including a germanium containing fin structure and a second region including a mandrel...

Fin-last finfet and methods of forming same
11/06/14 - 20140327046 - Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate...

High performance strained source-drain structure and method of fabricating the same
10/30/14 - 20140319581 - A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch...

Semiconductor device and method for fabricating the same
10/23/14 - 20140312387 - A semiconductor device includes a base layer of a group III-V compound, a channel layer disposed on the base layer and including a group IV element, a nitride layer disposed on the channel layer, a gate insulation layer disposed on the nitride layer and a gate electrode disposed on the...

Apparatus and method for forming semiconductor contacts
10/23/14 - 20140312388 - A method for forming semiconductor contacts comprises forming a germanium fin structure over a silicon substrate, depositing a doped amorphous silicon layer over the first drain/source region and the second drain/source region at a first temperature, wherein the first temperature is lower than a melting point of the germanium fin...

Reacted conductive gate electrodes and methods of making the same
10/23/14 - 20140312389 - A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion...

Vertical pmos field effect transistor and manufacturing method thereof
10/16/14 - 20140306269 - A PMOS field effect transistor includes a substrate, a first nitride layer, a mesa structure, two gate oxide films, a gate stack layer and a second nitride layer. The substrate has a oxide layer and a first doping area. The first nitride layer is located on the oxide layer. The...

Semiconductor substrate and fabrication method thereof, and semiconductor apparatus using the same and fabrication method thereof
10/09/14 - 20140299918 - A semiconductor substrate and a fabrication method thereof, and a semiconductor apparatus using the same and a fabrication method thereof are provided. The semiconductor substrate includes a semiconductor wafer, a silicon germanium (SiGe)-based impurity doping region formed on the semiconductor wafer, and a protection layer formed on the SiGe-based impurity...

Semiconductor device and method for manufacturing the same
10/09/14 - 20140299919 - A semiconductor device and a method for manufacturing the same are provided. In one embodiment, the method comprises: growing a first epitaxial layer on a substrate; forming a sacrificial gate stack on the first epitaxial layer; selectively etching the first epitaxial layer; growing and in-situ doping a second epitaxial layer...

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