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Field Effect Transistor

Field Effect Transistor patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

Related Categories:

Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)


Heterojunction Device > Field Effect Transistor



Iii-v fet device with overlapped extension regions using gate last
01/29/15 - 20150028387 - A structure and method for fabricating a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) with self-aligned and overlapped extensions using a gate last process is disclosed. The a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) structure may be formed by forming a III-V compound semiconductor-containing heterostructure having at least one...

Iii-v device with overlapped extension regions using replacement gate
01/29/15 - 20150028388 - A structure and method for fabricating a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) with self-aligned and overlapped extensions using a replacement gate process is disclosed. The a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) structure may be formed by forming a III-V compound semiconductor-containing heterostructure having multiple layers and...

Semiconductor devices comprising a fin
01/29/15 - 20150028389 - A semiconductor device may include a fin disposed over a workpiece. The fin may include: a first semiconductive material disposed over the workpiece; an oxide of the first semiconductive material disposed over the first semiconductive material; a second conductive material disposed over and spaced apart from the oxide of the...

Iii-v semiconductor device having self-aligned contacts
01/22/15 - 20150021662 - A method including forming a III-V compound semiconductor-containing heterostructure, forming a gate dielectric having a dielectric constant greater than 4.0 positioned within a gate trench, the gate trench formed within the III-V compound semiconductor-containing heterostructure, and forming a gate conductor within the gate trench on top of the gate dielectric,...

Finfet with insulator under channel
01/22/15 - 20150021663 - A FinFET has a structure including a semiconductor substrate, semiconductor fins and a gate spanning the fins. The fins each have a bottom region coupled to the substrate and a top active region. Between the bottom and top fin regions is a middle stack situated between a vertically elongated source...

Lateral/vertical semiconductor device with embedded isolator
01/22/15 - 20150021664 - A lateral/vertical device is provided. The device includes a device structure including a device channel having a lateral portion and a vertical portion. The lateral portion of the device channel can be located adjacent to a first surface of the device structure, and one or more contacts and/or a gate...

Semiconductor device and power conversion device
01/15/15 - 20150014746 - A switching device includes a power semiconductor chip, and a drive circuit which drives the power semiconductor chip. In the power semiconductor chip, a path through which a main current flows is connected to a first source terminal, and a ground terminal of the drive circuit is connected to a...

High mobility strained channels for fin-based transistors
01/08/15 - 20150008484 - Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although...

Novel embedded shape sige for nfet channel strain
01/01/15 - 20150001583 - An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress to the channel region of the NMOS transistors and compressive stress to the channel regions of the...

Replacement channel
01/01/15 - 20150001584 - The present disclosure relates to a device and method for strain inducing or high mobility channel replacement in a semiconductor device. The semiconductor device is configured to control current from a source to a drain through a channel region by use of a gate. A strain inducing or high mobility...

Tucked active region without dummy poly for performance boost and variation reduction
01/01/15 - 20150001585 - In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor...

Fin tunnel field effect transistor (fet)
12/25/14 - 20140374799 - A fin tunnel field effect transistor includes a seed region and a first type region disposed above the seed region. The first type region includes a first doping. The fin tunnel field effect transistor includes a second type region disposed above the first type region. The second type region includes...

Overlapped iii-v finfet with doped semiconductor extensions
12/25/14 - 20140374800 - A semiconductor structure that includes a semiconductor fin comprising an III-V compound semiconductor material. A functional gate structure straddles a portion of the semiconductor fin. A semiconductor channel material having an electron mobility greater than silicon and comprising a different semiconductor material than the semiconductor fin and is located beneath...

Reduced resistance sige finfet devices and method of forming same
12/11/14 - 20140361338 - A method for forming a fin field-effect transistor (FinFET) device, comprises forming a plurality of silicon fins on a substrate, depositing silicon germanium (SiGe) on the plurality of fins, forming a gate region by forming a dummy gate stack on a predetermined area of the fins including the SiGe, removing...

Pmos transistors and fabrication methods thereof
12/11/14 - 20140361339 - A method is provided for fabricating a PMOS transistor. The method includes providing a semiconductor substrate; and forming gate structures on a surface of the semiconductor substrate. The method also includes forming sidewall spacers around the gate structures; and forming a protection layer on the sidewall spacers. Further, the method...

Semiconductor device and fabrication method thereof
12/11/14 - 20140361340 - A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and...

Method of making a semiconductor device using a dummy gate
12/04/14 - 20140353716 - A method of making a semiconductor device includes forming a fin mask layer on a semiconductor layer, forming a dummy gate over the fin mask layer, and forming source and drain regions on opposite sides of the dummy gate. The dummy gate is removed and the underlying fin mask layer...

Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region
12/04/14 - 20140353717 - An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised...

Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region
12/04/14 - 20140353718 - An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating...

Semiconductor devices and fabricating methods thereof
12/04/14 - 20140353719 - Provided are semiconductor devices and fabricating methods thereof. The semiconductor device includes a field insulating layer formed in a substrate, an interlayer dielectric layer formed on the field insulating layer and including a trench exposing at least a portion of the field insulating layer, a deposition insulating layer formed in...

Semiconductor device and method of manufacturing semiconductor device
12/04/14 - 20140353720 - To provide a semiconductor device having improved characteristics. The semiconductor device has a substrate and thereon a buffer layer, a channel layer, a barrier layer, a trench penetrating therethrough and reaching the inside of the channel layer, a gate electrode placed in the trench via a gate insulating film, and...

Bulk finfet with controlled fin height and high-k liner
12/04/14 - 20140353721 - A method of forming a semiconductor device that includes forming a material stack on a semiconductor substrate, the material stack including a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, wherein the second...

Reduced short channel effect of iii-v field effect transistor via oxidizing aluminum-rich underlayer
11/13/14 - 20140332851 - In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present...

Non-planar semiconductor device having group iii-v material active region with multi-dielectric gate stack
11/13/14 - 20140332852 - Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the...

Method to make dual material finfet on same substrate
11/06/14 - 20140327044 - A method of fabricating a semiconductor device including proving a substrate having a germanium containing layer that is present on a dielectric layer, and etching the germanium containing layer of the substrate to provide a first region including a germanium containing fin structure and a second region including a mandrel...

Method to make dual material finfet on same substrate
11/06/14 - 20140327045 - A method of fabricating a semiconductor device including proving a substrate having a germanium containing layer that is present on a dielectric layer, and etching the germanium containing layer of the substrate to provide a first region including a germanium containing fin structure and a second region including a mandrel...

Fin-last finfet and methods of forming same
11/06/14 - 20140327046 - Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate...

High performance strained source-drain structure and method of fabricating the same
10/30/14 - 20140319581 - A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch...

Semiconductor device and method for fabricating the same
10/23/14 - 20140312387 - A semiconductor device includes a base layer of a group III-V compound, a channel layer disposed on the base layer and including a group IV element, a nitride layer disposed on the channel layer, a gate insulation layer disposed on the nitride layer and a gate electrode disposed on the...

Apparatus and method for forming semiconductor contacts
10/23/14 - 20140312388 - A method for forming semiconductor contacts comprises forming a germanium fin structure over a silicon substrate, depositing a doped amorphous silicon layer over the first drain/source region and the second drain/source region at a first temperature, wherein the first temperature is lower than a melting point of the germanium fin...

Reacted conductive gate electrodes and methods of making the same
10/23/14 - 20140312389 - A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion...

Vertical pmos field effect transistor and manufacturing method thereof
10/16/14 - 20140306269 - A PMOS field effect transistor includes a substrate, a first nitride layer, a mesa structure, two gate oxide films, a gate stack layer and a second nitride layer. The substrate has a oxide layer and a first doping area. The first nitride layer is located on the oxide layer. The...

Semiconductor substrate and fabrication method thereof, and semiconductor apparatus using the same and fabrication method thereof
10/09/14 - 20140299918 - A semiconductor substrate and a fabrication method thereof, and a semiconductor apparatus using the same and a fabrication method thereof are provided. The semiconductor substrate includes a semiconductor wafer, a silicon germanium (SiGe)-based impurity doping region formed on the semiconductor wafer, and a protection layer formed on the SiGe-based impurity...

Semiconductor device and method for manufacturing the same
10/09/14 - 20140299919 - A semiconductor device and a method for manufacturing the same are provided. In one embodiment, the method comprises: growing a first epitaxial layer on a substrate; forming a sacrificial gate stack on the first epitaxial layer; selectively etching the first epitaxial layer; growing and in-situ doping a second epitaxial layer...

Method for forming semiconductor gate structure and semiconductor gate structure
10/02/14 - 20140291727 - A method for forming a semiconductor gate structure and a semiconductor gate structure are provided. The method includes: providing a substrate with a Ge layer as a surface thereof; forming a Sn layer on the Ge layer, in which an interface between the Ge layer and the Sn layer is...

Monolithic integrated circuit (mmic) structure and method for forming such structure
09/25/14 - 20140284661 - A method for forming a semiconductor structure having a transistor device with a control electrode for controlling a flow of carriers between a first electrode and a second electrode. A passivation layer is deposited over the first electrode, the second electrode and the control electrode. An etch stop layer is...

Sige surface passivation by germanium cap
09/18/14 - 20140264443 - The present disclosure relates to a transistor device having a germanium cap layer that is able to provide for a low interface trap density, while meeting effective oxide thickness scaling requirements, and a related method of fabrication. In some embodiments, the disclosed transistor device has a channel layer disposed within...

Stress-enhancing selective epitaxial deposition of embedded source and drain regions
09/18/14 - 20140264444 - Shallow trench isolation structures are formed within a semiconductor layer of a substrate to define an active area. The active area is recessed relative to a top surface of the shallow trench isolation structure. A shallow trench isolation (STI) spacer is formed on sidewalls of the shallow trench isolation structure...

Source/drain structure of semiconductor device
09/18/14 - 20140264445 - The disclosure relates to a semiconductor device. An exemplary structure for a field effect transistor comprises a substrate comprising a major surface and a cavity below the major surface; a gate stack on the major surface of the substrate; a spacer adjoining one side of the gate stack; a shallow...

Iii-v finfets on silicon substrate
09/18/14 - 20140264446 - A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon...

Apparatuses and methods comprising a channel region having different minority carrier lifetimes
09/18/14 - 20140264447 - Apparatuses, such as memory devices, memory cell strings, and electronic systems, and methods of forming such apparatuses are shown. One such apparatus includes a channel region that has a minority carrier lifetime that is lower at one or more end portions, than in a middle portion. Other apparatuses and methods...

Strained and uniform doping technique for finfets
09/11/14 - 20140252412 - The present disclosure relates to a device and method of forming enhanced channel carrier mobility within a transistor. Silicon carbon phosphorus (SiCP) source and drain regions are formed within the transistor with cyclic deposition etch (CDE) epitaxy, wherein both resistivity and strain are controlled by substitutional phosphorus. A carbon concentration...

Silicon-germanium fins and silicon fins on a bulk substrate
09/11/14 - 20140252413 - A first silicon-germanium alloy layer is formed on a semiconductor substrate including silicon. A stack of a first silicon layer and a second silicon-germanium alloy layer is formed over a first region of the first silicon-germanium alloy layer, and a second silicon layer thicker than the first silicon layer is...

Passivated iii-v or ge fin-shaped field effect transistor
09/11/14 - 20140252414 - A semiconductor device includes a semiconductor substrate having a top surface, and at least one coated fin protruding perpendicularly from the surface and having a height h and side walls. The at least one coated fin further includes a core of one or more layers selected from the group consisting...

Semiconductor device with charge compensation structure
09/04/14 - 20140246697 - A semiconductor device is provided. The semiconductor device includes a semiconductor body having a main surface. In a vertical cross-section which is substantially orthogonal to the main surface the semiconductor body includes a vertical trench, an n-type silicon semiconductor region, and two p-type silicon semiconductor regions each of which adjoins...

Channel sige removal from pfet source/drain region for improved silicide formation in hkmg technologies without embedded sige
09/04/14 - 20140246698 - When forming sophisticated P-channel transistors, a semiconductor alloy layer is formed on the surface of the semiconductor layer including the transistor active region. When a metal silicide layer is formed contiguous to this semiconductor alloy layer, an agglomeration of the metal silicide layer into isolated clusters is observed. In order...

Mishfet and schottky device integration
08/28/14 - 20140239346 - A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a...

Structure and method for defect passivation to reduce junction leakage for finfet device
08/28/14 - 20140239347 - The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate of a first semiconductor material; shallow trench isolation (STI) features formed in the semiconductor substrate; and a fin-like active region of a second semiconductor material epitaxy grown on the semiconductor substrate. The first...

Method for inducing strain in finfet channels
08/21/14 - 20140231872 - FinFETs in which a swelled material within the fin, typically an oxide of the fin semiconductor, causes strain that significantly increases charge carrier mobility within the FinFET channel. The concept can be applied to either p-type or n-type FinFETs. For p-type FinFETs the swelled material is positioned underneath the source...

Semiconductor device and method of manufacturing semiconductor device
08/14/14 - 20140225161 - A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer above the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a p-type nitride semiconductor layer above the second nitride semiconductor layer; two third nitride semiconductor layers...

Planar semiconductor growth on iii-v material
08/07/14 - 20140217468 - A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would...

Ga2o3 semiconductor element
08/07/14 - 20140217469 - A Ga2O3 semiconductor element includes: an n-type β-Ga2O3 single crystal film, which is formed on a high-resistance β-Ga2O3 substrate directly or with other layer therebetween; a source electrode and a drain electrode, which are formed on the n-type β-Ga2O3 single crystal film; and a gate electrode, which is formed on...

Ga2o3 semiconductor element
08/07/14 - 20140217470 - Provided is a high-quality Ga2O3 semiconductor element. Provided is, as one embodiment of the present invention, a Ga2O3 MISFET (10), which includes: an n-type α-(AlxGa1-x)2O3 single crystal film (3), which is formed on an α-Al2O3 substrate (2) directly or with other layer therebetween, and is composed of an α-(AlxGa1-x)2O3 single...

Ga2o3 semiconductor element
08/07/14 - 20140217471 - Provided is a high-quality Ga2O3 semiconductor element. Provided is, as one embodiment of the present invention, a Ga2O3 MESFET (10), which includes: an n-type α-(AlxGa1-x)2O3 single crystal film (3), which is formed on an α-Al2O3 substrate (2) directly or with other layer therebetween, and is composed of an α-(AlxGa1-x)2O3 single...

Doped and strained flexible thin-film transistors
07/31/14 - 20140209977 - Semiconductor trilayer structures that are doped and strained are provided. Also provided are mechanically flexible transistors, including radiofrequency transistors, incorporating the trilayer structures and methods for fabricating the trilayer structures and transistors. The trilayer structures comprise a first layer of single-crystalline semiconductor material, a second layer of single-crystalline semiconductor material...

Devices with strained source/drain structures
07/31/14 - 20140209978 - A device includes a substrate, a gate structure over the substrate, and source/drain (S/D) features in the substrate and interposed by the gate structure. At least one of the S/D features includes a first semiconductor material, a second semiconductor material over the first semiconductor material, and a third semiconductor material...

Deep gate-all-around semiconductor device having germanium or group iii-v active layer
07/24/14 - 20140203327 - Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure...

Method and system for a gallium nitride vertical jfet with self-aligned gate metallization
07/24/14 - 20140203328 - A semiconductor device includes a III-nitride substrate and a first III-nitride epitaxial layer coupled to the III-nitride substrate and comprising a drift region, a channel region, and an extension region. The channel region is separated from the III-nitride substrate by the drift region. The channel region is characterized by a...

Semiconductor substructure having elevated strain material-sidewall interface and method of making the same
07/17/14 - 20140197455 - A semiconductor substructure with improved performance and a method of forming the same is described. In one embodiment, the semiconductor substructure includes a substrate, having an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed...

Semiconductor device and fabricating the same
07/17/14 - 20140197456 - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a gate region, source and drain (S/D) regions separated by the gate region and a first fin structure in a gate region in the N-FET region. The first fin structure is formed by a first semiconductor...

Finfet device and method of fabricating same
07/17/14 - 20140197457 - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having isolation regions, a gate region, source and drain regions separated by the gate region, a first fin structure in a gate region. The first fin structure includes a first semiconductor material layer as a lower portion...

Finfet device and method of fabricating same
07/17/14 - 20140197458 - An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin,...

Novel fin structure of finfet
07/03/14 - 20140183600 - A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa. The mesa has a first semiconductor material, and the channel...

Structure and method for integrated devices on different substartes with interfacial engineering
06/26/14 - 20140175513 - The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first semiconductor material and a first reactivity; and a low reactivity capping layer of disposed on the semiconductor substrate, wherein the low reactivity capping layer includes a second semiconductor material and...

Partial poly amorphization for channeling prevention
06/19/14 - 20140167110 - Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate,...

Vertical nanowire based hetero-structure split gate memory
06/12/14 - 20140159114 - A memory cell is disclosed. The memory cell includes a vertical base disposed on a substrate. The vertical base includes first and second channels between top and bottom terminals. The memory cell also includes a first gate surrounding the first channel and a second gate surrounding the second channel. The...

Finfet device with isolated channel
06/05/14 - 20140151746 - Despite improvements in FinFETs and strained silicon devices, transistors continue to suffer performance degradation as device dimensions shrink. These include, in particular, leakage of charge between the semiconducting channel and the substrate. An isolated channel FinFET device prevents channel-to-substrate leakage by inserting an insulating layer between the channel (fin) and...

Fin-last finfet and methods of forming same
05/29/14 - 20140145242 - Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate...

Tunneling field effect transistors (tfets) for cmos architectures and approaches to fabricating n-type and p-type tfets
05/22/14 - 20140138744 - Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel...

Semiconductor devices including a stressor in a recess and methods of forming the same
05/22/14 - 20140138745 - Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in...

Co-integration of elemental semiconductor devices and compound semiconductor devices
05/15/14 - 20140131770 - First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one...