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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Heterojunction Device > With Lattice Constant Mismatch (e.g., With Buffer Layer To Accommodate Mismatch) With Lattice Constant Mismatch (e.g., With Buffer Layer To Accommodate Mismatch)With Lattice Constant Mismatch (e.g., With Buffer Layer To Accommodate Mismatch) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/03/08 - 20080001170 - Plasma implantated impurities in junction region recesses A transistor device having a conformal depth of impurities implanted by isotropic ion implantation into etched junction recesses. For example, a conformal depth of arsenic impurities and/or carbon impurities may be implanted by plasma immersion ion implantation in junction recesses to reduce boron diffusion and current leakage from boron doped ... 01/03/08 - 20080001169 - Lattice-mismatched semiconductor structures and related methods for device fabrication Lattice-mismatched materials having configurations that trap defects within sidewall-containing structures. ... 11/29/07 - 20070272944 - Semiconductor member, manufacturing method thereof, and semiconductor device An SiGe layer is grown on a silicon substrate. The SiGe layer or the silicon substrate and SiGe layer are porosified by anodizing the SiGe layer to form a strain inducing porous layer or a porous silicon layer and strain inducing porous layer. An SiGe layer and strained silicon layer ... 11/29/07 - 20070272943 - Structure and manufacturing method for epitaxial layers of gallium nitride-based compound semiconductors The present invention relates to a structure and a manufacturing method of epitaxial layers of gallium nitride-based compound semiconductors with less dislocation densities. Surface treatment is carried out first on the surface of a substrate using reaction precursors Cp2Mg and NH3. Then a gallium nitride-based buffer layer is formed on ... 10/25/07 - 20070246742 - Method of manufacturing a strained semiconductor layer, method of manufacturing a semiconductor device and semiconductor substrate suitable for use in such a method The invention relates to a method of manufacturing a semiconductor strained layer and to a method of manufacturing a semiconductor device (10) in which a semiconductor body (11) of silicon is provided, at a surface thereof, with a first semiconductor layer (1) having a lattice of a mixed crystal of ... 10/18/07 - 20070241367 - Ultra scalable high speed heterojunction vertical n-channel misfets and methods thereof A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the ... 07/12/07 - 20070158684 - Compound semiconductor, method of producing the same, and compound semiconductor device An InGaP buffer layer (3) is formed on a semi-insulating GaAs substrate (1) to a thickness of not less than 5 nm and not greater than 500 nm and an InAlAs layer (4) and an InGaAs channel layer (5) are grown thereon to form a heterostructure. An In segregation effect ... 06/21/07 - 20070138505 - Low defect group iii nitride films useful for electronic and optoelectronic devices and methods for making the same In a method for making a low-defect single-crystal GaN film, an epitaxial nitride layer is deposited on a substrate. A first GaN layer is grown on the epitaxial nitride layer by HVPE under a growth condition that promotes the formation of pits, wherein after growing the first GaN layer the ... 06/14/07 - 20070131967 - Self-standing gan single crystal substrate, method of making same, and method of making a nitride semiconductor device A self-standing gallium nitride-based semiconductor single crystal substrate has a surface (Ga-face) mirror-polished, and a rear surface (N-face) having an arithmetic mean roughness Ra of 1 micrometer or more and 10 micrometers or less. A nitride semiconductor device is fabricated such that, before the gallium nitride-based semiconductor single crystal substrate ... 05/24/07 - 20070114566 - Method for making free-standing algan wafer, wafer produced thereby, and associated methods and devices using the wafer A method for making a free-standing, single crystal, aluminum gallium nitride (AlGaN) wafer includes forming a single crystal AlGaN layer directly on a single crystal LiAlO2 substrate using an aluminum halide reactant gas, a gallium halide reactant gas, and removing the single crystal LiAlO2 substrate from the single crystal AlGaN ... 03/15/07 - 20070057287 - Embedded sige stressor with tensile strain for nmos current enhancement MOS devices having localized stressors are provided. Embodiments of the invention comprise a gate electrode formed over a substrate and source/drain regions formed on either side of the gate electrode. The source/drain regions include an embedded stressor and a capping layer on the embedded stressor. Preferably, the embedded stressor has ... 02/22/07 - 20070040188 - Contact or via hole structure with enlarged bottom critical dimension An integrated circuit chip includes a buffer layer, an underlying layer, a dielectric layer, a hole, and barrier layer. The buffer layer is over the underlying layer. The dielectric layer is over the buffer layer. The hole is formed in and extending through the dielectric layer and the buffer layer, ... 02/01/07 - 20070023780 - Semiconductor device and method of manufacturing the same A gate insulating film is formed using a plasma on a three-dimensional silicon substrate surface having a plurality of crystal orientations. The plasma gate insulating film experiences no increase in interface state in any crystal orientations as compared with tat in Si (100) crystal orientation and has a uniform thickness ... 11/16/06 - 20060255363 - Epitaxial substrate, semiconductor element, manufacturing method for epitaxial substrate and method for unevenly distributing dislocations in group iii nitride crystal An epitaxial substrate used to generate a group III nitride crystal having excellent crystal quality. An upper layer of a group III nitride is formed on a sapphire base with an off angle, and after that a heating process is performed at a temperature not lower than 1500° C., and ... 10/26/06 - 20060237745 - Super lattice modification of overlying transistor The invention provides a device having a substrate, a buffer region positioned upon the substrate, wherein the buffer region has an upper buffer region and a lower buffer region, a heterojunction region positioned upon the buffer region, and a superlattice positioned between the lower buffer region and the upper buffer ... 10/26/06 - 20060237744 - Formation of highly dislocation free compound semiconductor on a lattice mismatched substrate A highly dislocation free compound semiconductor, e.g. AlxInyGa1-x-yN (0≦x, y≦1), is formed on a lattice mismatched substrate, e.g. Si, by first depositing a polycrystalline buffer layer on the substrate. A defective layer is then created at or near the interface of the substrate and the polycrystalline buffer layer, e.g. through ... 10/12/06 - 20060226441 - Thin film transistor including organic semiconductor layer and substrate including the same Provided is a thin film transistor including a gate electrode on a substrate; a gate insulating layer on the gate electrode; source and drain electrodes including first source and drain layers on the gate insulating layer, respectively, and spaced apart from each other, wherein at lease one of the first ... 07/20/06 - 20060157732 - Fabrication of mos-gated strained-si and sige buried channel field effect transistors A method of fabricating semiconductor heterostructures including the steps of: (a) positioning a silicon wafer in a suitable environment and (b) processing the silicon substrate by applying several processing steps. A first optional processing step includes growing a graded buffer layer on a silicon substrate by low-energy plasma-enhanced chemical vapor ... 07/06/06 - 20060145187 - Gallium nitride semiconductor and method of manufacturing the same The present invention provides to a gallium nitride (GaN) semiconductor and a method of manufacturing the same, capable of reducing crystal defects caused by a difference in lattice parameters, and minimizing internal residual stress. In particular, since a high-quality GaN thin film is formed on a silicon wafer, manufacturing costs ... 07/06/06 - 20060145186 - Buffer structure for modifying a silicon substrate A buffer structure comprising a compositionally graded layer of a nitride alloy comprising two or more Group IIIB elements, for example La, Y, Sc or Ac, is used to modify a silicon substrate to produce a universal substrate on which a range of target materials, for example GaN, may be ... 06/22/06 - 20060131606 - Lattice-mismatched semiconductor structures employing seed layers and related fabrication methods Fabrication of monolithic semiconductor heterostructures and semiconductor devices based thereon employs isolated seed regions for facilitating elastic lattice conformation between the lattice-mismatched materials. Relative thicknesses of the materials are selected to introduce desirable strain distribution within the heterostructure for improved functionality and performance. ... 04/20/06 - 20060081875 - Transistor with a strained region and method of manufacture A transistor structure comprises a channel region overlying a substrate region. The substrate region comprises a first semiconductor material with a first lattice constant. The channel region comprises a second semiconductor material with a second lattice constant. The source and drain regions are oppositely adjacent the channel region and the ... 01/26/06 - 20060017063 - Metamorphic buffer on small lattice constant substrates A semiconductor device is supported by a substrate with a smaller lattice constant. A metamorphic buffer provides a transition from the smaller lattice constant of the substrate to the larger lattice constant of the semiconductor device. In one application, the semiconductor device has a lattice constant of between approximately 6.1 ... 01/19/06 - 20060011941 - Substrate for growing electro-optical single crystal thin film and method of manufacturing the same A substrate 1 for growing an electro-optical single crystal thin film in which two or more layers of buffer layers 3, 4, and 5 for buffering lattice mismatch between Si and BTO are formed on an Si (001) substrate 2 is provided as a substrate for growing an electro-optical single ... 01/12/06 - 20060006412 - Semiconductor substrate, method of manufacturing the same and semiconductor device A semiconductor substrate comprising a silicon substrate with an oxide film on its surface, on which a silicon layer, a warp-relieved SiGe layer and a warped cap layer are formed in this order, a semiconductor device comprising a transistor, a diode, a capacitor and/or a bipolar transistor formed solely or ... 07/14/05 - 20050151163 - Semiconductor device and manufacturing method thereof A semiconductor device includes a substrate having a first area and a second area adjacent to the first area, a first silicon layer provided on the substrate in the first area, a relaxed layer which is provided on the substrate in the second area and which has a lattice constant ... 06/23/05 - 20050133816 - Iii-nitride quantum-well field effect transistors A transistor with improved device characteristics includes a substrate, a first buffer layer deposited on the substrate, a highly resistive epilayer deposited on the buffer layer, a second epilayer deposited on the highly resistive epilayer, a channel layer deposited on the second epilayer, an AlGaN alloy epilayer deposited on the ... 06/09/05 - 20050121693 - Boron phosphide-based semiconductor device production method thereof light-emitting diode and boron phosphide-based semiconductor layer A boron phosphide-based semiconductor device enhanced in properties includes a substrate (11) composed of a {111}-Si single crystal having a surface {111} crystal plane and a boron phosphide-based semiconductor layer formed on the surface of the substrate and composed of a polycrystal layer (12) that is an aggregate of a ... ### FreshPatents.com Support |