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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Test Or Calibration Structure Test Or Calibration StructureTest Or Calibration Structure patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/31/08 - 20080023702 - Integrated circuit module and method of forming the same A method of forming an integrated circuit module may include interposing an auxiliary PCB between at least one semiconductor chip and a main PCB, the auxiliary PCB having at least one circuit pattern for electrical connection to one of the semiconductor chip and at least one circuit pattern formed on ... 01/31/08 - 20080023701 - Test module for semiconductor device A test module for measuring electrical characteristics of a semiconductor device includes a plurality of shallow trench isolation (STI) layers formed over a semiconductor substrate. An active area includes not only an extended part enclosing the STI layers but also a plurality of minute line-width parts isolated by the STI ... 01/24/08 - 20080017857 - Method of adding fabrication monitors to integrated circuit chips An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions ... 01/24/08 - 20080017856 - Wafer and semiconductor device testing method At least three pads 10A, 10B, 10C are provided on a scribe line 8 located adjacent to a chip region 2. The three pads are a power pad 10A connected to a power potential portion 5 in the chip region 2, a grounding pad 10B connected to a ground potential ... 01/24/08 - 20080017855 - Display substrate, method of manufacturing the same and display device having the same A display substrate includes a pixel, a signal transmission line, a first insulating layer and a test signal input part. The pixel is on an insulating substrate. The signal transmission line is on the insulating substrate to transmit an image signal. The first insulating layer is on the signal transmission ... 01/03/08 - 20080001147 - Semiconductor device and method for manufacturing the same In a circuit area wherein a semiconductor integrated circuit is to be formed, an isolation insulating film is formed on a surface of a semiconductor substrate (11), and, at the same time, five isolation insulating films (12m) extending in one specific direction are formed within a monitor area (1) at ... 01/03/08 - 20080001146 - Semiconductor device Provided is a semiconductor device, in which: patterns for detecting displacement at probing are formed of a plurality of minute conductors formed below a protective film; each of the plurality of minute conductors formed below the protective film is electrically insulated and formed to be smaller than a bottom surface ... 01/03/08 - 20080001145 - Handler for testing packaged chips A handler for testing packaged semiconductor chips includes a tray-transferring apparatus. Transferring members in the form of rods with external screw threads hold sides of the tray. The rods are rotated together to move the trays in a longitudinal direction. A driving unit rotates the rods together. The tray-transferring apparatus ... 12/13/07 - 20070284578 - Array substrate for liquid crystal display and method of testing An array substrate including a signal line, a test line to inspect the open of the signal line and fault of the pixels, and a fuse electrically connecting the signal line with the test line. The fuse is opened when a current higher than a reference current is applied thereto. ... 12/13/07 - 20070284576 - Semiconductor circuit arrangement and associated method for temperature detection A semiconductor circuit arrangement and a method for temperature detection is disclosed. One embodiment includes a semiconductor substrate, on which is formed a first insulating layer and thereon a thin active semiconductor region, which is laterally delimited by a second insulating layer. In the active semiconductor region, a first and ... 11/22/07 - 20070267632 - Apparatus and method for test structure inspection Herein are described layouts of test structures and scanning methodologies that allow large probe currents to be used so as to allow the detection of resistive defects with a resistance lower than 1 MΩ while at the same time allowing a sufficient degree of localization to be obtained for root ... 11/15/07 - 20070262306 - Semiconductor device having microstructure and method of manufacturing microstructure A semiconductor device having a microstructure and a method of manufacturing a microstructure are provided, suppressing any change of characteristics in a wafer state caused in an assembly step. Specifically, a wafer where a plurality of microstructure chips are formed and a dummy wafer are attached to each other using ... 11/15/07 - 20070262305 - Integrated circuit protection from esd damage during fabrication A semiconductor integrated circuit wafer containing a plurality of integrated circuit chips and having a common substrate, each chip formed with an internal region in the interior of the chip and a removable external region on the perimeter of the internal region and circuitry disposed preferably in the external region ... 11/01/07 - 20070252143 - Semiconductor memory element and lifetime operation starting apparatus therefor An example memory includes an address control portion, a protection film, a property deterioration material layer, data storage areas, and bonding pads. The protection film protects an organic semiconductor layer of a semiconductor circuit and prevents intrusion of moisture or chemical molecules in the air, light, or the like, into ... 10/18/07 - 20070241330 - Semiconductor integrated circuit device and manufacture thereof In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may ... 10/18/07 - 20070241328 - Process for producing power semiconductor components using a marker A power semiconductor component and process for producing power semiconductor components is disclosed. In one embodiment, a power semiconductor component is produced, including applying a semiconductor ship to a substrate using a fluorescent marker substance. ... 10/04/07 - 20070228372 - Method for fabricating a body contact in a finfet structure and a device including the same A method for fabricating a Finfet device with body contacts and a device fabricated using the method are provided. In one example, a silicon-on-insulator substrate is provided. A T-shaped active region is defined in the silicon layer of the silicon-on-insulator substrate. A source region and a drain region form two ... 10/04/07 - 20070228371 - Method for evaluating semiconductor device The present invention provides a method for evaluating an intended element or a parameter. In addition, the invention provides an evaluation method for obtaining a more precise result rapidly. According to the invention, a plurality of evaluation circuits are formed over the same substrate, and while simultaneously operating the plurality ... 09/27/07 - 20070221920 - Semiconductor component having test pads and method and apparatus for testing same A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is ... 09/20/07 - 20070215874 - Layout and process to contact sub-lithographic structures An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second structures are nested such that the sub-lithographic lines are disposed ... 09/13/07 - 20070210306 - Test pattern for measuring contact short at first metal level The invention relates to a test structure and methods of detecting electrical defects between adjacent metal contacts using such test structure at the first metal level within a semiconductor device. The test structure includes dual first metal level comb structures each having extending lines that are in direct electrical communication ... 08/16/07 - 20070187679 - Technique for evaluating a fabrication of a die and wafer The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known ... 07/26/07 - 20070170425 - Semiconductor integrated circuit device and test method thereof The present invention provides a high-quality semiconductor integrated circuit device, where the semiconductor integrated circuit device, a SiP or especially PoP semiconductor integrated circuit device, enables a simultaneous testing of the reliability of multiple upper and lower semiconductor integrated circuit elements; it also enables a testing of only the non-defective ... 07/19/07 - 20070164279 - Semiconductor chip A semiconductor chip comprises a metal pad exposed by an opening in a passivation layer, wherein the metal pad has a testing area and a bond area. During a step of testing, a testing probe contacts with the testing area for electrical testing. After the step of testing, a polymer ... 07/05/07 - 20070152216 - Interconnection in an insulating layer on a wafer An interconnection in an insulating layer on a wafer is described herein. A wafer having a plurality of conductive lines thereon is provided. An insulating layer is formed over the conductive lines. Two via holes are formed in the insulating layer to expose two of the conductive lines waiting to ... 07/05/07 - 20070152215 - Test pads on flash memory cards A semiconductor package is disclosed including test pads formed of solder bumps affixed to the semiconductor package during fabrication. When the package is encapsulated, due to the pressure exerted on the package during the encapsulation process, portions of the solder bumps get flattened out to be generally flush with and ... 06/28/07 - 20070145366 - Semiconductor structures A method and a structure are provided for preventing lift-off of a semiconductor monitor pattern from a substrate . A semiconductor structure and a semiconductor monitor structure are formed on a substrate. A material layer is formed covering the semiconductor monitor structure. A part of the semiconductor structure is removed ... 06/28/07 - 20070145365 - Image sensor Embodiments relate to and image sensor. In embodiments, the image sensor may include a semiconductor substrate, a photodiode region, a gate electrode, a dummy gate, and an interlayer dielectric layer. The semiconductor substrate includes a field oxide layer. The photodiode region may be formed on the semiconductor substrate. The gate ... 06/28/07 - 20070145364 - Test pattern for analyzing delay characteristic of interconnection line and method for analyzing delay characteristic of interconnection line using the same A test pattern for analyzing a delay characteristic of an interconnection line and a method of analyzing a delay characteristic of an interconnection line using the test pattern are provided. The test pattern for analyzing a delay characteristic of an interconnection line includes: a first metal line formed as a ... 06/28/07 - 20070145363 - Testing memory integrated circuits A memory device may include a controller and a plurality of flash memory dice. The controller is provided for read and write access and communications with a host. However, the controller may also be utilized to test one or more of the flash memory dice mounted on the device. In ... 06/21/07 - 20070138465 - Fabrication and test methods and systems Methods and systems for fabricating and testing semiconductor devices are disclosed. In one embodiment, a method of forming a material includes providing a first workpiece, forming a material on the first workpiece using a first process condition, and measuring a defect state of the material using a test that utilizes ... 06/14/07 - 20070131931 - Semiconductor wafer and semiconductor device, and method for manufacturing same There is a room for improvement in conventional semiconductor devices in terms of reducing the chip area. A semiconductor device 1 comprises an evaluation transistor 10 (first characteristic evaluation device), an evaluation transistor (second characteristic evaluation device), measurement pads 30 (first measurement pads) and measurement pads 40 (second measurement pads). ... 06/14/07 - 20070131930 - Semiconductor device and method for fabricating the same The following steps are carried out: forming a gate electrode on a semiconductor substrate with a gate insulating film interposed therebetween, forming a dummy gate electrode on the semiconductor substrate with a dummy gate insulating film interposed therebeweeen and forming another dummy gate electrode on the semiconductor substrate with an ... 05/31/07 - 20070120125 - Semiconductor integrated circuit device and method of testing the same Functional circuits such as a processor, an SRAM, a DRAM and a flash-EEPROM are mounted on a semiconductor chip. Of these functional circuits, for example, the flash-EEPROM which fluctuates a potential of the semiconductor chip is separated from the other circuits by means of a separating region provided in the ... 05/24/07 - 20070114529 - Scan testing system, method and apparatus Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to ... 05/10/07 - 20070102701 - Structure and method for parallel testing of dies on a semiconductor wafer In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a ... 05/10/07 - 20070102700 - Electrical open/short contact alignment structure for active region vs. gate region An apparatus and method are disclosed for measuring alignment of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias or misalignment. Bridging vertices on the polysilicon shapes are formed. Bridging vertices over the silicon area create low ... 05/03/07 - 20070096095 - Test pattern for semiconductor device and method for measuring pattern shift There are provided a test pattern for a semiconductor device includes a buried layer formed on a surface of a substrate; a semiconductor layer formed on an entire surface of the substrate; and first and second high-concentration impurity regions formed in the surface of the semiconductor layer and electrically connected ... 05/03/07 - 20070096094 - Methods and apparatus for designing and using micro-targets in overlay metrology Methods and apparatus for fabricating a semiconductor die including several target structures. A first layer is formed that includes one or more line or trench structures that extend in a first direction. A second layer is formed that includes one or more line or trench structures that extend in a ... 05/03/07 - 20070096093 - Calibration technique for measuring gate resistance of power mos gate device at wafer level This invention discloses a method for calibrating a gate resistance measurement of a semiconductor power device that includes a step of forming a RC network on a test area on a semiconductor wafer adjacent to a plurality of semiconductor power chips and measuring a resistance and a capacitance of the ... 05/03/07 - 20070096092 - Semiconductor device fault detection system and method An outer border, and a seal ring substantially co-extensive with and spaced from the outer border is disclosed. A plurality of fault detection chains extend from adjacent the outer border to within the seal ring. At least a first one of the plurality of fault detection chains includes a contact ... 05/03/07 - 20070096091 - Layer structure and removing method thereof and mehod of testing semiconductor machine A method of testing a semiconductor machine is provided. A wafer is provided and a removable auxiliary layer is formed on the wafer. A low dielectric constant dielectric layer with an expected thickness is formed on the removable auxiliary layer. The actual thickness of the low dielectric constant dielectric layer ... 04/26/07 - 20070090356 - Semiconductor device A semiconductor device includes a semiconductor substrate having electrodes, a resin layer provided on the surface of the semiconductor substrate on which the electrodes are formed and having concave portions formed on a second surface on the other side of a first surface facing the semiconductor substrate, test pads electrically ... 04/26/07 - 20070090355 - Single separable electrode and self-contained pad viability tester A single separable electrode that includes a plurality of separable electrically connected electrode sections. ... 04/12/07 - 20070080347 - Test pattern of cmos image sensor and method of measuring process management using the same The test pattern according to the present invention consists of an opaque metal film pattern formed on a semiconductor substrate, an insulating film formed on the semiconductor substrate and the metal film pattern, a red color filter formed on the insulating film, a planarization layer formed on the insulating film ... 03/29/07 - 20070069208 - Lsi design support apparatus and lsi design support method An LSI design support apparatus includes a data acquisition section and an equal processing section. The data acquisition section acquires first position data concerning positions of a plurality of first electrodes provided along a side of a first substrate, and second position data concerning positions of a plurality of second ... 03/29/07 - 20070069207 - Method and system of trace pull test The present invention provides an efficient test method and system for testing the IC package, such as BGA types of packages. With the present invention, manufacturer can have an easier way in testing various types of packages, including newer types. Manufacturer also can get the testing outcome which is more ... 03/08/07 - 20070051951 - Method for testing metal-insulator-metal capacitor structures under high temperature at wafer level A test methodology is provided for testing metal-insulator-metal (MIM) capacitor structures under high temperatures at the wafer level. A resistor is formed on a region of dielectric isolation material formed in a semiconductor substrate. The MIM capacitor is formed over the resistor and separated therefrom by dielectric material. A metal ... 03/08/07 - 20070051950 - Method for generating test patterns utilized in manufacturing semiconductor device A method for generating test patterns utilized in manufacturing a semiconductor device includes creating mini-data concerning a partial area pattern used in designing the semiconductor device, subjecting the mini-data to data processing in accordance with a condition of a manufacturing process of the semiconductor device, thereby creating processed mini-data, extracting ... 03/08/07 - 20070051949 - Method and arrangment for testing a stacked die semiconductor device A semiconductor device and related testing methods and configurations are provided to enable parallel (simultaneous) testing of multiple chips on a stacked multiple chip semiconductor device. Each chip in the device is configured to selectively output test results to one or more unique contacts on a substrate of the device. ... 03/08/07 - 20070051948 - Test structure and method for detecting and studying crystal lattice dislocation defects in integrated circuit devices A test structure (200, 200′) having an array (224) of test devices (220) for detecting and studying defects that can occur in an integrated circuit device, e.g., a transistor (144), due to the relative positioning of one component (100) of the device with respect to another component (108) of the ... 02/15/07 - 20070034868 - Semiconductor device and test system thereof A semiconductor device that includes a clock buffer, which generates an internal clock signal in response to a clock signal and a complementary clock signal if the semiconductor device is operating in a first mode and generates the internal clock signal in response to the clock signal and a reference ... 02/08/07 - 20070029549 - Providing current control over wafer borne semiconductor devices using overlayer patterns Disclosed are methods for providing wafer parasitic current control to a semiconductor wafer (1240) having a substrate (1240), at least one active layer (1240) and at least one surface layer (1240), Current control can be achieved through the formation of patterns (1240) surrounding contacts (1215), said patterns (1240) including insulating ... 01/25/07 - 20070018158 - Apparatus for separating metal coating film and method for separating metal coating film A metal coating removing apparatus (1) includes a first electrode (13) arranged so as to be opposed to a metal coating (101) as an object to be removed, a second electrode 14 arranged so as to be opposed to the metal coating (101) at a predetermined distance from the first ... 01/18/07 - 20070012917 - Pixel with transfer gate with no isolation edge A pixel and imager device, and method of forming the same, where the pixel has a transfer transistor gate associated with a photoconversion device and is isolated in a substrate by shallow trench isolation. The transfer transistor gate does not overlap the shallow trench isolation region. ... 01/11/07 - 20070007521 - Semiconductor device and test method of semiconductor device There is provided a semiconductor device comprising, a function unit portion including a circuit element, rank data presenting results of a rank-classification test on the circuit element, the rank-classification test being performed on the basis of a plurality of test criteria on wafer state, a non-volatile memory portion in which ... 01/11/07 - 20070007520 - Display substrate, method of manufacturing the same and display apparatus having the same A display substrate includes a plastic substrate, a gate wiring, a gate insulation layer, an active layer, a data wiring and a drain wiring. The gate wiring includes a gate line and a gate electrode portion that is electrically connected to the gate line. The active layer is formed on ... 01/11/07 - 20070007519 - Failure prediction for parallel mosfets Power conversion circuits often consist of several MOSFETs operating in parallel. Due to thermal cycling and mechanical operations, MOSFETs or the respective electric connections of the MOSFETs may fail. According to the present invention, there is provided a diagnosis circuit for a plurality of parallel MOSFETs, which predicts or determines ... 01/04/07 - 20070001168 - Semiconductor components and assemblies including vias of varying lateral dimensions Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. A first opening and a second opening are formed in a substrate such that the first opening and the second opening are in communication with each other. A portion ... 12/28/06 - 20060289863 - Semiconductor device evaluation apparatus and semiconductor device evaluation method An apparatus for evaluating a field-effect transistor includes a pulse generator, a current/voltage converter, a switch and a first constant-voltage source. The pulse generator can be electrically connected to a gate electrode of a field-effect transistor. The current/voltage converter includes an input terminal. The input terminal can be electrically connected ... 12/28/06 - 20060289862 - Systems and methods for thermal sensing Systems and methods for positioning thermal sensors within an integrated circuit in a manner that provides useful thermal measurements corresponding to different parts of the integrated circuit. In one embodiment, an integrated circuit includes multiple, duplicate functional blocks. A separate thermal sensor is coupled to each of the duplicate functional ... 12/28/06 - 20060289861 - Systems and arrangements to interconnect components of a semiconductor device Systems and arrangements to interconnect cells and structures within cells of an integrated circuit to enhance cell density are disclosed. Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasing ACLV tolerance with a fixed polysilicon gate pitch. In some embodiments, the ... 12/21/06 - 20060284174 - Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer An arrangement that will provide multiple communication paths for the simultaneously testing of a plurality of un-diced chips on a semiconductor wafer that will simultaneously permit each such communication path to service more than one chip while using a minimum number of tester contacts. These and other objects, features and ... 12/21/06 - 20060284173 - Method to test shallow trench isolation fill capability A shallow trench isolation (STI) test pattern comprising a plurality of test structures. Each of the test structures comprise at least two lines comprising a predefined line length, line width, and gap between the lines. At least one of the line length, line width and gap are different between each ... 12/14/06 - 20060278871 - Detecting and improving bond pad connectivity with pad check A method for analyzing an integrated circuit (or constituent parts thereof), a computer program implementing the method, and a computer configured to execute the program is disclosed. Analyzing the integrated circuit may include retrieving a design for the integrated circuit from a layout database, identifying the bond pads and gates ... 12/07/06 - 20060273313 - Ic packaging technique An IC packaging technique uses a recyclable and environmental benign plastic material (such as a thermal plastic material) to perform packaging to an IC chip, in order to solve shortcomings of an inability of being recycled of a thermosetting material, an inability of reprocessing and repairing the IC, and a ... 11/30/06 - 20060267010 - Semiconductor device, semiconductor device manufacturing method, and semiconductor device test method A semiconductor device manufacturing method includes forming a first layer and a second layer being different from the first layer, the first layer having a plurality of first test elements, the second layer having a plurality of pads, and adhering the first and second layers to electrically connect the first ... 11/30/06 - 20060267009 - Method for local wafer thinning and reinforcement A method is provided for preparing a semiconductor wafer for testing. The method includes selecting a die to be tested; measuring a diagonal of the die; thinning an area over the die extending beyond the scribe lines, the thinned area may be a circular area having a diameter that is ... 11/30/06 - 20060267008 - Semiconductor bond pad structures and methods of manufacturing thereof Described is a semiconductor device having improved semiconductor bond pad reliability and methods of manufacturing thereof. The semiconductor device includes a layer formed over an integrated circuit on a semiconductor substrate. The first layer includes a conductive portion and an insulating portion. A second layer is then formed over the ... 11/09/06 - 20060249729 - Methods of and apparatuses for measuring electrical parameters of a plasma process A sensor apparatus for measuring a plasma process parameter for processing a workpiece. The sensor apparatus includes a base, an information processor supported on or in the base, and at least one sensor supported on or in the base. The at least one sensor includes at least one sensing element ... 10/19/06 - 20060231835 - Semiconductor device including rom interface pad A semiconductor device comprises a multilayer formed on a semiconductor substrate, the multilayer including a first circuit pattern, a second circuit pattern for testing the semiconductor device, the second circuit formed on a predetermined region of the multilayer, an inter-metal insulating layer formed on the second circuit pattern, a plurality ... 10/19/06 - 20060231834 - Bonding strength testing device A bonding strength test device suits to perform a bonding strength test for at least one solder ball that fixed on a substrate. The bonding strength test device includes a fixed base and an impact apparatus. The impact apparatus has a first end and a second end corresponding to the ... 10/19/06 - 20060231833 - High-frequency, high-signal-density, surface-mount technology footprint definitions Methods for designing SMT connector footprints are disclosed. A circuit board may have disposed thereon an arrangement of SMT pads and corresponding vias. The arrangement of vias may differ from the arrangement of SMT pads. The arrangement of SMT pads may differ from the arrangement of contacts in a connector ... 10/05/06 - 20060220013 - Techniques for facilitating identification updates in an integrated circuit An integrated circuit comprises an identification portion having an output representative of one or more bits of digital information identifying the integrated circuit. This identification information may, for example, allow the manufacturer to determine which photolithographic masks were used to manufacture the integrated circuit. The identification portion is formed at ... 10/05/06 - 20060220012 - Test key having a chain circuit and a kelvin structure A test key formed on a semiconductor substrate has a plurality of electronic components, a plurality of conductors, a plurality of vias for connecting the electronic components and the conductors, a first pad, a second pad, a third pad, and a fourth pad. The first pad, the electronic components, the ... 09/28/06 - 20060214164 - Semiconductor device and method of manufacturing the device based on evaluation data of test transistors uniformly arranged on test wafer This patent specification describes a method of manufacturing semiconductor device which includes providing a test wafer having a plurality of test transistors formed on a substrate and uniformly arranged in a substantially whole area of the test wafer, measuring characteristic of the test transistors and implanting onto a manufacturing wafer ... 09/21/06 - 20060208256 - Self-calibration in non-contact surface photovoltage measurement of depletion capacitance and dopant concentration The surface photovoltage dopant concentration measurement of a semiconductor wafer is calibrated by biasing the semiconductor wafer into an avalanche breakdown condition in a surface depletion region; determining a contact potential difference value corresponding to an avalanche breakdown; determining small signal ac-surface photovoltage value corresponding to an avalanche breakdown; and ... 09/14/06 - 20060202201 - Wafer-level package having test terminal A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least one external connection terminal, at least one redistribution trace provided on the semiconductor wafer, at ... 08/31/06 - 20060192200 - Test key structure A test key structure includes a substrate, a closed loop, a plurality of spacers, a plurality of first and second doping regions and a plurality of contacts. The closed loop having two conductive lines and two connection portions is located on the substrate. Each connection portion connects to one end ... 08/24/06 - 20060186406 - Method and system for qualifying a semiconductor etch process A method of manufacturing a semiconductor device by qualifying an etch process. A semiconductor substrate is subjected to a predefined etch process to produce a partially-etched film. A scatterometry signature of the partially-etched film is produced. The scatterometry signature is used to determine if a physical property of the partially-etched ... 08/24/06 - 20060186405 - Semiconductor device and manufacturing process therefor A semiconductor device 100 has a probing mark 111 forming region; a bonding pad 110 having a bonding region 113; and a check mark 120 separate from the bonding pad 110. In the configuration, the probing mark 111 forming region and the bonding region 113 can be identified on the ... 08/24/06 - 20060186404 - Dummy wafer A dummy wafer including a carbon fiber reinforced plastic (CFRP). Specifically the dummy wafer has a wafer substrate including CFRP, the substrate has two skin layers disposed on respective principal surface side and a core layer interposed between the skin layers, and each of the skin layers has multiple one-dimensionally ... 08/24/06 - 20060186403 - Semiconductor device The present invention is such that a semiconductor device has, on a substrate (10), a first functional area (1) (for example, a storage element area) and a second functional area (2) (for example, a driving circuitor signal processing circuit), wherein, if the substrate (10) is viewed in a planar fashion, ... 08/10/06 - 20060175607 - Semiconductor device, device forming substrate, wiring connection testing method, and manufacturing method of the semiconductor device A semiconductor device includes a substrate, a semiconductor element formed on the substrate, and a wiring connection testing structure which is formed on the substrate and which includes an electron beam irradiation area where an electron beam is irradiated so that a wiring connection is tested. The wiring connection testing ... 08/10/06 - 20060175606 - Subthreshold design methodology for ultra-low power systems A system and method for enabling a device to function at a subthreshold voltage level of the device is provided. Generally, the system contains a subthreshold data memory capable of functioning when a supply voltage is within the subthreshold voltage level of the device. The system also contains control logic ... 08/03/06 - 20060169977 - Liquid detection end effector sensor and method of using the same Liquid detection sensors are attached to both sides of a robotic arm end effector of a semiconductor wafer process system. The sensor mechanism or probe is situated on the front side and backside of the end effector, designed with electrical lines that are traced onto a polyester base material. The ... 07/27/06 - 20060163572 - Semiconductor memory testing device and test method using the same A test device for a semiconductor memory device includes a clock frequency multiplier, a data input buffer, a test data generator and a data output buffer. The clock frequency multiplier multiplies an external clock signal having a relatively low frequency provided from an external test device to generate an internal ... 07/27/06 - 20060163571 - Test element group structures having 3 dimensional sram cell transistors A test element group structure having 3-dimensional SRAM cell transistors includes a bulk metal-oxide-semiconductor (MOS) transistor formed at a semiconductor substrate and a first interlayer insulating layer covering the bulk MOS transistor. A lower thin film transistor is disposed on the first interlayer insulating layer, and the lower thin film ... 07/27/06 - 20060163570 - Aerodynamic jetting of aerosolized fluids for fabrication of passive structures Method and apparatus for direct writing of passive structures having a tolerance of 5% or less in one or more physical, electrical, chemical, or optical properties. The present apparatus is capable of extended deposition times. The apparatus may be configured for unassisted operation and uses sensors and feedback loops to ... 07/27/06 - 20060163569 - Test structure of semiconductor device A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate ... 07/27/06 - 20060163568 - Integration system and the method for operating the same An integration system for obtaining a set of overlay offset parameters of a first process layer which is going to be formed in an assigned photolithography tool with an assigned mask and an assigned pre-tool. By using the integration system, the set of overlay offset parameters of the first process ... 07/20/06 - 20060157703 - Charged plate,cdm simulator and test method Disclosed is a simulator in which there are provided a field plate for electrostatically charging a device under test, which comprises a first substrate (high resistance substrate) having a relatively high resistance and a substrate having a predetermined dielectric constant; and a ground plate for discharging the charged device which ... 07/20/06 - 20060157702 - Kerf with improved fill routine A semiconductor disk which exhibits chip areas arranged next to one another and separated from one another by a kerf. The chip areas in each case exhibit a multiplicity of similar device patterns, such that at least one fill area with fill patterns is arranged in the kerf, and the ... 07/20/06 - 20060157701 - Integrated sensor chip unit The invention relates to a sensor module, in particular a measured-value pickup (2) for determining measurement data and a circuit arrangement (3) for enabling a wire-free power supply and interrogation of the measurement data. The measured-value pickup is formed as an integrable sensor (2), and the circuit arrangement is formed ... 07/20/06 - 20060157700 - Semiconductor wafer with test structure The invention relates to a semiconductor wafer (1) having a plurality of first sawing regions (201-211) running parallel to one another in a first direction (X) and a plurality of second sawing regions (301-311) running parallel to one another in a second direction (Y), having useful regions (10) which in ... 07/20/06 - 20060157699 - Test structure for integrated electronic circuits A test structure for integrated electronic circuits having a substantially planar substrate coated with a plurality of metallization layers comprises a switching element formed on the surface of the substrate. It also comprises a tunnel formed in one or more metallization layers between the top of the switching element and ... 07/20/06 - 20060157698 - Semiconductor manufacturing system, semiconductor device and method of manufacture A semiconductor manufacturing system for accurately recognizing the timing of maintenance of the system includes a processing chamber (101) and a movable member (107) moving in and out of the processing chamber (101). The movable member (107) has a sensor (106) for observing a state in the processing chamber (101). ... 07/20/06 - 20060157697 - System and method for adjusting a manufacturing condition of an electronic device and method for manufacturing an electronic device A system for adjusting a manufacturing condition of an electronic device includes: an inspection tool configured to inspect a plurality of protrusions on a substance layer for manufacturing an electronic device; a height calculation unit configured to calculate each of heights of the protrusions, based on the inspection result; and ... 07/13/06 - 20060151785 - Semiconductor device with split pad design A semiconductor device includes a device body, a pad and a signal distribution runner. The device body includes a plurality of parallel cells and at least one integrated electronic component. The pad is located on a surface of the device body and includes a first portion and a second portion ... 07/13/06 - 20060151784 - Photonic devices and pics including sacrificial testing structures and method of making the same A testing structure formed on a photonic integrated circuit including a plurality of first photonic components and having a given functionality corresponding to a given interconnectivity of the first photonic components, the testing structure including: at least one second photonic component being suitable for testing at least one of the ... 07/13/06 - 20060151783 - Semiconductor integrated circuit device A semiconductor integrated circuit device includes a digital circuit part and an analog circuit part that are disposed on a surface of one semiconductor substrate. A dummy layer part made of polysilicon that is the same as polysilicon composing a gate of a transistor is disposed between the digital circuit ... 07/06/06 - 20060145152 - Composite pattern for monitoring various defects of semiconductor device A composite monitor is capable of determining a variety of defects of a semiconductor device. The composite monitor has an isolation region in a well region, an active region pattern in the well region and defined by the isolation region, and a metal line pattern partially overlying the active region ... 06/29/06 - 20060138411 - Semiconductor wafer with a test structure, and method The invention proposes a semiconductor wafer with a test structure for detecting parasitic contact structures on the semiconductor wafer, in which a first interconnect plane (A) contains interconnects (1) running parallel to one another and a second interconnect (2) that is arranged between the latter. The two first interconnects (1) ... 06/29/06 - 20060138410 - Method for measuring information about a substrate, and a substrate for use in a lithographic apparatus A method for measuring information provided by a substrate is disclosed. The substrate includes a feature that has been created by a lithographic apparatus. The method includes projecting a beam of light onto a marker disposed above and/or near the feature on the substrate, and detecting information provided by the ... 06/22/06 - 20060131578 - Structure of semiconductor substrate including test element group wiring A structure of test element group wiring includes, in addition to an electrode on a substrate including one or more layers of insulating films, and real wirings electrically connected to the electrode, includes dummy wirings electrically isolated from the electrode and having a portion of the same shape as the ... 06/22/06 - 20060131577 - Isolation circuit An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is provided to transfer the other signal from the second pad to the third pad in ... 06/22/06 - 20060131576 - Semiconductor device having overlay measurement mark and method of fabricating the same There are provided a semiconductor device having an overlay measurement mark, and a method of fabricating the same. The semiconductor device includes a scribe line region disposed on a semiconductor substrate. A first main scale layer having a first group of line and space patterns and a second group of ... 06/22/06 - 20060131575 - Electronic device and manufacturing method thereof An electronic device includes an element group which generates a specific identification number and is composed of a plurality of elements. The specific identification number is set based on irregular deviation in electric characteristic of the elements which is caused due to a random failure in a manufacturing process. ... 06/22/06 - 20060131574 - Nanowire sensor and method of manufacturing the same Provided are a nanowire sensor and a method of manufacturing the same. The nanowire sensor includes: a sensing target system comprising a target element to be detected; two electrodes separated from each other contained in the sensing target system; vanadium oxide (V2O5) nanowires incorporated in the sensing target system and ... 06/15/06 - 20060124928 - Integrated circuit disabling A method and a circuit for protecting at least one element of an integrated circuit, including conditioning the operation of the element to be protected to the state of a signal conditioned by an irreversibly programmable element, the state of which is set during a probe test of the integrated ... 06/15/06 - 20060124927 - Iridium oxide nanostructure Methods of forming a conductive structure on a substrate prior to packaging, and a test probe structure generated according to the method, are disclosed. The conductive structure includes a high aspect ratio structure formed by injected molded solder. The invention can be applied to form passive elements and interconnects on ... 06/08/06 - 20060118785 - Techniques for patterning features in semiconductor devices Techniques for semiconductor processing are provided. In one aspect, a method for patterning one or more features in a semiconductor device comprises the following step. At least one critical dimension of the one or more features is reduced during etching of the antireflective material. A lithographic structure is also provided. ... 06/08/06 - 20060118784 - Structure and method for failure analysis in a semiconductor device In a method and structure for semiconductor failure analysis, the structure comprises: a plurality of analytic fields disposed on a predetermined area of a semiconductor device; semiconductor transistors arranged in each of the analytic fields, the semiconductor transistors arranged in an array; wordlines arranged on each of the plurality of ... 06/01/06 - 20060113535 - Probe look ahead: testing parts not currently under a probehead A semiconductor substrate, probe card, and methods for stressing and testing dies on a semiconductor substrate are provided. The semiconductor substrate, typically a semiconductor wafer, comprises dies disposed thereon and a redistribution layer (RDL) for routing signals from a test circuit into dies on the substrate that are not currently ... 06/01/06 - 20060113534 - Test structure of semiconductor device A test structure of a semiconductor device with improved test reliability is provided. The test structure includes first and second active regions which are electrically isolated from each other and on which silicided first and second junction regions are formed, respectively, a semiconductor substrate or a well which is formed ... 06/01/06 - 20060113533 - Semiconductor device and layout design method for the same In layout design of a semiconductor device including a device forming region formed on a substrate; an isolation region formed on the semiconductor substrate so as to surround the device forming region; a gate electrode formed on the device forming region; and a gate interconnect connected to the gate electrode ... 06/01/06 - 20060113532 - Multidirectional leakage path test structure A test structure for testing a multidirectional current leakage path. A first doped region of a first conductivity is in the first well of the first conductivity in a substrate, in which the first doped region has a dopant concentration higher than the first well has. A first contact is ... 05/25/06 - 20060108583 - System and method for removing film from planar substrate peripheries A system for removing film from a planar substrate includes a shuttle which transports a film-coated substrate through a film removal station to a rotation station. At the rotation station, the substrate is removed from the shuttle and rotated to a new orientation. After being repositioned on the shuttle, the ... 05/11/06 - 20060097253 - Structured semiconductor element for reducing charging effects A semiconductor circuit element for reducing undesirable charging effects for a connection element of test structures for semiconductor circuits is disclosed. A surface of a semiconductor circuit element has interconnect structures that are electrically insulated from the remainder of the surface of the semiconductor circuit element, where exclusively the interconnect ... 05/04/06 - 20060091384 - Substrate testing apparatus with full contact configuration A substrate testing apparatus with full contact configuration. The apparatus includes a jig and a full-contact probe substrate. The jig has a conductive tape disposed thereon for fully electrically connecting a plurality of first connecting pads disposed on an upper surface of a substrate strip. The full-contact probe substrate has ... 05/04/06 - 20060091383 - Semiconductor structure and testing method thereof A semiconductor structure and a testing method thereof are provided. The semiconductor structure comprises a substrate, a well, an isothermal heating layer, a first dielectric layer, an interconnection material layer and a second dielectric layer. Wherein, the well is disposed in the substrate, the isothermal heating layer is disposed over ... 04/20/06 - 20060081842 - Monitor pattern of semiconductor device and method of manufacturing semiconductor device A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by contact vias. In the same wiring layer as that of the wirings, a dummy pattern is formed so as to ... 04/13/06 - 20060076558 - Semiconductor device and manufacturing method thereof An object of the present invention is to prevent a junction leakage current generation across a pn junction formed under a silicide layer, even when a direct probing to an electrode formed of the silicide layer is performed. There is provided a semiconductor device including an element for evaluation, wherein ... 04/06/06 - 20060071209 - Biopolymer resonant tunneling with a gate voltage source The invention provides an apparatus and method for sequencing and identifying a biopolymer. The invention provides a first electrode, a second electrode, a first gate electrode, a second gate electrode, a gate voltage source and a potential means. The gate electrodes may be ramped by a voltage source to search ... 04/06/06 - 20060071208 - Inspection methods and structures for visualizing and/or detecting specific chip structures The present invention provides inspection methods and structures for facilitating the visualization and/or detection of specific chip structures. Optical or fluorescent labeling techniques are used to “stain” a specific chip structure for easier detection of the structure. Also, a temporary/sacrificial illuminating (e.g., fluorescent) film is added to the semiconductor process ... 03/23/06 - 20060060845 - Bond pad redistribution layer for thru semiconductor vias and probe touchdown A semiconductor device having a conductive layer above a dielectric layer and a top metal layer. The conductive layer is patterned to form an alternate probe area to test the functionality of active circuitry within the semiconductor device and patterned to electrically route a thru semiconductor via within the semiconductor ... 03/23/06 - 20060060844 - Electrical open/short contact alignment structure for active region vs. gate region An apparatus and method are disclosed for measuring alignment of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias or misalignment. Bridging vertices on the polysilicon shapes are formed. Bridging vertices over the silicon area create low ... 03/23/06 - 20060060843 - Resistor structures to electrically measure unidirectional misalignment of stitched masks An apparatus and method for matched variable resistor structures to electrically measure unidirectional misalignment of stitched masks for etched interconnect layers includes a first test pad (101) and a second test pad (102) for measuring resistance therebetween; a first resistive element (105) electrically connected at a first end to the ... 03/09/06 - 20060049400 - Semiconductor device A first wiring part in a first wiring layer is a starting terminal that is connected to a ground potential. The first wiring part and a second wiring part in a second wiring layer are connected by a first connecting part. The second wiring part and a third wiring part ... 03/02/06 - 20060043364 - Methods for applying front side and edge protection material to electronic devices at the wafer level, devices made by the methods, and systems including the devices Methods for applying a dielectric protective layer to a wafer in wafer-level chip scale package manufacture. A flowable dielectric protective material with fluxing capability is applied over the active surface of an unbumped semiconductor wafer to cover active device areas, bond pads, test socket contact locations, and optional pre-scribed wafer ... 02/23/06 - 20060038172 - Apparatus and methods for wafer-level testing of the chip-scale semiconductor device packages A test chuck is configured for assembly with, and to test, semiconductor devices of a large-scale substrate. The test chuck includes a substrate with terminals that are arranged correspondingly to the arrangement of bond pads or other contacts of the semiconductor devices, which have yet to be singulated from the ... 02/23/06 - 20060038171 - Semiconductor integrated circuit design tool, computer implemented method for designing semiconductor integrated circuit, and method for manufacturing semiconductor integrated circuit A semiconductor integrated circuit design tool includes a reference data defining module configured to define design data of one of transistors implementing the semiconductor integrated circuit as reference data, a simulator configured to simulate on each effective channel length of the transistors, based on the design data and a reference ... 02/16/06 - 20060033100 - Anisotropically conductive connector and production process thereof, and probe member An anisotropically conductive connector, by which positioning, and holding and fixing to a wafer to be inspected can be conducted with ease even when the wafer has a large area, contains a frame plate having a plurality of anisotropically conductive film-arranging holes formed corresponding to regions of electrodes to be ... 02/02/06 - 20060022197 - Technique for evaluating local electrical characteristics in semiconductor devices By providing a test structure including a plurality of test pads, the anisotropic behavior of stress and strain influenced electrical characteristics, such as the electron mobility, may be determined in a highly efficient manner. Moreover, the test pads may enable the detection of stress and strain induced modifications with a ... 02/02/06 - 20060022196 - Semiconductor substrate and semiconductor device fabrication method The semiconductor substrate comprises a first monitor part 14a formed in a first region near a center of a semiconductor wafer 10, which includes a first element having a first electrode 24 formed over the semiconductor wafer 10 with a first insulation film 22 formed therebetween, and a first electrode ... 02/02/06 - 20060022195 - Scribe line structure The present invention provides a scribe line structure, which includes a substrate, a plurality of dielectric layers of low dielectric constant materials formed on the substrate, at least a process monitor pattern made of materials of metal formed between the dielectric layers, and a dummy metal structure connected to the ... 01/26/06 - 20060017051 - Apparatus having photoelectric converting element, and device manufacturing method Disclosed is an apparatus that includes an output unit having a photoelectric converting element, for producing a signal corresponding to light incident on the photoelectric converting element, a restricting unit for restricting a light receiving region of the photoelectric converting element to one of a first region and a second ... 01/19/06 - 20060011911 - Detection of molecular probes fixed to an active zone of a sensor The present invention relates to a method for detecting at least one parameter representative of molecular probes fixed to zones of a sensor. ... 01/12/06 - 20060006384 - Special contact points for accessing internal circuitry of an intergrated circuit One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads ... 01/12/06 - 20060006383 - Single and double-gate pseudo-fet devices for semiconductor materials evaluation Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior ... 01/05/06 - 20060001022 - Methods for making nearly planar dielectric films in integrated circuits In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric layers—the insulative layers sandwiched between layers of metal wiring—in integrated circuits. Accordingly, the inventor devised several methods ... 12/29/05 - 20050285106 - Method of reworking structures incorporating low-k dielectric materials Methods of etching a semiconductor structure using ion milling with a variable-position endpoint detector to unlayer multiple interconnect layers, including low-k dielectric films. The ion milling process is controlled for each material type to maintain a planar surface with minimal damage to the exposed materials. In so doing, an ion ... 12/29/05 - 20050285105 - Pressure inspector and method for inspecting liquid crystal display panels A pressure inspector (1) for inspecting at least one liquid crystal display panel includes a roller (11), and a holder (12) holding the roller such that the roller is rotatable in the holder and can roll along the liquid crystal display panel. When the pressure inspector works, the rollers are ... 12/29/05 - 20050285104 - Apparatus and method of removing particles An impurities elimination apparatus including a base plate, a first nozzle for removing impurities on the base plate using air suction, a glass substrate disposed on the base plate, and a second nozzle for coating the glass substrate with an organic material. ... 12/08/05 - 20050269567 - Test key for monitoring gate conductor to deep trench misalignment A test key for monitoring GC-DT misalignment is provided. Deep trench capacitors are embedded in an interlacing matrix manner. GC lines are defined on a substrate and passing over the deep trench capacitors. A first bit line contact pattern surrounded by first assistant bit line contact patterns is disposed on ... 12/01/05 - 20050263760 - Semiconductor structure comprising a stress sensitive element and method of measuring a stress in a semiconductor structure A semiconductor structure comprises a stress sensitive element. A property of the stress sensitive element is representative of a stress in the semiconductor structure. Additionally, the semiconductor structure may comprise an electrical element. The stress sensitive element and the electrical element comprise portions of a common layer structure. Analyzers may ... 12/01/05 - 20050263759 - Semiconductor devices and method for manufacturing the same, semiconductor device modules, circuit substrates and electronic apparatuses A method for manufacturing a semiconductor device includes, (a) mounting a plurality of first semiconductor chips in a manner not to overlap with one another on a substrate having a plurality of wiring patterns formed thereon, and electrically connecting each of the first semiconductor chips to any one of the ... 11/24/05 - 20050258420 - Semiconductor device having a gap between a gate electrode and a dummy gate electrode A method of deforming a pattern comprising the steps of forming, over a substrate, a layered-structure with an upper surface including at least one selected region and at least a re-flow stopper groove, wherein the re-flow stopper groove extends outside the selected region and separate from the selected region; selectively ... 11/17/05 - 20050253140 - Method of bumping die pads for wafer testing A method of processing a semiconductor wafer including a plurality of semiconductor dies is provided. The method includes providing a semiconductor wafer including a plurality of semiconductor dies, at least a portion of the semiconductor dies including contact pads for testing the respective semiconductor die. The method also includes positioning ... 11/10/05 - 20050247931 - Selectable decoupling capacitors for integrated circuits and associated methods Selectable capacitors are used to modify performance characteristics of functional circuit elements of an integrated circuit (IC). In an embodiment, the decoupling capacitors are implemented as additional or alternative mounting pads on a surface of the IC. At least one selectable capacitor is provided for each IC circuit element, such ... 11/10/05 - 20050247930 - Shallow trench isolation void detecting method and structure for the same Disclosed is a. method for detecting STI void of a semiconductor wafer. The method of the present invention comprises steps of assigning a detecting area in a predetermined region of the wafer; forming active areas and gate strips crossing the active areas by the process synchronized with that for other ... 10/27/05 - 20050236617 - Semiconductor device One of aspects of the present invention is to provide a semiconductor device, which includes an insulating substrate, and a semiconductor chip mounted on the insulating substrate. The semiconductor chip has a chip electrode thereon. The semiconductor device also includes a first terminal electrically connected with the chip electrode through ... 10/27/05 - 20050236616 - Reliable semiconductor structure and method for fabricating A reliable semiconductor structure and its fabrication method. Active regions and/or scribe lines on a semiconductor substrate are configured along a crack resistant crystalline direction. Thermal cracking due to the abrupt temperature ramp of rapid thermal processing can be avoided. ... 10/13/05 - 20050224792 - Novel test structure for speeding a stress-induced voiding test and method of using same A test structure, having: a first member having: a roughly a rectangular shape; a first width dimension; and a first length dimension that is greater than the first width dimension; and a second member having: a roughly a rectangular shape; a second width dimension; and a second length dimension that ... 10/13/05 - 20050224791 - Semiconductor package security features using thermochromatic inks and three-dimensional identification coding Numerous embodiments of an apparatus and method for generating an identification feature are described. In one embodiment of the present invention, portions of an identification character printed with thermochromatic ink are distributed within a three-dimensional matrix of a multi-layer patch. The multi-layer patch may be disposed above a substrate. ... 10/06/05 - 20050218401 - Device for detecting an attack against an integrated circuit chip A circuit for detecting attacks by contacting an integrated circuit chip comprising means for applying a random signal to a first terminal of at least one conductive path formed in at least one first metallization level of the chip, means for comparing the applied signal with a signal present on ... 09/29/05 - 20050211980 - Device and method for detecting stress migration properties A device and method are provided for detecting stress migration properties of a semiconductor module mounted in a housing. A stress migration test (SMT) structure is formed in the semiconductor module. An integrated heating (IH) device is formed within or in direct proximity to the SMT structure. The SMT structure ... 09/29/05 - 20050211979 - Ic package, inspection method of ic package mounting body, repairing method of ic package mounting body, and inspection pin for ic package mounting body Disclosed is an IC package including an interpose substrate and lands for external connection disposed on a face of the interpose substrate in a grid pattern, the interpose substrate having a penetration hole on at least a position between the lands for external connection disposed in a grid pattern. Besides, ... 09/22/05 - 20050205865 - Ic testing apparatus and methods Methods, devices, and systems of the invention provide improved semiconductor device testing with firm tester-to-device interface and increased contact area. A test probe (24, 58) associated with ATE (18) is configured to substantially correspond to a probe receptacle (38) of a test board (16) or semiconductor device (10). Upon insertion ... 09/15/05 - 20050199875 - Inspection pattern, inspection method, and inspection system for detection of latent defect of multi-layer wiring structure An inspection pattern, an inspection method, and an inspection system for detection of a latent defect of a multi-layer wiring structure formed on the semiconductor wafer. The inspection pattern includes lower-layer wiring portions, upper-layer wiring portions, an insulating layer provided between them, contact units connecting them to form a contact ... 09/08/05 - 20050194591 - Semiconductor devices and manufacturing method therefor A non-contact identification semiconductor device is provided with a semiconductor chip including a receiving circuit that receives an inquiry to the non-contact identification semiconductor device, a memory that stores identification information of multiple bits and a sending circuit that sends the identification information. An antenna coupled to said semiconductor chip ... 09/08/05 - 20050194590 - System and method for controlling manufacturing apparatuses A control system for a manufacturing apparatus includes manufacturing information input unit acquiring time series data of apparatus parameters controlling manufacturing apparatuses; failure pattern classification module classifying in-plane distributions of failures of each of the wafers into failure patterns; an index calculation unit configured to statistically process the time series ... 09/01/05 - 20050189540 - Module inspection fixture An apparatus for inspecting semiconductor module packages which includes a cylindrical base section, a truncated spherical section superimposed on the cylindrical base capable of being rotated and tilted on the cylindrical base section, and a tray section superimposed on the truncated section. ... 08/25/05 - 20050184289 - Device and method for detecting alignment of active areas and memory cell structures in dram devices A test device and method for detecting alignment of active areas and memory cell structures in DRAM devices with vertical transistors. In the test device, parallel first and second memory cell structures disposed in the scribe line region, each has a deep trench capacitor and a transistor structure. An active ... 08/18/05 - 20050179035 - Apparatus and method to access a plurality of pn-junctions with a limited number of pins In one embodiment, a plurality of pn-junctions are grouped into n(n-1)/2 pairs (where n is an integer greater than 1) and each pn-junction pair includes a first pn-junction coupled antiparallel to a second pn-junction. In addition, n access points are coupled to the plurality of pn-junctions, and through the n ... 08/11/05 - 20050173702 - Chip mis-position detection method The invention includes first detection means (9A) disposed on the side of a stage (2), for detecting float or peel of semiconductor chips (10) inside a horizontal or longitudinal row unit regularly arranged in an X or Y axis direction, and second detection means (9B) disposed above the stage (2), ... 08/04/05 - 20050167661 - Lithography evaluating method, semiconductor device manufacturing method and program medium A lithography evaluating method comprises preparing a substrate, the substrate including a semiconductor substrate and a wiring structure including at least one wiring layer formed on the semiconductor substrate, partitioning the substrate into a plurality of regions to be evaluated, and obtaining a value of property relating to the wiring ... 07/28/05 - 20050161669 - Integrated system with modular microfluidic components Modular fluidic microchips, systems integrating such microchips, and associated preparative and analytical methods are presented. ... 07/21/05 - 20050156166 - Jig device for transporting and testing integrated circuit chip A novel jig device useful for transporting and testing an IC chip is disclosed. The jig device comprises a main jig body, having a holding part onto which the IC chip to be tested is attracted and held and at least one suction path is formed, and at least one ... 07/21/05 - 20050156165 - Test assembly including a test die for testing a semiconductor product die One embodiment of the present invention concerns a test assembly for testing product circuitry of a product die. In one embodiment, the test assembly includes at test die and an interconnection substrate for electrically coupling the test die to a host controller that communicates with the test die. The test ... 07/07/05 - 20050145842 - Socket for testing a semiconductor device and a connecting sheet used for the same Probes 1 for testing and outer connecting terminals 14a are electrically connected to a-test socket for semiconductor devices. In use of a connecting sheet, fabricated by an elastically deformative insulating member and electrodes 202, flexibility is given, and good electrical contacts are obtainable. Further, because the connecting sheet 2 is ... 07/07/05 - 20050145841 - Method to selectively identify reliability risk die based on characteristics of local regions on the wafer A method and system for selectively identifying reliability risk die based on characteristics of local regions on a wafer by computing particle sensitive yield and using the particle sensitive yield to identify reliability risk die. Specifically, a bin characteristics database which identifies hard and soft bins that are sensitive to ... 06/30/05 - 20050139827 - Test patterns for measurement of effective vacancy diffusion area A test pattern (100, 200, 300, 400, 600, 700) has a first metal structure (102) disposed on a substrate (352), one or more intermediate layers (358) disposed above the first metal structure (102) and a second metal structure (104) disposed above the one or more intermediate layers (352). A first ... 06/30/05 - 20050139826 - Structure of test element group wiring and semiconductor substrate A structure of test element group wiring includes, in addition to an electrode on a substrate including one or more layers of insulating films, and real wirings electrically connected to the electrode, includes dummy wirings electrically isolated from the electrode and having a portion of the same shape as the ... 06/23/05 - 20050133786 - Semiconductor testing device and semiconductor testing method A semiconductor testing device of the invention has a measuring substrate that is provided with holes therethrough for exposing a pad of each of the dies of a semiconductor wafer mounted on the measuring substrate, the semiconductor wafer being supported by a wafer holder on one side of the measuring ... 06/23/05 - 20050133785 - Device and method for detecting the overheating of a semiconductor device The invention relates to a method and a device (1, 11, 21) for detecting the overheating of a semiconductor device, comprising a temperature measuring means (3, 13, 23) that changes its electrical conductivity when the temperature of the semiconductor device changes. ... 06/16/05 - 20050127356 - Test mask structure Disclosed is a test mask structure. The test mask structure of the present invention comprises at least an array pattern region, in a certain proportion to the final product, having a first pattern density according to the certain proportion; and at least one test mask pattern region having a second ... 06/02/05 - 20050116224 - Circuit board having test coupon and method for evaluating the circuit board A circuit board includes: a substrate; a conductive pattern disposed on a surface of the substrate; a lower insulation layer disposed on the conductive pattern to cover the conductive pattern except for an opening, through which the conductive pattern is partially exposed from the lower insulation layer; a conductor disposed ... 06/02/05 - 20050116223 - Burn-in substrate and burn-in device Input and output of small-current signals between a mother board and semiconductor devices subjected to a burn-in test are made via a device driving unit. Large-current main power is supplied via the device driving unit through bus bars without passing through the mother board. In this way, the risk of ... 06/02/05 - 20050116222 - Memory device and method for burn-in test A memory device and a method for burn-in test are described. The memory device has a plurality of sub-array word line leak-current limited units and a plurality of single word line leak-current limited units. They are used to limit the current in each word line to a predetermined word line ... ### FreshPatents.com Support |