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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Thin Active Physical Layer Which Is (1) An Active Potential Well Layer Thin Enough To Establish Discrete Quantum Energy Levels Or (2) An Active Barrier Layer Thin Enough To Permit Quantum Mechanical Tunneling Or (3) An Active Layer Thin Enough To Permit Carrier Transmission With Substantially No Scattering (e.g., Superlattice Quantum Well, Or Ballistic Transport Device) > Heterojunction > Quantum Well > Superlattice > Field Effect Device Field Effect DeviceField Effect Device patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.01/24/08 - 20080017844 - Low-temperature-grown (ltg) insulated-gate phemt device and method A pseudomorphic-high-electron-mobility-transistor (PHEMT) includes a substrate, a low-temperature-grown (LTG) GaAs gate-insulator layer disposed on the substrate, and a gate electrode disposed on the gate-insulator layer. ... 01/17/08 - 20080012004 - Spintronic devices with constrained spintronic dopant A spintronic device may include at least one superlattice and at least one electrical contact coupled thereto, with the at least one superlattice including a plurality of groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a ... 03/01/07 - 20070045611 - Mosfet with laterally graded channel region and method for manufacturing same The present invention relates generally to a semiconductor device having a channel region comprising a semiconductor alloy of a first semiconductor material and a second, different material, and wherein atomic distribution of the second material in the channel region is graded along a direction that is substantially parallel to a ... 11/23/06 - 20060261326 - Semiconductor device with different lattice properties To reduce a current loss through a channel and improve electron mobility, a first semiconductor layer and a second semiconductor layer (sequentially formed on a semiconductor substrate) have different lattice properties. The first semiconductor layer and the second semiconductor layer may be etched to form a first semiconductor pattern. A ... 08/03/06 - 20060169972 - Vertical carbon nanotube transistor integration A hybrid semiconductor structure which includes a horizontal semiconductor device and a vertical carbon nanotube transistor, where the vertical carbon nanotube transistor and the horizontal semiconductor device have at least one shared node is provided. The at least one shared node can include, for example, a drain, source or gate ... 04/06/06 - 20060071205 - Nanocrystal switch A switch comprises a set of electrodes with a nanocrystal channel disposed between the electrodes. The nanocrystal channel has bridges between conductive nanocrystals. A gate electrode is disposed above the nanocrystal channel and is insulated there from. Voltage applied to the gate can modulate electrical conductivity of the bridges between ... 03/30/06 - 20060065887 - Carbon nanotube-based electronic devices made by electrolytic deposition and applications thereof Carbon nanotube-based devices made by electrolytic deposition and applications thereof are provided. In a preferred embodiment, the present invention provides a device comprising at least one array of active carbon nanotube junctions deposited on at least one microelectronic substrate. In another preferred embodiment, the present invention provides a device comprising ... 01/05/06 - 20060001018 - Iii-v and ii-vi compounds as template materials for growing germanium containing film on silicon An assembly comprising a semiconductor substrate having a first lattice constant, an intermediate layer having a second lattice constant formed on the semiconductor substrate, and a virtual substrate layer having a third lattice constant formed on the intermediate layer. The intermediate layer comprises one of a combination of III-V elements ... 12/29/05 - 20050285098 - Ultra-linear multi-channel field effect transistor Alternate layers of wide band gap and narrow band gaps of different kinds of semiconductors are used to form multiple channels of a FET. The channels are doped or formed as 2-DEG/2-DHG in narrow band semiconductor by charge supply layer in the wide band gap semiconductor. The different kinds of ... 09/15/05 - 20050199873 - Semiconductor device with heterojunction An aspect of the present invention provides a semiconductor device that includes a semiconductor base made of a first semiconductor material of a first conductivity type, a hetero-semiconductor region forming a heterojunction with the semiconductor base and made of a second semiconductor material having a different band gap from the ... 08/18/05 - 20050179030 - Field effect transistor device with channel fin structure and method of fabricating the same A finFET device includes a semiconductor substrate having specific regions surrounded with a trench. The trench is filled with an insulating layer, and recess holes are formed within the specific regions such that channel fins are formed by raised portions of the semiconductor substrate on both sides of the recess ... 08/18/05 - 20050179029 - Methods of fabricating vertical carbon nanotube field effect transistors for arrangement in arrays and field effect transistors and arrays formed thereby A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. ... 08/04/05 - 20050167655 - Vertical nanotube semiconductor device structures and methods of forming the same Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming ... 07/21/05 - 20050156158 - Charge trapping device and method of forming the same A charge trapping device, and a method of forming the same is disclosed. Charge traps are optimally distributed through a trapping region based on controlling various conventional processing operations, such as an implant, an anneal, an insulator film deposition, and the like. In some embodiments, FETs can be configured to ... 07/21/05 - 20050156157 - Hierarchical assembly of interconnects for molecular electronics A hierarchical assembly methodology can interconnect individual two- and/or three-terminal molecules with other nanoelements (nanoparticles, nanowires, etc.) to form solution-based suspensions of nanoscale assemblies. The nanoassemblies can then undergo chemical-selective alignment and attachment to nanopatterned silicon and/or other surfaces for interconnection and/or measurement. ... 07/07/05 - 20050145838 - Vertical carbon nanotube field effect transistor A field effect transistor employs a vertically oriented carbon nanotube as the transistor body, the nanotube being formed by deposition within a vertical aperture, with an optional combination of several nanotubes in parallel to produced quantized current drive and an optional change in the chemical composition of the carbon material ... ### FreshPatents.com Support |