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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Thin Active Physical Layer Which Is (1) An Active Potential Well Layer Thin Enough To Establish Discrete Quantum Energy Levels Or (2) An Active Barrier Layer Thin Enough To Permit Quantum Mechanical Tunneling Or (3) An Active Layer Thin Enough To Permit Carrier Transmission With Substantially No Scattering (e.g., Superlattice Quantum Well, Or Ballistic Transport Device) > Heterojunction > Quantum Well > Superlattice > Strained Layer Superlattice > Si X Ge 1-x Si X Ge 1-xSi X Ge 1-x patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.12/27/07 - 20070295953 - Germanium phototransistor with floating body A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in ... 11/15/07 - 20070262296 - Photodetectors employing germanium layers A germanium-based photodetector comprises a p- (or n-type) germanium layer, an intrinsic single crystal germanium layer formed on the p- (or n-) type germanium layer, and an n- (or p-type) germanium layer formed on the intrinsic single crystal germanium layer. An electrically conductive contact extends vertically from an upper surface ... 11/15/07 - 20070262295 - A method for manipulation of oxygen within semiconductor materials Methods and electronic devices fabricated by those methods are disclosed where the method allows controlled movement of oxygen during fabrication of electronic and photonic devices, facilitated by a technique of oxygen updiffusion (OUD). The method includes fabrication of a compound semiconductor film, doped with either carbon or boron, over a ... 11/08/07 - 20070257249 - Silicon/silcion germaninum/silicon body device with embedded carbon dopant A semiconductor structure and method of manufacturing a semiconductor device, and more particularly, an NFET device. The devices includes a stress receiving layer provided over a stress inducing layer with a material at an interface there between which reduces the occurrence and propagation of misfit dislocations in the structure. The ... 10/18/07 - 20070241323 - Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates Edge-angle-optimized solid phase epitaxy is described as a method for forming hybrid orientation substrates comprising changed-orientation Si device regions free of the trench-edge defects typically seen when trench-isolated regions of Si are recrystallized to the orientation of an underlying single-crystal Si template after an amorphization step. For the case of ... 09/20/07 - 20070215859 - Strained silicon with elastic edge relaxation A thin blanket epitaxial layer of SiGe is grown on a silicon substrate to have a biaxial compressive stress in the growth plane. A thin epitaxial layer of silicon is deposited on the SiGe layer, with the SiGe layer having a thickness less than its critical thicknesses. Shallow trenches are ... 08/16/07 - 20070187669 - Field effect transistor and a method for manufacturing the same A field effect transistor fabricated in a device isolation region includes a Si1-xGex layer (0<x≦1) that a lattice strain is relaxed, a strained Si layer formed on the Si1-xGex, a gate electrode insulatively disposed over a part of the strained Si layer, source and drain regions formed in the strained ... 03/29/07 - 20070069195 - Silicon germanium semiconductive alloy and method of fabricating same A silicon germanium (SiGe) semiconductive alloy is grown on a substrate of single crystalline Al2O3. A {111} crystal plane of a cubic diamond structure SiGe is grown on the substrate's {0001} C-plane such that a <110> orientation of the cubic diamond structure SiGe is aligned with a <1,0,−1,0> orientation of ... 03/01/07 - 20070045610 - Transistor device with strained germanium (ge) layer by selectively growth and fabricating method thereof A transistor device with strained Ge layer by selectively growth and a fabricating method thereof are provided. A strained Ge layer is selectively grown on a substrate, so that the material of source/drain region is still the same as that of the substrate, and the strained Ge layer serves as ... 02/01/07 - 20070023745 - Strained channel transistor and method of fabricating the same A strained channel transistor according to the present invention includes a semiconductor substrate, a semiconductor layer having a lattice constant larger than the lattice constant of the semiconductor substrate on the semiconductor substrate, a strained channel layer on the semiconductor layer, and one or more epitaxial layers on sides of ... 01/18/07 - 20070012913 - Semiconductor device and production method thereof A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to ... 01/11/07 - 20070007509 - Strained semiconductor structures A method for in situ formation of low defect, strained silicon and a device formed according to the method are disclosed. In one embodiment, a silicon germanium layer is formed on a substrate, and a portion of the silicon germanium layer is removed to expose a surface that is smoothed ... 01/04/07 - 20070001165 - Memory cell comprising one mos transistor with an isolated body having a prolonged memory effect A memory cell with one MOS transistor formed in a floating body region in which the lower surface of the source and drain regions, outside of the source extension and drain extension regions, rests on an insulating layer. ... 01/04/07 - 20070001164 - Cmos image sensor and method for fabricating the same A CMOS image sensor includes a substrate including silicon, a silicon germanium (SiGe) epitaxial layer formed over the substrate, the SiGe epitaxial layer formed through epitaxial growth and doped with a predetermined concentration level of impurities, an undoped silicon epitaxial layer formed over the SiGe epitaxial layer by epitaxial growth, ... 01/04/07 - 20070001163 - Floating body germanium phototransistor A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in ... 01/04/07 - 20070001162 - Single transistor memory cell with reduced programming voltages A transistor fabrication method includes forming an electrode overlying a channel of a semiconductor on insulator (SOI) substrate. Source/drain structures are formed in the substrate on either side of the channel. The source/drain structures include a layer of a second semiconductor over a first semiconductor. The first and second semiconductors ... 12/28/06 - 20060289856 - Semiconductor device and production method thereof A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to ... 12/28/06 - 20060289855 - Quantum dot based optoelectronic device and method of making same A method of forming an optically active region on a silicon substrate includes the steps of epitaxially growing a silicon buffer layer on the silicon substrate and epitaxially growing a SiGe cladding layer having a plurality of arrays of quantum dots disposed therein, the quantum dots being formed from a ... 12/21/06 - 20060284164 - Strained germanium field effect transistor and method of making the same A strained germanium field effect transistor (FET) and method of making the same, comprise forming a germanium layer on a substrate, then forming a Si protective layer on the germanium layer, next forming a gate insulation layer on the Si protective layer, and fmally positioning a gate on the gate ... 11/30/06 - 20060266997 - Methods for forming semiconductor structures with differential surface layer thicknesses A semiconductor structure having a substrate with a surface layer including strained silicon. The surface layer has a first region with a first thickness less than a second thickness of a second region. A gate dielectric layer is disposed over a portion of at least the first surface layer region. ... 11/30/06 - 20060266996 - Semiconductor device and method of manufacturing the same A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor on a semiconductor layer formed on an insulating layer, in which the channel of the n-channel MIS transistor is formed of a strained Si layer having biaxial tensile strain and the channel of the p-channel MIS transistor ... 11/16/06 - 20060255331 - Strained silicon forming method with reduction of threading dislocation density A method for growing strained Si layer and relaxed SiGe layer with multiple Ge quantum dots (QDs) on a substrate is disclosed. The method can reduce threading dislocation density, decrease surface roughness of the strained silicon and further shorten growth time for forming epitaxy layers than conventional method. The method ... 10/19/06 - 20060231826 - Step-embedded sige structure for pfet mobility enhancement A device, and method for manufacturing the same, including a PFET having an embedded SiGe layer where a shallow portion of the SiGe layer is closer to the PFET channel and a deep portion of the SiGe layer is further from the PFET channel. Thus, the SiGe layer has a ... 09/21/06 - 20060208250 - Semiconductor device based on si-ge with high stress liner for enhanced channel carrier mobility The carrier mobility in transistor channel regions of Si—Ge devices is increased by employing a stressed liner. Embodiments include applying a high compressive or tensile stressed film overlying relaxed source/drain regions. Other embodiments include applying a high compressively or high tensilely stressed film, after post silicide spacer removal, over gate ... 08/10/06 - 20060175601 - Nanoscale wires and related devices The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, ... 07/27/06 - 20060163558 - Mos transistor with elevated source/drain structure In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction ... 07/27/06 - 20060163557 - Semiconductor device and fabrication process thereof A p-channel MOS transistor includes a strained SOI substrate formed of a SiGe mixed crystal layer and a strained Si layer formed on the SiGe mixed crystal layer via an insulation film, a channel region being formed in the strained Si layer, a gate electrode formed on the strained Si ... 07/20/06 - 20060157688 - Methods of forming semiconductor constructions and integrated circuits The invention includes a TFT-based logic circuit construction. Such construction includes a pair of first transistor devices, and a pair of second transistor devices over the first transistor devices. The first transistor devices have first active regions extending into a first semiconductive material, and the second transistor devices have second ... 07/20/06 - 20060157687 - Non-planar mos structure with a strained channel region An embodiment is a non-planar MOS transistor structure including a strained channel region. The combination of a non-planar MOS transistor structure, and in particular an NMOS tri-gate transistor, with the benefits of a strained channel yields improved transistor drive current, switching speed, and decreased leakage current for a given gate ... 07/13/06 - 20060151776 - Semiconductor integrated circuit and fabrication process thereof A semiconductor integrated circuit device includes an n-channel MOS transistor formed on a first device region of a silicon substrate and a p-channel MOS transistor formed on a second device region of the silicon substrate, wherein the n-channel MOS transistor includes a first gate electrode carrying a pair of first ... 06/29/06 - 20060138398 - Semiconductor device and fabrication method thereof A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and ... 06/22/06 - 20060131559 - Method of manufacturing a semiconductor device with a silicon-germanium gate electrode A SiO2 film serving as a gate dielectric film is formed on a silicon substrate. A seed Si film is formed on the gate dielectric film. A thin SiGe film of a thickness of 50 nm or less is formed on the seed Si film at a temperature between 450° ... 06/15/06 - 20060124919 - Ge-si quantum well structures Si—Ge quantum wells where the well material has a lowest conduction band energy minimum at k=0 (the Γ point of the first Brillouin zone) are provided. Quantum well structures that satisfy this condition have “Kane-like” bands at and near k=0 which can provide physical effects useful for various device applications, ... 06/08/06 - 20060118776 - Field effect transistor A field effect transistor comprises a source and a drain, and a channel layer of Si1-x-yGexCy crystal (1>x>0, 1>y≧0). Ge composition increases toward a drain end, in a vicinity of a source end of the channel layer. ... 05/18/06 - 20060102888 - Semiconductor substrate and method of fabricating the same A semiconductor substrate and a method of fabricating the same are provided. The semiconductor substrate includes: a Si substrate; a SiO2 layer having a predetermined width formed on the Si substrate; a SiGe layer having a first end portion and a second end portion at both sides and formed on ... 05/11/06 - 20060097243 - Semiconductor array and method for manufacturing a semiconductor array A method for manufacturing a semiconductor array, particularly a high-frequency bipolar transistor, is provided, the method includes process steps, so that a dielectric is produced on a monocrystalline, first semiconductor region of a first conductivity type, a silicide layer is deposited and patterned in such a way that the silicide ... 05/04/06 - 20060091377 - Hetero-integrated strained silicon n-and p-mosfets The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions ... 04/20/06 - 20060081837 - Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present ... 04/20/06 - 20060081836 - Semiconductor device and method of manufacturing the same In a field effect semiconductor device for high frequency power amplification, it is difficult to achieve size reduction and increased efficiency simultaneously while ensuring voltage withstanding. A further improvement in efficiency is attained by using a strained Si channel for LDMOS at an output stage for high frequency power amplification. ... 03/16/06 - 20060054881 - Sers-active structures including nanowires A SERS-active structure is disclosed that includes a substrate and at least one nanowire disposed on the substrate. The at least one nanowire includes a core including a first material and a coating including a SERS-active material. A SERS system is also disclosed that includes a SERS-active structure. Also disclosed ... 02/16/06 - 20060033095 - Non-planar pmos structure with a strained channel region and an integrated strained cmos flow A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si1-x Gex layer is formed on the silicon-on-isolator (SOI) substrate. The relaxed Si1-x Gex layer is patterned and subsequently etched to form a fin on ... 01/19/06 - 20060011906 - Ion implantation for suppression of defects in annealed sige layers A method for fabricating substantially relaxed SiGe alloy layers with a reduced planar defect density is disclosed. The method of the present invention includes forming a strained Ge-containing layer on a surface of a Si-containing substrate; implanting ions at or below the Ge-containing layer/Si-containing substrate interface and heating to form ... 12/29/05 - 20050285097 - Integration of strained ge into advanced cmos technology A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure ... 12/08/05 - 20050269561 - Strained si on multiple materials for bulk or soi substrates The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate, a first layered stack atop the substrate, the first layered stack comprising a ... 11/10/05 - 20050247926 - Semiconductor device based on si-ge with high stress liner for enhanced channel carrier mobility The carrier mobility in transistor channel regions of Si—Ge devices is increased by employing a stressed liner. Embodiments include applying a high compressive or tensile stressed film overlying relaxed source/drain regions. Other embodiments include applying a high compressively or high tensilely stressed film, after post silicide spacer removal, over gate ... 11/03/05 - 20050242340 - Strained silicon nmos devices with embedded source/drain A planar NFET on a strained silicon layer supported by a SiGe layer achieves reduced external resistance by removing SiGe material outside the transistor body and below the strained silicon layer and replacing the removed material with epitaxial silicon, thereby providing lower resistance for the transistor electrodes and permitting better ... 10/20/05 - 20050230676 - Methods of forming cmos integrated circuit devices and substrates having buried silicon germanium layers therein and devices so formed CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained ... 10/20/05 - 20050230675 - Field-effect transistor, semiconductor device, and photo relay According to the present invention, there is provided a field-effect transistor comprising: a silicon layer formed on an insulating film; a first-conductivity-type base layer formed in said silicon layer; a second-conductivity-type source layer formed in said silicon layer so as to be adjacent to said first-conductivity-type base layer; a second-conductivity-type ... 10/13/05 - 20050224786 - Microelectronic device with depth adjustable sill and method of fabrication thereof A microelectronic device includes a substrate, and a patterned feature located over the substrate and a plurality of doped regions, wherein the patterned feature includes at least one electrode. The microelectronic device includes at least one sill region for the enhancement of electron and/or hole mobility. ... 10/06/05 - 20050218399 - Method of fabrication sige heterojunction bipolar transistor The present invention provides for a method of fabricating a semiconductor device comprising a non-selectively grown SiGe(C) heterojunction bipolar transistor including the steps of forming an insulating layer (12, 40) on a substrate and providing a layer structure including a conductive layer (14, 42) on the insulating layer (12, 40), ... 09/22/05 - 20050205859 - Shallow trench isolation process A structure including a transistor and a trench structure, with the trench structure inducing only a portion of the strain in a channel region of the transistor. ... 09/22/05 - 20050205858 - Transistor with shallow germanium implantation region in channel A method of manufacturing a transistor and a structure thereof, wherein a very shallow region having a high dopant concentration of germanium is implanted into a channel region of a transistor at a low energy level, forming an amorphous germanium implantation region in a top surface of the workpiece, and ... 09/15/05 - 20050199872 - Silicon-germanium thin layer semiconductor structure with variable silicon-germanium composition and method of fabrication A SiGe thin layer semiconductor structure containing a substrate having a dielectric layer, a variable composition SixGe1-x layer on dielectric layer, and a Si cap layer on the variable composition SixGe1-x layer. The variable composition SixGe1-x layer can contain a SixGe1-x layer with a graded Ge content or a plurality ... 09/08/05 - 20050194585 - Field effect transistor and a method for manufacturing the same A field effect transistor fabricated in a device isolation region includes a Si1-xGex layer (0<x≦1) that a lattice strain is relaxed, a strained Si layer formed on the Si1-xGex, a gate electrode insulatively disposed over a part of the strained Si layer, source and drain regions formed in the strained ... 08/18/05 - 20050179028 - Construction of thin strain-relaxed sige layers and method for fabricating the same A construction of thin strain-relaxed SiGe layers and method for fabricating the same is provided. The construction includes a semiconductor substrate, a SiGe buffer layer formed on the semiconductor substrate, a Si(C) layer formed on the SiGe buffer layer, and an relaxed SiGe epitaxial layer formed on the Si(C) layer. ... 08/04/05 - 20050167654 - Ion recoil implantation and enhanced carrier mobility in cmos device An integrated circuit (IC) includes a CMOS device formed above a semiconductor substrate having ions therein that are implanted in the semiconductor substrate by an ion recoil procedure. The IC preferably, but not necessarily, incorporates sub-0.1 micron technology in the CMOS device. The implanted ions may preferably be germanium ions. ... 07/28/05 - 20050161663 - Rare earth-oxides, rare earth -nitrides, rare earth -phosphides and ternary alloys with silicon Atomic layer epitaxy (ALE) is applied to the fabrication of new forms of rare-earth oxides, rare-earth nitrides and rare-earth phosphides. Further, ternary compounds composed of binary (rare-earth oxides, rare-earth nitrides and rare-earth phosphides) mixed with silicon and or germanium to form compound semiconductors of the formula RE-(O, N, P)—(Si,Ge) are ... 07/21/05 - 20050156156 - Method of fabricating a non-floating body device with enhanced performance Provided is a semiconductor transistor device including a substrate having at least two regions, a semiconductive region extending to a first surface of the substrate and an insulative region extending to a second surface of the substrate. The semiconductor transistor device also includes a patterned semiconductor structure overlying both surfaces ... 07/21/05 - 20050156155 - Rare earth-oxides, rare earth-nitrides, rare earth-phosphides and ternary alloys with silicon Atomic layer epitaxy (ALE) is applied to the fabrication of new forms of rare-earth oxides, rare-earth nitrides and rare-earth phosphides. Further, ternary compounds composed of binary (rare-earth oxides, rare-earth nitrides and rare-earth phosphides) mixed with silicon and or germanium to form compound semiconductors of the formula RE-(O, N, P)—(Si,Ge) are ... 07/21/05 - 20050156154 - Protecting silicon germanium sidewall with silicon for strained silicon/silicon germanium mosfets Raised Si/SiGe source and drain regions include epitaxially grown silicon on SiGe sidewalls. The epi silicon prevents adverse effects of Ge during silicidation, including Ge out diffusion and silicide line breakage. The Si also increases the active area. ... 07/07/05 - 20050145837 - Enhancement of electron and hole mobilities in <110> si under biaxial compressive strain The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress ... 06/02/05 - 20050116218 - Non-planar transistor having germanium channel region and method of manufacturing the same Provided is a non-planar transistor with a multi-gate structure that includes a germanium channel region, and a method of manufacturing the same. The non-planar transistor includes a silicon body and a channel region that covers exposed surfaces of the silicon body. The channel region is formed of a germanium layer ... 06/02/05 - 20050116217 - Trench type mosgated device with strained layer on trench sidewall A MOSgated trench device has a reduced on resistance by forming a less than about a 13 nm thick strained SiGe layer on the silicon surface of the trenches and forming a thin (30 nm or less) layer of epitaxially deposited silicon on the SiGe layer which epi layer is ... ### FreshPatents.com Support |