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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Thin Active Physical Layer Which Is (1) An Active Potential Well Layer Thin Enough To Establish Discrete Quantum Energy Levels Or (2) An Active Barrier Layer Thin Enough To Permit Quantum Mechanical Tunneling Or (3) An Active Layer Thin Enough To Permit Carrier Transmission With Substantially No Scattering (e.g., Superlattice Quantum Well, Or Ballistic Transport Device)

Thin Active Physical Layer Which Is (1) An Active Potential Well Layer Thin Enough To Establish Discrete Quantum Energy Levels Or (2) An Active Barrier Layer Thin Enough To Permit Quantum Mechanical Tunneling Or (3) An Active Layer Thin Enough To Permit Carrier Transmission With Substantially No Scattering (e.g., Superlattice Quantum Well, Or Ballistic Transport Device)

Thin Active Physical Layer Which Is (1) An Active Potential Well Layer Thin Enough To Establish Discrete Quantum Energy Levels Or (2) An Active Barrier Layer Thin Enough To Permit Quantum Mechanical Tunneling Or (3) An Active Layer Thin Enough To Permit Carrier Transmission With Substantially No Scattering (e.g., Superlattice Quantum Well, Or Ballistic Transport Device) patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

10/23/14 - 20140312298 - Graphene and nanotube/nanowire transistor with a self-aligned gate structure on transparent substrates and method of making same
Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the...

10/16/14 - 20140306175 - Thin film transistor
A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, a first conductive layer, a second conductive layer, an insulating layer and a gate electrode. The drain electrode is spaced apart from the source electrode. The first conductive layer is sandwiched between the source electrode and...

10/09/14 - 20140299835 - Ram memory point with a transistor
A memory cell formed of a semiconductor nanorod having its ends heavily doped to form source and drain regions and having its central portion comprising, between the source and drain regions, an N-type region surrounded on a majority of its periphery with a quasi-intrinsic P-type region, and wherein the P-type...

10/02/14 - 20140291606 - Solution-assisted carbon nanotube placement with graphene electrodes
A semiconductor device includes a substrate having at least one electrically insulating portion. A first graphene electrode is formed on a surface of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode. A second graphene electrode formed...

10/02/14 - 20140291607 - Insulating sheet having heterogeneous laminated structure, method of manufacturing the same, and transistor including the insulating sheet
An insulating sheet has a heterogeneous laminated structure, and includes a graphene sheet and a hexagonal boron nitride sheet on the graphene sheet, the hexagonal boron nitride sheet having a root mean square (RMS) surface roughness of about 0.5 nm or less in a region having an area of about...

10/02/14 - 20140291608 - Quantum dot optical devices with enhanced gain and sensitivity and methods of making same
Various embodiment include optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit having an array of conductive regions, and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one...

09/25/14 - 20140284547 - Self-formation of high-density arrays of nanostructures
A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are...

09/18/14 - 20140264253 - Leakage reduction structures for nanowire transistors
A nanowire device of the present description may include a highly doped underlayer formed between at least one nanowire transistor and the microelectronic substrate on which the nanowire transistors are formed, wherein the highly doped underlayer may reduce or substantially eliminate leakage and high gate capacitance which can occur at...

09/18/14 - 20140264254 - Semiconductor light emitting device and illumination apparatus including the same
There is provided a light emitting device including a plurality of nanoscale light emitting structures spaced apart from one another on a first conductivity-type semiconductor base layer, the plurality of nanoscale light emitting structures each including a first conductivity-type semiconductor core, an active layer and a second conductivity-type semiconductor layer,...

09/18/14 - 20140264255 - Method for making a sensor device using a graphene layer
A graphene layer is generated on a substrate. A plastic material is deposited on the graphene layer to at least partially cover the graphene layer. The substrate is separated into at least two substrate pieces....

09/11/14 - 20140252305 - Enhanced photo-thermal energy conversion
Semiconducting quantum dots are applied to a fluid. The quantum dots are configured to absorb visible or near infrared light and re-radiate infrared energy that excites a fundamental vibration frequency of the fluid....

09/11/14 - 20140252306 - Monolithic three dimensional integration of semiconductor integrated circuits
A three-dimensional integrated circuit comprising top tier nanowire transistors formed on a bottom tier of CMOS transistors, with inter-tier vias, intra-tier vias, and metal layers to connect together the various CMOS transistors and nanowire transistors. The top tier first begins as lightly doped regions on a first wafer, with an...

09/11/14 - 20140252307 - Single electron transistor and method for fabricating the same
A transistor and a fabrication method thereof. A transistor includes a channel region including linkers, formed on a substrate, and a metallic nanoparticle grown from metal ions bonded to the linkers, a source region disposed at one end of the channel region, a drain region disposed at the other end...

09/04/14 - 20140246647 - Nanostructure light emitting device and method of manufacturing the same
A nanostructure semiconductor light emitting device includes a base layer, an insulating layer, and a plurality of light emitting nanostructures. The base layer includes a first conductivity type semiconductor. The insulating layer is disposed on the base layer and has a plurality of openings through which regions of the base...

08/28/14 - 20140239249 - Rapid biological synthesis process to produce semiconducting chalcogenide nanostructures for transistor or solar cell applications
The process disclosed herein produces macroscopic quantities of semiconducting arsenic sulfide nanofibers within one to three days. The process is biotically influenced by the bacteria Shewanella sp. Strain ANA-3. The fibers are semiconductors with bandgaps between 2.2 and 2.5 eV. Newly measured semiconducting and bandgap properties can lead to applications...

08/14/14 - 20140225058 - Rectifying device, electronic circuit using the same, and method of manufacturing rectifying device
To provide a rectifying device equipped with a carrier transporter excellent in high frequency responsiveness and heat resistance, an electronic circuit using the same, and a method of manufacturing the rectifying device. The rectifying device includes a pair of electrodes, and a carrier transporter arranged between the pair of electrodes...

07/31/14 - 20140209854 - Nanowire capacitor for bidirectional operation
A method of fabricating an electronic device includes the following steps. At least one first set and at least one second set of nanowires and pads are etched in an SOI layer of an SOI wafer. A first gate stack is formed that surrounds at least a portion of each...

07/31/14 - 20140209855 - Nanowire structures having wrap-around contacts
Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of...

07/24/14 - 20140203238 - Wire-last integration method and structure for iii-v nanowire devices
In one aspect, a method of fabricating a nanowire FET device includes the following steps. A layer of III-V semiconductor material is formed on an SOI layer of an SOI wafer. Fins are etched into the III-V material and SOI layer. One or more dummy gates are formed over a...

07/17/14 - 20140197370 - Overlap capacitance nanowire
A device and method for fabricating a nanowire include patterning a first set of structures on a substrate. A dummy structure is formed over portions of the substrate and the first set of structures. Exposed portions of the substrate are etched to provide an unetched raised portion. First spacers are...

07/17/14 - 20140197371 - Overlap capacitance nanowire
A device and method for fabricating a nanowire include patterning a first set of structures on a substrate. A dummy structure is formed over portions of the substrate and the first set of structures. Exposed portions of the substrate are etched to provide an unetched raised portion. First spacers are...

07/10/14 - 20140191185 - Apparatus and method for fabricating nano resonator using laser interference lithography
A method of fabricating a nano resonator, includes forming a line pattern in a first substrate, and transferring the line pattern to a second substrate including a gate electrode. The method further includes forming a source electrode and a drain electrode on the transferred line pattern....

07/10/14 - 20140191186 - Regenerative nanosensor devices
The present invention provides a regenerative nanosensor device for the detection of one or more analytes of interest. In certain embodiments, the device comprises a nanostructure having a reversible functionalized coating comprising a supramolecular assembly. Controllable and selective disruption of the assembly promotes desorption of at least part of the...

07/03/14 - 20140183441 - Apparatus for generating/detecting terahertz wave using graphene and manufacturing method of the same
Provided is a terahertz wave generating/detecting apparatus and a method for manufacturing the same. The terahertz wave generating/detecting apparatus includes; a substrate having an active region and a transmitting region; a lower metal layer extending in a first direction on the active region and the transmitting region of the substrate;...

06/26/14 - 20140175372 - Recessed contact to semiconductor nanowires
A semiconductor nanowire device includes at least one semiconductor nanowire having a bottom surface and a top surface, an insulating material which surrounds the semiconductor nanowire, and an electrode ohmically contacting the top surface of the semiconductor nanowire. A contact of the electrode to the semiconductor material of the semiconductor...

06/26/14 - 20140175373 - Topological insulator structure
A topological insulator structure includes an insulating substrate and a magnetically doped TI quantum well film located on the insulating substrate. A material of the magnetically doped TI quantum well film is represented by a chemical formula of Cry(BixSb1-x)2-yTe3. 0<x<1, 0<y<2. Values of x and y satisfies that an amount...

06/26/14 - 20140175374 - Hybrid cmos nanowire mesh device and finfet device
A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate containing a nanowire mesh device and a second portion of the SOI substrate containing a FINFET device. The nanowire mesh device including stacked and spaced apart semiconductor nanowires located on the substrate, each semiconductor nanowire...

06/26/14 - 20140175375 - Hybrid cmos nanowire mesh device and pdsoi device
A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate contains a nanowire mesh device and a second portion of the SOI substrate contains a partially depleted semiconductor on insulator (PDSOI) device. The nanowire mesh device includes stacked and spaced apart semiconductor nanowires located on...

06/05/14 - 20140151630 - Protection for the epitaxial structure of metal devices
Techniques for fabricating metal devices, such as vertical light-emitting diode (VLED) devices, power devices, laser diodes, and vertical cavity surface emitting laser devices, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of the light-emitting diode and increased...

06/05/14 - 20140151631 - Asymmetric bottom contacted device
The invention provides a Bottom Contacted 2D-layer Device (BCD) for the determination of graphene doping and chemical sensing. The device can be made by transfer of high quality CVD grown graphene films onto n- or p-doped silicon substrates yielding Schottky barrier diodes. Exposure to liquids and gases change the charge...

05/29/14 - 20140145143 - Carbon nanotube transistor voltage converter circuit
A voltage converter circuit includes one or more single-walled carbon nanotube transistors, capable of handling relatively high amounts of current. The transistors are formed using a porous structure which has a number of single-walled carbon nanotubes. The porous structure may be anodized aluminum oxide or another porous material. The circuit...

05/22/14 - 20140138610 - Magnetic domain wall shift register memory device readout
A memory device includes a first nanowire, a second nanowire and a magnetic tunnel junction device coupling the first and second nanowires....

05/22/14 - 20140138611 - In nanowire, device using the same and method of manufacturing in nanowire
There is provided an In nanowire including a substrate, an indium thin film formed on the substrate, an insulating film formed on the indium thin film and having at least one through hole through formation of a pattern, and an In nanowire vertically protruded from the indium thin film through...

05/22/14 - 20140138612 - Fullerene-doped nanostructures and methods therefor
Nanostructures are doped to set conductivity characteristics. In accordance with various example embodiments, nanostructures such as carbon nanotubes are doped with a halogenated fullerene type of dopant material. In some implementations, the dopant material is deposited from solution or by vapor deposition, and used to dope the nanotubes to increase...

03/27/14 - 20140084238 - Nano-patterned substrate and epitaxial structure cross-reference to related application
A nano-patterned substrate includes a substrate and a plurality of nano-structures. The substrate has an upper surface and each of the plurality of nano-structures comprises a semiconductor buffer region and a buffer region formed on the upper surface of the substrate, wherein one of the pluralities of nano-structures has a...

03/06/14 - 20140061582 - Suspended nanowire structure
A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the...

03/06/14 - 20140061583 - Silicon nanotube mosfet
A nanotubular MOSFET device extends a scaling roadmap while maintaining good short channel effects and providing competitive drive current. The nanotubular MOSFET device includes a concentric tubular inner and outer gate separated from each other by a tubular shaped epitaxially grown silicon layer, and a source and drain respectively separated...

02/27/14 - 20140054540 - Device including semiconductor nanocrystals & method
A method of making a device comprising semiconductor nanocrystals comprises forming a first layer capable of transporting charge over a first electrode, wherein forming the first layer comprises disposing a metal layer over the first electrode and oxidizing at least the surface of the metal layer opposite the first electrode...

02/20/14 - 20140048764 - Sub-10 nm graphene nanoribbon lattices
A graphene lattice comprising an ordered array of graphene nanoribbons is provided in which each graphene nanoribbon in the ordered array has a width that is less than 10 nm. The graphene lattice including the ordered array of graphene nanoribbons is formed by utilizing a layer of porous anodized alumina...

02/13/14 - 20140042385 - Contacts-first self-aligned carbon nanotube transistor with gate-all-around
A method of fabricating a semiconducting device is disclosed. A carbon nanotube is deposited on a substrate of the semiconducting device. A first contact on the substrate over the carbon nanotube. A second contact on the substrate over the carbon nanotube, wherein the second contact is separated from the first...

02/13/14 - 20140042386 - Nanowire structures having non-discrete source and drain regions
Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires....

02/06/14 - 20140034899 - Graphene semiconductor and electrical device including the same
A graphene semiconductor including graphene and a metal atomic layer disposed on the graphene, wherein the metal atomic layer includes a metal, which is capable of charge transfer with the graphene....

01/30/14 - 20140027708 - Photonic integrated circuits based on quantum cascade structures
Photonic integrated circuits (PICs) are based on quantum cascade (QC) structures. In embodiment methods and corresponding devices, a QC layer in a wave confinement region of an integrated multi-layer semiconductor structure capable of producing optical gain is depleted of free charge carriers to create a low-loss optical wave confinement region...

01/09/14 - 20140008604 - Super-long semiconductor nano-wire structure and method of making
The present invention disclosure provides a super-long semiconductor nanowire structure. The super-long semiconductor nanowire structure is intermittently widened to prevent fractures in the super-long semiconductor nanowire structure. At the same time, the present invention further provides a method of making a super-long semiconductor nanowire structure. The method forms an intermittently...

01/09/14 - 20140008605 - Method for dispersing quantum dots or quantum wires in zeolite, method for stabilizing quantum dots or quantum wires in zeolite, and zeolite containing quantum dots or quantum wires dispersed by the method
The present application relates to a method for dispersing quantum dots (QDs) or quantum wires in zeolite, to zeolite containing quantum dots or quantum wires dispersed by the method, and to a method for stabilizing quantum dots or quantum wires in zeolite....

01/09/14 - 20140008606 - Cylindrical-shaped nanotube field effect transistor
A cylindrical-shaped nanotube FET may be manufactured on silicon (Si) substrates as a ring etched into a gate stack and filled with semiconductor material. An inner gate electrode couples to a region of the gate stack inside the inner circumference of the ring. An outer gate electrode couples to a...

01/02/14 - 20140001432 - Applications for nanopillar structures
A disclosed method of fabricating a hybrid nanopillar device includes forming a mask on a substrate and a layer of nanoclusters on the hard mask. The hard mask is then etched to transfer a pattern formed by the first layer of nanoclusters into a first region of the hard mask....

01/02/14 - 20140001433 - Methods for passivating a carbonic nanolayer
Methods for passivating a carbonic nanolayer (that is, material layers comprised of low dimensional carbon structures with delocalized electrons such as carbon nanotubes and nanoscopic graphene flecks) to prevent or otherwise limit the encroachment of another material layer are disclosed. In some embodiments, a sacrificial material is implanted within a...

12/05/13 - 20130320293 - Semiconductor light emitting device package and method of manufacturing the same
A semiconductor light emitting device package includes a base unit including a main body having electrical insulation properties and at least one pair of first and second through electrodes formed in the main body in a thickness direction thereof and formed of a semiconductor material, and a light emitting structure...

12/05/13 - 20130320294 - Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition
Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor...

11/28/13 - 20130313512 - Graphene electronic device and method of fabricating the same
A graphene electronic device and a method of fabricating the graphene electronic device are provided. The graphene electronic device may include a graphene channel layer formed on a hydrophobic polymer layer, and a passivation layer formed on the graphene channel layer. The hydrophobic polymer layer may prevent or reduce adsorption...

11/28/13 - 20130313513 - Semiconductor devices having modulated nanowire counts
Semiconductor devices having modulated nanowire counts and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a plurality of nanowires disposed above a substrate and stacked in a first vertical plane with a first uppermost nanowire. A second semiconductor device has...