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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Bulk Effect Device > Bulk Effect Switching In Amorphous Material > In Array

In Array

In Array patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

07/03/14 - 20140183439 - Current selector for non-volatile memory in a cross bar array based on defect and band engineering metal-dielectric-metal stacks
Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a...

07/03/14 - 20140183440 - Variable resistance memory device
A variable resistance memory device includes a plurality of cell blocks each of which includes a plurality of first lines extending in parallel to each other along a first direction, a plurality of second lines extending in parallel to each other along a second direction crossing the first direction, and...

06/26/14 - 20140175371 - Vertical cross-point embedded memory architecture for metal-conductive oxide-metal (mcom) memory elements
Vertical cross-point embedded memory architectures for metal-conductive oxide-metal (MCOM) memory elements are described. For example, a memory array includes a substrate. A plurality of horizontal wordlines is disposed in a plane above the substrate. A plurality of vertical bitlines is disposed above the substrate and interposed with the plurality of...

06/19/14 - 20140166971 - Variable resistance memory device and method of manufacturing the same
A variable resistance memory device includes a semiconductor substrate having a vertical transistor with a shunt gate that increases an area of a gate of the vertical transistor....

06/19/14 - 20140166972 - Methods of self-aligned growth of chalcogenide memory access device
Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the...

06/12/14 - 20140158974 - Resistance-switching memory cells adapted for use at low voltage
A memory cell is provided that includes a diode and a resistance-switching material layer coupled in series with the diode. The resistance-switching material layer has a thickness between 20 and 65 angstroms. Other aspects are also provided....

06/12/14 - 20140158975 - Memory cell that includes a sidewall collar for pillar isolation and methods of forming the same
A method of forming a memory cell is provided. The method includes forming a steering element pillar having a first stiffness and a sidewall, forming a sidewall collar along at least a portion of the sidewall of the steering element pillar, the sidewall collar having a second stiffness, wherein the...

05/22/14 - 20140138609 - High density resistive memory having a vertical dual channel transistor
Resistive memory cell array fabricated with unit areas able to be scaled down to 4 F2, where F is minimum feature size in a technology node are described. Memory cells in a pair of cells commonly include a pair of buried sources in the bottom of trenches formed in a...

05/15/14 - 20140131655 - Semiconductor memory devices and methods of fabricating the same
Provided are semiconductor memory devices and the methods of fabricating the same. The method may include forming a plurality of diode patterns in each of a plurality of first trenches, each of the plurality of first trenches including at least two active regions, the plurality of diode patterns occupying a...

05/08/14 - 20140124728 - Resistive memory device, resistive memory array, and method of manufacturing resistive memory device
A resistive memory device has a structure in which a source, a channel layer, a drain, and a resistive memory layer are sequentially formed in a particular direction, with a gate electrode formed around the channel layer. The source, channel layer, and drain may be vertically stacked on a substrate,...

05/08/14 - 20140124729 - 3-dimensional (3d) non-volatile memory device and method of fabricating the same
Provided are 3D non-volatile memory devices and methods of fabricating the same. A 3D non-volatile memory device according to an embodiment of the present invention includes a plurality of conductive lines, which are separated from one another in parallel; a plurality of conductive planes, which extend across the plurality of...

04/17/14 - 20140103286 - Integrated circuit tamper detection and response
The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits. One integrated circuit having a tamper detection and response device includes at least one photovoltaic cell and at least one memory cell coupled to the at least one photovoltaic cell....

04/17/14 - 20140103287 - Semiconductor storage device and method for manufacturing same
Disclosed are a semiconductor storage device and a manufacturing method. The storage device has: a substrate; a first word line above the substrate; a first laminated body above the first word line and having N+1 first inter-gate insulating layers and N first semiconductor layers alternately laminated; a first bit line...

04/17/14 - 20140103288 - Memory arrays and associated methods of manufacturing
Memory arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a memory array includes an access line extending along a first direction and a first contact line and a second contact line extending along a second direction different from the first direction. The first and second contact...

03/20/14 - 20140077149 - Resistance memory cell, resistance memory array and method of forming the same
A resistance memory cell including a variable resistance layer is provided. The variable resistance layer includes at least one dominant resistance layer and at least one auxiliary resistance layer. The dominant resistance layer(s) and the auxiliary resistance layer(s) in totality form a closed ion exchange system, the exchanged ions are...

03/20/14 - 20140077150 - Semiconductor memory storage array device and method for fabricating the same
A semiconductor memory storage array device comprises a first electrode layer, an oxide layer, a second electrode layer, a memory material layer and a first insulator layer. The oxide layer is disposed on the first electrode layer. The second electrode layer is disposed on the oxide layer. The memory material...

03/06/14 - 20140061574 - Three dimensional memory array architecture
Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular...

03/06/14 - 20140061575 - Three dimensional memory array architecture
Three dimensional memory array architectures and methods of forming the same are provided. An example memory array can include a stack comprising a plurality of first conductive lines at a number of levels separated from one another by at least an insulation material, and at least one conductive extension arranged...

03/06/14 - 20140061576 - Fin-type memory
Memory devices and methods for forming a device are disclosed. A substrate prepared with a lower electrode level with bottom electrodes is provided. Fin stack layers are formed on the lower electrode level. Spacers are formed on top of the fin stack layers. The spacers have a width which is...

03/06/14 - 20140061577 - Semiconductor memory device and method of manufacturing the same
First, a trench penetrating first conductive layers and interlayer insulating layers is formed. Next, a column-shaped conductive layer is formed to fill the trench via a side wall layer. Then, after formation of the side wall layer, by migration of oxygen atoms between the side wall layer and the first...

03/06/14 - 20140061578 - Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device below comprises: a memory cell array configured having memory cells arranged therein disposed at intersections of a plurality of first lines and a plurality of second lines formed so as to intersect each other, and the memory cells each comprising a variable resistance element; and...

03/06/14 - 20140061579 - Nonvolatile memory element and nonvolatile memory device
A variable resistance nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer including: a first oxide layer including a metal oxide having non-stoichiometric composition and including p-type carriers; a second oxide layer located between and in contact with the first oxide layer and a...

03/06/14 - 20140061580 - Semiconductor stack incorporating phase change material
A semiconductor stack for performing at least a logic operation includes adjacent layers arranged in a stacked configuration with each layer comprising at least a phase-change memory cell in which a phase-change material is provided between a heater electrical terminal and at least two further heater electrical terminals, the phase-change...

03/06/14 - 20140061581 - Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor
A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line. Dielectric pillars are placed on both sides of the gate contact. Also a method...

02/27/14 - 20140054538 - 3-dimensional stack memory device
A 3-dimensional stack memory device includes a semiconductor substrate, a stacked active pattern configured so that a plurality of stripe shape active regions and insulation layers are stacked alternatively over the semiconductor substrate, a gate electrode formed in the stacked active pattern, a source and drain formed at both sides...

02/27/14 - 20140054539 - Method and structure of monolithically integrated ic and resistive memory using ic foundry-compatible processes
The present invention relates to integrating a resistive o y device on top of an IC substrate monolithically using IC-foundry compatible processes. A method for forming an integrated circuit includes receiving a semiconductor substrate having a CMOS IC device formed on a surface region, forming a dielectric layer overlying the...

02/20/14 - 20140048763 - Forming resistive random access memories together with fuse arrays
A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching...

01/30/14 - 20140027705 - Memristor cell structures for high density arrays
A memristor array includes a lower layer of crossbars, upper layer of crossbars intersecting the lower layer of crossbars, memristor cells interposed between intersecting crossbars, and pores separating adjacent memristor cells. A method forming a memristor array is also provided....

01/30/14 - 20140027706 - Switching device and operating method for the same and memory array
A switching device and an operating method for the same and a memory array are provided. The switching device comprises a first solid electrolyte, a second solid electrolyte and a switching layer. The switching layer is adjoined between the first solid electrolyte and the second solid electrolyte....

01/30/14 - 20140027707 - Memory device and fabricating method thereof
According to one embodiment, a memory device includes first interconnects, second interconnects, and a first memory cell. The first memory cell is located in an intersection of one of the first interconnects and one of the second interconnects. The first memory cell includes a first multilayer structure and a first...

01/23/14 - 20140021439 - Semiconductor constructions, memory arrays, methods of forming semiconductor constructions and methods of forming memory arrays
Some embodiments include methods of forming semiconductor constructions. Carbon-containing material is formed over oxygen-sensitive material. The carbon-containing material and oxygen-sensitive material together form a structure having a sidewall that extends along both the carbon-containing material and the oxygen-sensitive material. First protective material is formed along the sidewall. The first protective...

12/26/13 - 20130341587 - Memory arrays and methods of forming memory cells
Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend...

12/05/13 - 20130320292 - Semiconductor memory device
A semiconductor memory device in accordance with an embodiment comprises first lines, second lines, and a memory cell array including memory cells. Each of the memory cells is disposed at each of intersections of the first lines and the second lines and is configured by a rectifier element and a...

11/28/13 - 20130313511 - Memory cell array and variable resistive memory device including the same
A memory cell array and a resistive variable memory device including the memory cell array are provided. The memory cell array includes a memory group. The memory cell array includes a pair of word lines, an inter-pattern insulating layer interposed between the pair of word lines, and a plurality of...

11/21/13 - 20130306933 - Nonvolatile memory cells and arrays of nonvolatile memory cells
A nonvolatile memory cell includes first and second electrodes. Programmable material and a select device are received in series between and with the first and second electrodes. Current conductive material is in series between and with the programmable material and the select device. An array of vertically stacked tiers of...

11/07/13 - 20130292633 - Etch bias homogenization
Methods and memory devices formed using etch bias homogenization are provided. One example method of forming a memory device using etch bias homogenization includes forming conductive material at respective levels over a substrate. Each respective level of conductive material is electrically coupled to corresponding circuitry on the substrate during patterning...

11/07/13 - 20130292634 - Resistance-switching memory cells having reduced metal migration and low current operation and methods of forming the same
In some aspects, a memory cell is provided that includes a steering element, a metal-insulator-metal (“MIM”) stack coupled in series with the steering element, and a conductor above the MIM stack. The MIM stack includes a resistance switching element and a top electrode disposed on the resistance switching element, and...

11/07/13 - 20130292635 - Memory cells, memory cell arrays, methods of using and methods of making
A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second...

10/31/13 - 20130285006 - Variable resistance memory device and method of fabricating the same
A variable resistance memory device includes a selection transistor, which includes a first doped region and a second doped region, a vertical electrode coupled to the first doped region of the selection transistor, a bit line coupled to the second doped region of the selection transistor, a plurality of word...

10/24/13 - 20130277639 - Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor
A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line with a spacer of electrically insulating material surrounding the gate contact. Also a method...

10/24/13 - 20130277640 - Non-volatile semiconductor memory device and method for manufacturing the same
A non-volatile semiconductor memory device includes a cell array layer including a first wire, one or more memory cells stacked on the first wire, and a second wire formed on the memory cell so as to cross the first wire, wherein the memory cell includes a current rectifying element and...

10/17/13 - 20130270510 - Nonvolatile semiconductor memory element, nonvolatile semiconductor memory device, and method for manufacturing nonvolatile semiconductor memory device
A nonvolatile semiconductor memory element includes: a variable resistance element including a first electrode, a variable resistance layer, and a second electrode, and having a resistance value which changes according to a polarity of an electric pulse applied between the first electrode and the second electrode; and a current steering...

10/10/13 - 20130264536 - Siox-based nonvolatile memory architecture
Various embodiments of the present invention pertain to memresistor cells that comprise: (1) a substrate; (2) an electrical switch associated with the substrate; (3) an insulating layer; and (3) a resistive memory material. The resistive memory material is selected from the group consisting of SiOx, SiOxH, SiOxNy, SiOxNyH, SiOxCz, SiOxCzH,...

10/10/13 - 20130264537 - Phase change memory and method for fabricating the same
The storage STI units have thickness substantially equal to thickness of the vertical LEDs. The peripheral STI units have thickness substantially equal to thickness of the storage STI units. The N-type conductive region contains SiC. A top of P-type conductive region is flush with a top of the peripheral substrate....

10/03/13 - 20130256625 - Variable resistance memory device
A variable resistance memory device includes: a pair of first electrodes and a second electrode interposed between the pair of first electrodes; a first variable resistance material layer interposed between one of the first electrodes and the second electrode; and a second variable resistance material layer interposed between the other...

10/03/13 - 20130256626 - Semiconductor memory device and a method of manufacturing the same
Disclosed herein is a semiconductor memory device, including: a first electrode formed on a substrate; an ion source layer formed on an upper layer of the first electrode; and a second electrode formed on an upper layer of the ion source layer. Resistance change type memory cells in each of...

09/26/13 - 20130248814 - Non-volatile memory device and array thereof
A non-volatile memory device including a first electrode, a resistor structure, a diode structure, and a second electrode is provided. The resistor structure is disposed on the first electrode. The resistor structure includes a first oxide layer. The first oxide layer is disposed on the first electrode. The diode structure...

09/12/13 - 20130234102 - Bipolar junction transistors, memory arrays, and methods of forming bipolar junction transistors and memory arrays
Some embodiments include methods of forming BJTs. A first type doped region is formed within semiconductor material. First and second trenches are formed within the semiconductor material to pattern an array of pedestals, and the trenches are filled with electrically insulative material. An upper portion of the first type doped...

09/12/13 - 20130234103 - Nanoscale switching device with an amorphous switching material
Nanoscale switching devices are disclosed. The devices have a first electrode of a nanoscale width; a second electrode of a nanoscale width; and a layer of an active region disposed between and in electrical contact with the first and second electrodes. The active region contains a switching material capable of...

09/12/13 - 20130234104 - Memory cell that includes a sidewall collar for pillar isolation and methods of forming the same
A method of forming a memory cell is provided. The method includes forming a steering element pillar having a first stiffness and a sidewall, forming a sidewall collar along at least a portion of the sidewall of the steering element pillar, the sidewall collar having a second stiffness, wherein the...

08/29/13 - 20130221317 - Creating an embedded reram memory from a high-k metal gate transistor structure
An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the...

08/29/13 - 20130221318 - Memory cells and memory cell arrays
Some embodiments include memory cells. The memory cells may have a first electrode, and a trench-shaped programmable material structure over the first electrode. The trench-shape defines an opening. The programmable material may be configured to reversibly retain a conductive bridge. The memory cell may have an ion source material directly...