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Write driver circuit for memory arrayWrite driver circuit for memory array description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060176743, Write driver circuit for memory array. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] This invention relates to accessing memory arrays, and in particular, to a write driver circuit for a memory array. BACKGROUND [0002] FIGS. 1A and 1B illustrate a high performance, low power domino SRAM design including multiple local cell groups such as that shown in U.S. Pat. No. 6,657,886, the entire contents of which are incorporated herein by reference. As shown in FIG. 1A, each cell group includes multiple SRAM cells 1-N and local true and complement bitlines LBLT and LBLC. Each SRAM cell includes a pair of inverters that operate together in a loop to store true and complement (T and C) data. The local true bitline LBLT and the local complement bitline LBLC are connected to each SRAM cell by a pair of wordline N-channel field effect transistors (NFETs) to respective true and complement sides of the inverters. A WORDLINE provides the gate input to wordline NFETs. A particular WORDLINE is activated, turning on respective wordline NFETs to perform a read or write operation. [0003] As shown in FIG. 1B, the prior art domino SRAM includes multiple local cell groups 1-M. Associated with each local cell group are precharge true and complement circuits coupled to the respective local true and complement bitlines LBLT and LBLC, write true and write complement circuits, and a local evaluate circuit. Each of the local evaluate circuits is coupled to a global bitline labeled 2ND STAGE EVAL and a second stage inverter that provides output data or is coupled to more stages. A write predriver circuit receiving input data and a write enable signal provides write true WRITE T and write complement WRITE C signals to the write true and write complement circuits of each local cell group. [0004] A read occurs when a wordline is activated. Since true and complement (T and C) data is stored in the SRAM memory cell, either the precharged high true local bitline LBLT will be discharged if a zero was stored on the true side or the precharged high complement bitline LBLC will be discharged if a zero was stored on the complement side. The local bitline, LBLT or LBLC connected to the one side will remain in its high precharged state. If the true local bitline LBLT was discharged then the zero will propagate through one or more series of domino stages eventually to the output of the SRAM array. If the true local bitline was not discharged then no switching through the domino stages will occur and the precharged value will remain at the SRAM output. [0005] To perform a write operation, the wordline is activated as in a read. Then either the write true WRITE T or write complement WRITE C signal is activated which pulls either the true or complement local bitline low via the respective write true circuit or write complement circuit while the other local bitline remains at its precharged level, thus updating the SRAM cell. [0006] During a write operation, the wordline is activated as in a read. The cell will begin to discharge the bitline corresponding to the side of the cell that has a zero stored. If the write operation is meant to change the state of the cell, the write circuit will discharge the bitline opposite of the one that the cell has begun to discharge. Thus the bitline being discharged by the cell can trigger a read before the cell is updated by the write operation, particularly if the write circuit response is slow. Such an occurrence can produce inaccurate results and is referred to as a false read. There is a need in the art for a circuit for driving write operations that also suppresses false reads. SUMMARY OF THE INVENTION [0007] Embodiments of the invention include a circuit for interfacing local bitlines to a global bitline. The circuit includes an interface line coupled to a local bitline through a local bitline device. A global output device has an input coupled to the interface line and an output coupled to the global bitline. A clamping device is coupled to the interface line, the clamping device coupling the interface line to ground in response to a data in signal. A memory having the circuit is also disclosed. [0008] Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0009] The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: [0010] FIG. 1A illustrates an exemplary conventional SRAM cell; [0011] FIG. 1B illustrates an exemplary domino SRAM; [0012] FIG. 2 is a block diagram of a synchronization circuit for use with a memory array; [0013] FIG. 3 depicts two cell blocks interfaced at a global bitline interface; [0014] FIG. 4 depicts a local bitline data driver in an exemplary embodiment; and [0015] FIG. 5 depicts a local bitline hold unit in an alternate embodiment. [0016] The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings. DETAILED DESCRIPTION OF THE INVENTION [0017] FIG. 2 is a block diagram of a synchronization circuit 300 for use with a memory array. The synchronization circuit 300 is divided into a top and bottom portion, corresponding to the top local cell group 200 and the bottom local cell group 202 of a memory array that is divided into a top sub-array and a bottom sub-array. Local interface circuits 400 access the top local cell group 200 or the bottom local cell group 202 over bitlines LBLTtop, LBLCtop, LBLTbot and LBLCbot and output a global bitline 402. [0018] Operation of the synchronization circuit 300 will be made with reference to the top portion, with corresponding elements in the bottom portion operating in the same manner. The synchronization circuit 300 generates a number of array signals in response to a synchronization signal. In the embodiment of FIG. 2, the synchronization signal is a most significant bit signal 302 labeled msb_top. The most significant bit signal 302 is from a decoded address word. [0019] The most significant bit signal 302 is provided to an inverter 304 that generates the compliment of the most significant bit signal 302, labeled msbn_top. The compliment of the most significant bit signal 302 is provided to word drivers 306 and 308 to enable the generation of wordline select signals output by word drivers 306 and 308. The wordline signal is the row access signal that activates memory cells in top local cell group 200. The wordline drivers 306 and 308 are described in further detail with reference to FIG. 3. Continue reading about Write driver circuit for memory array... Full patent description for Write driver circuit for memory array Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Write driver circuit for memory array patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Write driver circuit for memory array or other areas of interest. ### Previous Patent Application: Semiconductor device and writing method Next Patent Application: Low power chip select (cs) latency option Industry Class: Static information storage and retrieval ### FreshPatents.com Support Thank you for viewing the Write driver circuit for memory array patent info. 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