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Williams, Morgan & Amerson patentsThe following is a sampling of recent Williams, Morgan & Amerson patent applications (USPTO Patent Application #, Patent Title) sorted by month.
February 2011 - Williams, Morgan & Amerson patents
20110044831 - Motor with high pressure rated can 20110045031 - Use of buckysome or carbon nanotube for drug delivery 20110033031 - Method and apparatus for detecting ring trip precursors 20110033038 - Method and apparatus for battery switching during ringing 20110033039 - Method and apparatus for controlling ringing voltage 20110026424 - Triggering migration of a network access agent associated with an access terminal January 2011 - Williams, Morgan & Amerson patents
20110014482 - Ductile multilayer silicone resin films 20110003441 - Light activated silicon controlled switch December 2010 - Williams, Morgan & Amerson patents
20100327358 - Semiconductor element formed in a crystalline substrate material and comprising an embedded in situ n-doped semiconductor material 20100327362 - Non-insulating stressed material layers in a contact level of semiconductor devices 20100327367 - Contact optimization for enhancing stress transfer in closely spaced transistors 20100327368 - Enhancing selectivity during formation of a channel semiconductor alloy by a wet oxidation process 20100327373 - Uniform high-k metal gate stacks by adjusting threshold voltage for sophisticated transistors by diffusing a metal species prior to gate patterning 20100330757 - Enhanced cap layer integrity in a high-k metal gate stack by using a hard mask for offset spacer patterning 20100330790 - Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers 20100330808 - Cap layer removal in a high-k metal gate stack by using an etch process 20100322158 - Indicating dynamic allocation of component carriers in multi-component carrier systems 20100322858 - Radiohaloimatinibs and methods of their synthesis and use in pet imaging of cancers 20100310972 - Performing double exposure photolithography using a single reticle 20100301416 - Strain transformation in biaxially strained soi substrates for performance enhancement of p-channel and n-channel transistors 20100301421 - Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode 20100301427 - Work function adjustment in high-k metal gate electrode structures by selectively removing a barrier layer 20100301486 - High-aspect ratio contact element with superior shape in a semiconductor device for improving liner deposition 20100301489 - Microstructure device including a metallization structure with self-aligned air gaps formed based on a sacrificial material 20100301494 - Re-establishing a hydrophobic surface of sensitive low-k dielectrics in microstructure devices 20100304333 - Expandable dental implant 20100304542 - Enhanced etch stop capability during patterning of silicon nitride including layer stacks by providing a chemically formed oxide layer during semiconductor processing 20100304566 - Establishing a hydrophobic surface of sensitive low-k dielectrics of microstructure devices by in situ plasma treatment 20100305737 - Tuning a process controller based on a dynamic sampling rate November 2010 - Williams, Morgan & Amerson patents
20100297072 - Combinations of immunostimulatory agents, oncolytic virus, and additional anticancer therapy 20100289080 - Semiconductor device comprising metal gates and a silicon containing resistor formed on an isolation structure 20100289081 - Reduced silicon thickness of n-channel transistors in soi cmos devices 20100289083 - Multi-step deposition of a spacer material for reducing void formation in a dielectric material of a contact level of a semiconductor device 20100289089 - Adjusting threshold voltage for sophisticated transistors by diffusing a gate dielectric cap layer material prior to gate dielectric stabilization 20100289090 - Enhancing uniformity of a channel semiconductor alloy by forming sti structures after the growth process 20100289094 - Enhancing deposition uniformity of a channel semiconductor alloy by an in situ etch process 20100289114 - Semiconductor element formed in a crystalline substrate material and comprising an embedded in situ doped semiconductor material 20100289125 - Enhanced electromigration performance of copper lines in metallization systems of semiconductor devices by surface alloying 20100282694 - Gravity separation vessel, baffle arranged in a gravity separation vessel and method of separating a liquid/gas mixture 20100284088 - Dichroic filters formed using silicon carbide based layers 20100285486 - Non-invasive detection of bladder cancer by fluorescence in situ hybridization of aurora a 20100276790 - Interlayer dielectric material in a semiconductor device comprising stressed layers with an intermediate buffer material 20100278730 - Non-invasive molecular imaging of cellular histone deacetylase substrate using magnetic resonance spectroscopy (mrs) or positron emission tomography (pet) August 2010 - Williams, Morgan & Amerson patents
20100200146 - Low thermal distortion silicone composite molds 20100203698 - Method of forming a semiconductor structure 20100193860 - Short channel transistor with reduced length variation by using amorphous electrode material during implantation 20100193872 - Work function adjustment in a high-k gate electrode structure after transistor fabrication by using lanthanum 20100193896 - Method for nitridation of shallow trench isolation structure to prevent oxygen absorption 20100193963 - Void sealing in a dielectric material of a contact level of a semiconductor device comprising closely spaced transistors 20100197133 - Method of forming a metallization system of a semiconductor device by using a hard mask for defining the via size 20100197340 - Monitoring and adjusting transmit power level(s) in a communications system 20100198556 - Method and system for semiconductor process control and monitoring by using a data quality metric July 2010 - Williams, Morgan & Amerson patents
20100187635 - Semiconductor device comprising nmos and pmos transistors with embedded si/ge material for creating tensile and compressive strain 20100190309 - Method for adjusting the height of a gate electrode in a semiconductor device 20100181619 - Method of forming a field effect transistor 20100182676 - Variable- beamwidth angle encoding laser scanner 20100182774 - Managing load power consumption based on stored energy rate 20100183779 - Method and apparatus for sanitizing consumable products using ultraviolet light 20100175286 - Name badge with illuminated graphic display 20100178490 - Roll-to-roll plasma enhanced chemical vapor deposition method of barrier layers comprising silicon and carbon 20100163426 - Electrochemical planarization system comprising enhanced electrolyte flow 20100163939 - Transistor device comprising an embedded semiconductor alloy having an asymmetric configuration 20100164016 - Adjusting of strain caused in a transistor channel by semiconductor material provided for threshold adjustment 20100164093 - Heat dissipation in temperature critical device areas of semiconductor devices by heat pipes connecting to the substrate backside 20100164123 - Local silicidation of via bottoms in metallization systems of semiconductor devices 20100164530 - Adjusting configuration of a multiple gate transistor by controlling individual fins June 2010 - Williams, Morgan & Amerson patents
20100155727 - Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions 20100161103 - Method and system for advanced process control in an etch system by gas flow control on the basis of cd measurements 20100152140 - Method of cancer treatment with naphthol analogs 20100142471 - Coordinating transmission scheduling among multiple base stations 20100144675 - Regulation of sgc function by corrin derivatives 20100133614 - Multiple gate transistor having homogenously silicided fin end portions 20100133620 - Reduced topography-related irregularities during the patterning of two different stress-inducing layers in the contact level of a semiconductor device 20100133621 - Restricted stress regions formed in the contact level of a semiconductor device 20100133648 - Microstructure device including a metallization structure with self-aligned air gaps between closely spaced metal lines 20100133700 - Performance enhancement in metallization systems of microstructure devices by incorporating grain size increasing metal features 20100134125 - Built-in compliance in test structures for leakage and dielectric breakdown of dielectric materials of metallization systems of semiconductor devices 20100134167 - Compensation of degradation of performance of semiconductor devices by clock duty cycle adaptation May 2010 - Williams, Morgan & Amerson patents
20100128243 - Compact collimator lens form for large mode area and low numerical aperture fiber laser applications 20100116886 - Imaging semi-active laser system 20100107403 - Semiconductor device comprising efuses of enhanced programming efficiency 20100107717 - Method and device for fabricating bonding wires on the basis of microelectronic manufacturing techniques 20100109005 - Semiconductor device comprising a distributed interconnected sensor structure for die internal monitoring purposes 20100109012 - Stress transfer enhancement in transistors by a late gate re-crystallization 20100109091 - Recessed drain and source areas in combination with advanced silicide formation in transistors 20100109131 - Reduced wafer warpage in semiconductors by stress engineering in the metallization system 20100109158 - Semiconductor device including a reduced stress configuration for metal pillars 20100109161 - Reducing metal voids in a metallization layer stack of a semiconductor device by providing a dielectric barrier layer 20100109757 - Compensation of operating time-related degradation of operating speed by a constant total die power mode 20100110402 - Focus correction in lithography tools via lens aberration control 20100111151 - Method and apparatus for metallic line testing of a subscriber line 20100112468 - Self-correcting substrate support system for focus control in exposure systems 20100112816 - Method of reducing non-uniformities during chemical mechanical polishing of microstructure devices by using cmp pads in a glazed mode April 2010 - Williams, Morgan & Amerson patents
20100106278 - Product-related feedback for process control 20100099085 - Serum dna methylation screening for cancer 20100077839 - In situ monitoring of metal contamination during microstructure processing 20100078645 - Semiconductor device comprising a buried poly resistor 20100078653 - Transistor having a high-k metal gate stack and a compressively stressed channel 20100078689 - Transistor with embedded si/ge material having reduced offset to the channel region 20100078691 - Transistor with embedded si/ge material having enhanced across-substrate uniformity 20100078735 - Cmos device comprising nmos transistors and pmos transistors having increased strain-inducing sources and closely spaced metal silicide regions 20100078736 - Asymmetric transistor devices formed by asymmetric spacers and tilted implantation 20100078821 - Metal cap layer with enhanced etch resistivity for copper-based metal regions in semiconductor devices 20100078823 - Contacts and vias of a semiconductor device formed by a hard mask and double exposure 20100079843 - Normally emitting pixel architecture for frustrated total internal reflection displays 20100079959 - Semiconductor device comprising an in-chip active heat transfer system 20100081244 - Transistor device comprising an asymmetric embedded semiconductor alloy 20100081277 - Method for passivating exposed copper surfaces in a metallization layer of a semiconductor device 20100082519 - Unique interface in service oriented architecture March 2010 - Williams, Morgan & Amerson patents
20100073664 - Lookdown and loitering ladar system 20100059230 - Coil tubing guide 20100062012 - Negative genetic regulation of cancer cell renewal in synergy with notch- or numb-specific immunotherapy 20100051286 - Optical sensing system for wellhead equipment 20100052068 - Drive current adjustment for transistors formed in the same active region by locally providing embedded strain-inducing semiconductor material in the active region 20100052069 - Static ram cell design and multi-contact regime for connecting double channel transistors 20100052110 - Semiconductor device comprising a carbon-based material for through hole vias 20100052134 - 3-d integrated semiconductor device comprising intermediate heat spreading capabilities 20100052137 - Enhanced wire bond stability on reactive metal surfaces of a semiconductor device by encapsulation of the bond structure 20100052147 - Semiconductor device including stress relaxation gaps for enhancing chip package interaction stability 20100052175 - Reducing leakage and dielectric breakdown in dielectric materials of metallization systems of semiconductor devices by forming recesses 20100052181 - Using a cap layer in metallization systems of semiconductor devices as a cmp and etch stop layer 20100055867 - Structured strained substrate for forming strained transistors with reduced thickness of active layer 20100055899 - Particle reduction in pecvd processes for depositing low-k material by using a plasma assisted post-deposition step 20100055902 - Reducing critical dimensions of vias and contacts above the device level of semiconductor devices 20100055903 - Enhancing structural integrity of low-k dielectrics in metallization systems of semiconductor devices by using a crack suppressing material layer February 2010 - Williams, Morgan & Amerson patents
20100039083 - Bootstrap supply for switched mode power converter 20100035867 - Inhibitors of cyclic nucleotide synthesis and their use for therapy of various diseases 20100024724 - Apparatus and method for removing bubbles from a process liquid 20100025742 - Transistor having a strained channel region caused by hydrogen-induced lattice deformation 20100025743 - Transistor with embedded si/ge material having enhanced boron confinement 20100025770 - Gate dielectrics of different thickness in pmos and nmos transistors 20100025771 - Performance enhancement in pmos and nmos transistors on the basis of silicon/carbon material 20100025772 - Semiconductor device comprising a silicon/germanium resistor 20100025776 - Drive current adjustment for transistors by local gate engineering 20100025779 - Shallow pn junction formed by in situ doping during selective growth of an embedded semiconductor alloy by a cyclic growth/etch deposition process 20100025782 - Technique for reducing silicide non-uniformities in polysilicon gate electrodes by an intermediate diffusion blocking layer 20100025855 - Enhancing structural integrity and defining critical dimensions of metallization systems of semiconductor devices by using ald techniques 20100028614 - Method of forming nanoscale features using soft lithography 20100028790 - Method and system for reducing overlay errors in semiconductor volume production using a mixed tool scenario January 2010 - Williams, Morgan & Amerson patents
20100013708 - Directive spatial interference beam control 20100006979 - Method of manufacturing a trench capacitor for high voltage processes 20100009507 - Method of constructing cmos device tubs 20100010768 - Identifying manufacturing disturbances using preliminary electrical test data 20100002910 - Method and apparatus for developing synthetic three-dimensional models from imagery December 2009 - Williams, Morgan & Amerson patents
20090321835 - Three-dimensional transistor with double channel configuration 20090321836 - Double gate and tri-gate transistor formed on a bulk substrate and method for forming the transistor 20090321837 - Contact trenches for enhancing stress transfer in closely spaced transistors 20090321841 - Cmos device comprising mos transistors with recessed drain and source areas and non-conformal metal silicide regions 20090321843 - Cmos device comprising mos transistors with recessed drain and source areas and a si/ge material in the drain and source areas of the pmos transistor 20090321850 - Threshold adjustment for mos devices by adapting a spacer width prior to implantation 20090325355 - Reducing implant degradation in tilted implantations by shifting implantation masks 20090325375 - Reducing leakage in dielectric materials including metal regions including a metal cap layer in semiconductor devices 20090325378 - Reducing contamination of semiconductor substrates during beol processing by performing a deposition/etch cycle during barrier deposition 20090315182 - Silicide interconnect structure 20090316134 - Fiber laser ladar 20090319196 - Method and system for quantitative inline material characterization in semiconductor production processes based on structural measurements and related models 20090308151 - Christmas tree with internally positioned flowmeter 20090308152 - Christmas tree with internally positioned flowmeter 20090313409 - Method and apparatus for multi-phy communication without an atm bus master 20090302295 - Structures & methods for combining carbon nanotube array and organic materials as a variable gap interposer for removing heat from solid-state devices 20090305498 - Semiconductor device comprising a copper alloy as a barrier layer in a copper metallization layer 20090294809 - Reduction of metal silicide diffusion in a semiconductor device by protecting sidewalls of an active region 20090294810 - Microstructure device including a compressively stressed low-k material layer 20090294860 - In situ formed drain and source regions in a silicon/germanium containing transistor device 20090294868 - Drive current adjustment for transistors formed in the same active region by locally inducing different lateral strain levels in the active region 20090294898 - Microstructure device including a metallization structure with self-aligned air gaps between closely spaced metal lines 20090294921 - Semiconductor device comprising metal lines with a selectively formed dielectric cap layer 20090295457 - Cold temperature control in a semiconductor device 20090296920 - Echo cancellation balance using noise generator and average power detection 20090298249 - Drive current increase in transistors by asymmetric amorphization implantation 20090298279 - Method for reducing metal irregularities in advanced metallization systems of semiconductor devices 20090299678 - Method and apparatus for determining a product loading plan for a testing system November 2009 - Williams, Morgan & Amerson patents
20090290517 - Calibrating radiofrequency paths of a phased-array antenna 20090292385 - Automated throughput control system and method of operating the same 20090286927 - Hyperbranched polymers 20090277644 - Method and apparatus for christmas tree condition monitoring 20090277644 - Method and apparatus for christmas tree condition monitoring 20090281197 - Acetic acid/thymol compositions and their use in the treatment of onychomycosis 20090281197 - Acetic acid/thymol compositions and their use in the treatment of onychomycosis 20090273035 - Method for selectively removing a spacer in a dual stress liner approach 20090273036 - Method for reducing defects of gate of cmos devices during cleaning processes by modifying a parasitic pn junction 20090273035 - Method for selectively removing a spacer in a dual stress liner approach 20090273036 - Method for reducing defects of gate of cmos devices during cleaning processes by modifying a parasitic pn junction 20090273053 - Semiconductor device including analog circuitry having a plurality of devices of reduced mismatch 20090273053 - Semiconductor device including analog circuitry having a plurality of devices of reduced mismatch 20090273086 - Method of reducing erosion of a metal cap layer during via patterning in semiconductor devices 20090273086 - Method of reducing erosion of a metal cap layer during via patterning in semiconductor devices 20090274981 - Method of detecting repeating defects in lithography masks on the basis of test substrates exposed under varying conditions 20090274981 - Method of detecting repeating defects in lithography masks on the basis of test substrates exposed under varying conditions 20090275200 - Technique for reducing topography-related irregularities during the patterning of a dielectric material in a contact level of closely spaced transistors 20090275200 - Technique for reducing topography-related irregularities during the patterning of a dielectric material in a contact level of closely spaced transistors 20090275264 - System and method for optical endpoint detection during cmp by using an across-substrate signal 20090275264 - System and method for optical endpoint detection during cmp by using an across-substrate signal 20090276075 - Method and system for monitoring a predicted product quality distribution 20090276077 - Method and system for semiconductor process control and monitoring by using pca models of reduced size 20090276075 - Method and system for monitoring a predicted product quality distribution 20090276077 - Method and system for semiconductor process control and monitoring by using pca models of reduced size 20090276174 - Method and system for a two-step prediction of a quality distribution of semiconductor devices 20090276174 - Method and system for a two-step prediction of a quality distribution of semiconductor devices 20090276617 - Computer system comprising a secure boot mechanism on the basis of symmetric key encryption 20090276617 - Computer system comprising a secure boot mechanism on the basis of symmetric key encryption July 2009 - Williams, Morgan & Amerson patents
20090178798 - Fracturing isolation sleeve 20090175778 - Spheroidal aggregates comprising single-wall carbon nanotubes and method for making the same 20090166618 - Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions 20090166738 - Ram cell including a transistor with floating body for information storage having asymmetric drain/source extensions 20090166794 - Temperature monitoring in a semiconductor device by thermocouples distributed in the contact structure 20090166800 - Interlayer dielectric material in a semiconductor device comprising a doublet structure of stressed materials 20090166814 - Interlayer dielectric material in a semiconductor device comprising stressed layers with an intermediate buffer material 20090166861 - Wire bonding of aluminum-free metallization layers by surface conditioning 20090169819 - Nanostructure films 20090170319 - Method of forming an interlayer dielectric material having different removal rates during cmp 20090170320 - Cmp system and method using individually controlled temperature zones 20090170339 - Reducing the creation of charge traps at gate dielectrics in mos transistors by performing a hydrogen treatment 20090171492 - Method and apparatus for reducing setups during test, mark and pack operations
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