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11/27/08 - USPTO Class 365 | 90 views | #20080291748 | Prev - Next | About this Page

Wide window clock scheme for loading output fifo registers

Title: Wide window clock scheme for loading output fifo registers

Brief Patent Description - Full Patent Description - Patent Claims

The Patent Description & Claims data below is from USPTO Patent Application 20080291748, Wide window clock scheme for loading output fifo registers.

1. A FIFO clock circuit comprising: a first capture circuit receiving first and second internal clock signals; a first delay circuit coupled to the first capture circuit receiving an external clock signal; a first FIFO clock start capture and latch circuit coupled to the first delay circuit; a first FIFO clock generator circuit receiving read/write information coupled to the first FIFO clock start capture and latch circuit for generating a first FIFO clock signal; a second capture circuit receiving first and second internal clock signals; a second delay circuit coupled to the second capture circuit receiving an external clock signal; a second FIFO clock start capture and latch circuit coupled to the second delay circuit; a second FIFO clock generator circuit receiving read/write information coupled to the second FIFO clock start capture and latch circuit for generating a first FIFO clock signal; and circuitry for providing latency information to the first and second capture circuits and to the first and second FIFO clock generator circuits, wherein the first and second FIFO clock start capture and latch circuits are in electrical communication.

Brief Patent Description - Full Patent Description - Patent Claims

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Semiconductor storage device and burst operation method
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Semiconductor device that uses a plurality of source voltages
Industry Class:
Static information storage and retrieval

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