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  Weighted fair queue having adjustable scaling factorUSPTO Application #: 20080013452Title: Weighted fair queue having adjustable scaling factor Abstract: A scheduler for a network processor includes a scheduling queue in which weighted fair queuing is applied. The scheduling queue has a range R. Flows are attached to the scheduling queue at a distance D from a current pointer for the scheduling queue. The distance D is calculated for each flow according to the formula D=((WF×FS)/SF), where WF is a weighting factor applicable to a respective flow; FS is a frame size attributable to the respective flow; and SF is a scaling factor. The scaling factor SF is adjusted depending on a comparison of the distance D to the range R. (end of abstract) Agent: Ibm Corporation, Intellectual Property Law - Rochester, MN, US Inventors: William John Goetzinger, Glen Howard Handlogten, James Francis Mikos, David Alan Norgaard USPTO Applicaton #: 20080013452 - Class: 370235000 (USPTO) Related Patent Categories: Multiplex Communications, Data Flow Congestion Prevention Or Control, Flow Control Of Data Transmission Through A Network The Patent Description & Claims data below is from USPTO Patent Application 20080013452. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] The present application is a continuation of and claims priority to U.S. patent application Ser. No. 10/015,760, filed Nov. 1, 2001, titled "WEIGHTED FAIR QUEUE HAVING ADJUSTABLE SCALING FACTOR," which is hereby incorporated by reference herein in its entirety. CROSS REFERENCE TO RELATED PATENT APPLICATIONS [0002] The present application is related to the following U.S. patent applications, each of which is hereby incorporated by reference herein in its entirety: [0003] U.S. patent application Ser. No. 10/016,518, filed Nov. 1, 2001, titled "WEIGHTED FAIR QUEUE HAVING EXTENDED EFFECTIVE RANGE" (IBM Docket No. ROC920010199US1); [0004] U.S. patent application Ser. No. 10/015,994, filed Nov. 1, 2001, titled "WEIGHTED FAIR QUEUE SERVING PLURAL OUTPUT PORTS" (IBM Docket No. ROC920010200US1); [0005] U.S. patent application Ser. No. 10/002,085, filed Nov. 1, 2001, titled "EMPTY INDICATORS FOR WEIGHTED FAIR QUEUES" (IBM Docket No. ROC920010202US1); [0006] U.S. patent application Ser. No. 10/004,373, filed Nov. 1, 2001, titled "QoS SCHEDULER AND METHOD FOR IMPLEMENTING PEAK SERVICE DISTANCE USING NEXT PEAK SERVICE TIME VIOLATED INDICATION" now U.S. Pat. No. 6,973,036 issued Dec. 6, 2005 (IBM Docket No. ROC920010203US1); [0007] U.S. patent application Ser. No. 10/002,416, filed Nov. 1, 2001, titled "QoS SCHEDULER AND METHOD FOR IMPLEMENTING QUALITY OF SERVICE WITH AGING STAMPS" now U.S. Pat. No. 7,103,051 issued on Sep. 5, 2006 (IBM Docket No. ROC920010204US1); [0008] U.S. patent application Ser. No. 10/004,440, filed Nov. 1, 2001, titled "QoS SCHEDULER AND METHOD FOR IMPLEMENTING QUALITY OF SERVICE WITH CACHED STATUS ARRAY" now U.S. Pat. No. 7,046,676 issued on May 16, 2006 (IBM Docket No. ROC920010205US1); and [0009] U.S. patent application Ser. No. 10/004,217, filed Nov. 1, 2001, titled "QoS SCHEDULER AND METHOD FOR IMPLEMENTING QUALITY OF SERVICE ANTICIPATING THE END OF A CHAIN OF FLOWS" now U.S. Pat. No. 6,982,986 issued on Jan. 3, 2006 (IBM Docket No. ROC920010206US1). FIELD OF THE INVENTION [0010] The present invention is concerned with data and storage communication systems and is more particularly concerned with a scheduler component of a network processor. BACKGROUND OF THE INVENTION [0011] Data and storage communication networks are in widespread use. In many data and storage communication networks, data packet switching is employed to route data packets or frames from point to point between source and destination, and network processors are employed to handle transmission of data into and out of data switches. [0012] FIG. 1 is a block diagram illustration of a conventional network processor in which the present invention may be applied. The network processor, which is generally indicated by reference numeral 10, may be constituted by a number of components mounted on a card or "blade". Within a data communication network, a considerable number of blades containing network processors may be interposed between a data switch and a data network. [0013] The network processor 10 includes data flow chips 12 and 14. The first data flow chip 12 is connected to a data switch 15 (shown in phantom) via first switch ports 16, and is connected to a data network 17 (shown in phantom) via first network ports 18. The first data flow chip 12 is positioned on the ingress side of the switch 15 and handles data frames that are inbound to the switch 15. [0014] The second data flow chip 14 is connected to the switch 15 via second switch ports 20 and is connected to the data network 17 via second network ports 22. The second data flow chip 14 is positioned on the egress side of the switch 15 and handles data frames that are outbound from the switch 15. [0015] As shown in FIG. 1, a first data buffer 24 is coupled to the first data flow chip 12. The first data buffer 24 stores inbound data frames pending transmission of the inbound data frames to the switch 15. A second data buffer 26 is coupled to the second data flow chip 14, and stores outbound data frames pending transmission of the outbound data frames to the data network 17. [0016] The network processor 10 also includes a first processor chip 28 coupled to the first data flow chip 12. The first processor chip 28 supervises operation of the first data flow chip 12 and may include multiple processors. A second processor chip 30 is coupled to the second data flow chip 14, supervises operation of the second data flow chip 14 and may include multiple processors. [0017] A control signal path 32 couples an output terminal of second data flow chip 14 to an input terminal of first data flow chip 12 (e.g., to allow transmission of data frames therebetween). [0018] The network processor 10 further includes a first scheduler chip 34 coupled to the first data flow chip 12. The first scheduler chip 34 manages the sequence in which inbound data frames are transmitted to the switch 15 via first switch ports 16. A first memory 36 such as a fast SRAM is coupled to the first scheduler chip 34 (e.g., for storing data frame pointers and flow control information as described further below). The first memory 36 may be, for example, a QDR (quad data rate) SRAM. [0019] A second scheduler chip 38 is coupled to the second data flow chip 14. The second scheduler chip 38 manages the sequence in which data frames are output from the second network ports 22 of the second data flow chip 14. Coupled to the second scheduler chip 38 are at least one and possibly two memories (e.g., fast SRAMs 40) for storing data frame pointers and flow control information. The memories 40 may, like the first memory 36, be QDRs. The additional memory 40 on the egress side of the network processor 10 may be needed because of a larger number of flows output through the second network ports 22 than through the first switch ports 16. [0020] FIG. 2 schematically illustrates conventional queuing arrangements that may be provided for a data flow chip/scheduler pair (either the first data flow chip 12 and the first scheduler chip 34 or the second data flow chip 14 and the second scheduler chip 38) of the network processor 10 of FIG. 1. In the particular example illustrated in FIG. 2, the first data flow chip 12 and the first scheduler chip 34 are illustrated, but a very similar queuing arrangement may be provided in connection with the second data flow chip 14 and the second scheduler chip 38. In the queuing arrangement for the first data flow chip 12 and the first scheduler chip 34, incoming data frames (from data network 17) are buffered in the input data buffer 24 associated with the first data flow chip 12 (FIG. 1). Each data frame is associated with a data flow or "flow". As is familiar to those who are skilled in the art, a "flow" represents a one-way connection between a source and a destination. [0021] Flows with which the incoming data frames are associated are enqueued in a scheduling queue 42 maintained in the first scheduler chip 34. The scheduling queue 42 defines a sequence in which the flows enqueued therein are to be serviced. The particular scheduling queue 42 of interest in connection with the present invention is a weighted fair queue which arbitrates among flows entitled to a "best effort" or "available bandwidth" Quality of Service (QoS). Continue reading... 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