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Wafer holder and method of holding a waferRelated Patent Categories: Semiconductor Device Manufacturing: Process, Chemical EtchingWafer holder and method of holding a wafer description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060281314, Wafer holder and method of holding a wafer. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001] The present application claims the priority of JP 2005-50064, filed in Japan on Feb. 25, 2005, the entire contents of which are incorporated herein by reference. FIELD OF THE INVENTION [0002] The present invention relates generally to a wafer holder and a method of holding a wafer, and in one aspect, the present invention relates to a wafer holder including wafer stage and a wafer stage outer-ring surrounding the wafer stage and provided in a plasma processing chamber such as a plasma processing chamber of an angled sputtering system. BACKGROUND OF THE INVENTION [0003] In fabricating integrated circuits, forming many different films on Si wafers by physical vapor deposition (PVD) is one of the common steps. Currently there are many different configurations and methods in performing PVD process, for example ionized PVD and long-through-sputtering. [0004] An angled sputtering is one of the PVD techniques where the target and wafer are placed not in parallel but with an angle. See JP 2002-194540. The advantage of this sputtering technique is it yields extremely uniform film. The disadvantage of this technique is that edge exclusion (hereinafter referred to "EE") for a film deposited on a wafer surface trades-off with film wrapping around the wafer edge. This is explained in details with reference to FIGS. 5 to 9 of the present application. [0005] A cross sectional diagram of an example of an angled sputtering system and a conventional wafer holder 50 adopted in the angled sputtering system are shown in FIGS. 5 to 8, respectively. The process chamber of this angled sputtering system has a vacuum port 66 and a wafer in/out port 67. The wafer holder 50 is comprised of wafer stage 51, insulating shield 52 surrounding wafer stage 51, metallic outer-shield 53, shaft 54 supporting the metallic outer-shield 53 and a masking outer-ring 55. The masking outer-ring 55 is attached to several metallic or insulating pins 56, usually 3 (three) metallic or insulating pins, in order to move the masking outer-ring 55 up and down. In FIG. 5, the insulating pins 56, 56 are moved up and down by lift-up pin controller 65. [0006] While the wafer 57 is loaded on to the wafer stage 51, the masking outer-ring 55 is raised up. After the wafer 57 is placed on the wafer stage 51, the masking outer-ring 55 is lowered until the separation between the upper surface of wafer 57 and the backside surface of the masking outer-ring 55 is less than 1 mm. Usually, the masking outer-ring 55 is not lowered until the backside surface of it touches the wafer 57, since it causes a generation of particles on the surface of wafer 57 by the fraction. The masking outer-ring 55 covers a few millimeters, usually less than 5 mm, on the wafer edge 62 (FIG. 7). This covered region is denoted by X (denoted by numeral 63) in FIGS. 7 and 8. [0007] The configuration of other conventional and commonly used wafer holder is given in FIG. 9 wherein there is no masking outer-ring. Problems to be Solved [0008] FIGS. 7 and 8 show the film deposition characteristics at the most close and most far positions on wafer 57 with respect to the target 58 when the film is deposited by the angled sputtering system shown in FIG. 5. These positions are labeled as A (denoted by numeral 59) and B (denoted by numeral 60) in FIG. 6. At position A (59), some atoms 61 from the sputtering target 58 go through the space between the wafer 57 and the masking outer-ring 55, as shown in FIG. 7, and deposit at the wafer edge 62. At position B (60), the shadow due to the existence of masking outer-ring 55 is larger than X (63), as shown in FIG. 8, since atoms 61 are coming in at an angle. This shadowed region is defined as Y (denoted by numeral 64) in FIG. 8. Films are not deposited in this shadowed region Y (64) at position B (60). Because of these different deposition characteristics at positions A (59) and B (60), the film is non-uniform at the wafer edge 62. Further this non-uniform region is larger than X (63), which is the region that is physically covered by the masking outer-ring 55. [0009] This non-uniform region may be extended up to y (64). For example, when X (63) becomes 2 mm, Y (64) may be as large as 10 mm resulting in a 10 mm edge exclusion (EE). Although it is possible to reduce the EE by shortening X (63), it is difficult to get at least 5 mm EE as far as masking outer-ring 55 is used. This is a considerably larger value compared to the semiconductor industry's requirement of small edge exclusion (EE), such as less than 2 mm edge exclusion (EE). [0010] If a masking outer-ring 55 is not adopted in the wafer holder as shown in FIG. 9, films deposit all over the wafer resulting in almost 0 EE. However, in this condition films wrap around the wafer edge and deposit on wafer stage 51. This contaminates the backside of the wafer 57. Film deposition on the wafer stage 51 is an undesirable feature since that film gets thicker and thicker with time. This accelerates and increases the wafer backside contamination with the increase of process time. Means for Solving the Problem [0011] In order to solve the above-described problems, one aspect of the present invention provides a wafer holder including a wafer stage and a wafer stage outer-ring surrounding the wafer stage wherein the wafer stage has a diameter smaller than the diameter loaded on the wafer stage, the inner diameter at the upper side of the outer-ring is larger than the diameter of wafer loaded on the wafer stage, and the upper surface of the wafer stage outer-ring lies above the upper surface of wafer loaded on the wafer stage. [0012] According to such a wafer holder, since the inner diameter at the upper side of the wafer stage outer-ring is slightly larger than the diameter of wafer loaded on the wafer stage and the wafer stage has a diameter smaller than the diameter of the wafer loaded on the wafer stage so that a narrow space is formed between the outer peripheral of the wafer and the inner peripheral wall of the wafer stage outer-ring. Thereby, it is possible to reduce edge exclusion (EE), for example it is possible to reduce edge exclusion (EE) to less than 2 mm by the before described slightly larger inner diameter at the upper side of the wafer stage outer-ring. And it is possible to reduce the probability in contaminating the backside of wafer with depositing material by the existence of the narrow space between the outer peripheral of wafer and the inner peripheral wall of the wafer stage outer-ring. [0013] Also, since the upper surface of wafer stage outer-ring lies slightly above the upper surface of wafer loaded on the wafer stage, the wafer backside contamination, which is caused when the wafer holder as shown in FIG. 9 is used, can be minimized. [0014] In the before described wafer holder, the wafer holder outer-ring may further have a different inner diameter at the lower side. That is to say, in the above-described wafer holder, the wafer stage outer-ring may be modified to have two different inner diameters, the one is the inner diameter at the upper side of the outer-ring and the other is the inner diameter at the lower side of the outer-ring. The above-described inner diameter at the upper side of the wafer stage outer-ring is slightly larger than the diameter of wafer loaded on the wafer stage as described above, while the inner diameter at the lower side of the wafer stage outer-ring is slightly smaller than the diameter of wafer but slightly larger than the diameter of the wafer stage. [0015] According to this configuration, the above-described narrow space between the outer peripheral wall of the wafer and the inner peripheral wall of the wafer stage outer-ring continues and extends to the narrow space between the outer peripheral wall of the wafer stage and the inner peripheral wall of the wafer stage outer-ring. [0016] Therefore, it is possible to effectively reduce the probability in contaminating the backside surface of wafer with depositing material by the existence of the narrow space between the outer peripheral of wafer and the inner peripheral wall of the wafer stage outer-ring and between the outer peripheral wall of the wafer stage and the inner peripheral wall of the wafer stage outer-ring. [0017] In the above-described wafer holder wherein the wafer stage outer-ring has two different inner diameters, the one is the inner diameter at the upper side of the outer-ring and the other is the inner diameter at the lower side of the outer-ring, the wafer stage outer-ring may be modified to have a horizontal plane formed between one inner peripheral wall defining the inner diameter at the upper side of outer-ring and the other inner peripheral wall defining the inner diameter at lower side of outer-ring, and the horizontal plane lies below the backside surface of the wafer loaded on the wafer stage without contacting the backside surface of wafer. [0018] According to this configuration, it is possible to reduce the probability of contaminating the backside of wafer with depositing material by the existence of the narrow gap between the backside surface of a wafer loaded on the wafer stage and the upper surface of the above-described horizontal plane. [0019] In any of the above-described wafer holders, the wafer stage may be modified to be made of two or more separate pieces for adjusting the height of the wafer stage thereby adjusting the space between the upper surface of the wafer stage and the upper surface of the wafer stage outer-ring. Continue reading about Wafer holder and method of holding a wafer... Full patent description for Wafer holder and method of holding a wafer Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Wafer holder and method of holding a wafer patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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