Wafer guide in wafer cleaning apparatus

Abstract: A wafer guide in a wafer cleaning apparatus comprises of a lower panel portion. The wafer guide also comprises of a plurality of wafer supporting panel portions, the plurality of wafer supporting panel portions being configured to protrude from at least one side of the lower panel portion and support a wafer. The wafer guide also comprises of a plurality of slot portions, the plurality of slot portions being configured to form at upper ends of the plurality of wafer supporting panel portions and hold the wafer by forming contact with at least a portion of a wafer edge area without forming contact with a wafer cell area. (end of abstract)

Agent: Volentine Francos, & Whitt PLLC - Reston, VA, US
Inventor: Hu-Won Seo
USPTO Applicaton #: #20070125726 - Class: 211041180 (USPTO)
Related Patent Categories: Supports: Racks, Special Article, Platelike, Semiconductor Wafer

Wafer guide in wafer cleaning apparatus description/claims

The Patent Description & Claims data below is from USPTO Patent Application 20070125726, Wafer guide in wafer cleaning apparatus.

Brief Patent Description - Full Patent Description - Patent Application Claims

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to semiconductor device manufacturing equipment and, more particularly, to a wafer cleaning apparatus which removes impurities on the surface of a wafer.

[0003] This application claims the benefit of Korean Patent Application No. 10-2005-0116945, filed Dec. 2, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

[0004] 2. Description of the Related Art

[0005] Semiconductor devices are manufactured using various processes such as, for example, an impurity ion implantation process, a thin film deposition process, an etching process, and a chemical mechanical polishing (CMP) process. The impurity ion implantation process implants 3B or 5B group impurity ions into a semiconductor. The thin film deposition process forms one or more layers on a semiconductor substrate. The etching process patterns the one or more layers formed on the semiconductor substrate in a predetermined pattern. The CMP process levels the wafer surface by polishing the wafer surface after the deposition of a layer such as an interlayer insulating layer on the wafer.

[0006] While the above-mentioned processes may be used to fabricate semiconductor devices, these processes also generate contaminants. These contaminants may adhere to the surface of the semiconductor wafer during the manufacturing of the semiconductor device. There is therefore a need for a wafer cleaning process to clean the wafer periodically during the semiconductor manufacturing process.

[0007] Generally, during a wafer cleaning process, a wafer to be cleaned is held in a wafer vessel which is also known as a wafer guide. A wafer guide is disclosed in Korean Patent No.10-0512183 and U.S. Pat. No. 6,235,147. The wafer guide includes slots for holding the wafer. Furthermore, the wafers held in the slot portions are immersed into chemical bathes for cleaning, and are moved to a drying portion to dry the wafers.

[0008] When wafers held in a wafer guide are moved from one spot to another, the movement of the wafer guide may produce vibrations that may damage the wafers. In order to protect the wafers from vibrations, the wafers may be inserted deep into slots of the wafer guide. The deep insertion of the wafers in the slots of the wafer guide may increase the stability of the held wafers thus protecting the wafers from vibrations.

[0009] However, inserting wafers deep into the slots of the wafer guide may cause problems. For example, studies show that as the wafers are inserted deep into the slots, the amount of wafer surface coming in contact with the slots increases. This increase in the contact surface between the wafer and the slot may lead to a greater possibility of the wafer being damaged. The damage to the wafer may occur because of scratches forming on the wafer surface in contact with the slot. Furthermore, as a cleaning solution flows through the scratches, additional defects may also be formed in the wafer.

[0010] The problems due to scratches on a wafer are exacerbated when the integration density of a semiconductor device is increased. Specifically, when the integration density of semiconductors is increased, there is a tendency to position cells closer to the edge of a wafer so as to increase the number of cells per wafer. Thus, there are now more cells on a wafer surface that is directly in contact with a slot holding the wafer. This design issue coupled with the problem of an increase in the contact surface between a slot and a wafer may increase the number of scratch related defects in semiconductor wafers. These problems may decrease the production yield of the semiconductor manufacturing process.

[0011] In a conventional wafer guide, slot portions for holding wafers are formed at positions such that the slot portions may hold the wafer at the center of a wafer flat zone. Thus, for example, when wafers are loaded in a conventional wafer guide such that the wafer flat zone is oriented towards the bottom, an area that is 4.4 mm from the wafer edge area may be in contact with the slot portions of the wafer guide. On the other hand, when wafers are loaded in a conventional wafer guide such that the wafer flat zone is oriented towards the top, an area that is 6 mm from the wafer edge area may be in contact with the slot portions of the wafer guide. FIGS. 1 through 3 show exemplary intervals between a wafer edge area and a wafer cell area in currently produced wafers.

[0012] FIG. 1 illustrates a first wafer in which the distance between a wafer edge area 10 and a wafer cell area 12 is 5 mm. FIG. 2 illustrates a second wafer in which the distance between a wafer edge area 20 and a wafer cell area 22 is 4 mm. FIG. 3 illustrates a third wafer in which the distance between a wafer edge area 30 and a wafer cell area 32 is 3.5 mm.

[0013] Under certain conditions, when wafers of FIGS. 1 through 3 are loaded in the conventional wafer guide, scratches may occur in the wafer cell areas. For example, when the first wafer in which the distance between a wafer edge area 10 and a wafer cell area 12 is 5 mm, is loaded such that the wafer flat zone is oriented towards the bottom, no scratches occur in the wafer cell area 12. However, when the first wafer is loaded such that the wafer flat zone is oriented towards the top, scratches occur in the wafer cell area 12 because the length of contact between the slot portion and the wafer surface (6 mm) exceeds the distance of 5 mm between the wafer edge area 10 and the wafer cell area 12. Furthermore, in the second wafer (in which the distance between the wafer edge area 20 and the wafer cell area 22 is 4 mm) and the third wafer (in which the distance between the wafer edge area 30 and the wafer cell area 32 is 3.5 mm,) the length of contact between the slot portion and the wafer surface exceeds the distance between the wafer edge area and the wafer cell area, regardless of the direction of loading the wafers (i.e., regardless of whether the wafer flat zone is oriented towards the bottom or top.) Therefore, it is likely that scratches will occur in the wafer cell area leading to defects in the wafer and to a decrease in the production yield of the semiconductor manufacturing process.

[0014] FIGS. 4A and 4B depict wafer cell areas that include scratches. Referring to FIGS. 4A and 4B, each wafer cell area 42 is separated from other cell areas by a scribe line 40. Furthermore, each cell area 42 includes scratches 44 that are formed because of the contact between a slot portion and the wafer cell area 42.

[0015] FIGS. 5A and 5B depict a wafer cell area having defects caused by fluids flowing along the scratches 44. Specifically, when a wafer with scratches 44 in the wafer cell area (as shown in FIGS. 4A and 4B) is immersed into a chemical bath, a cleaning solution flows along the scratch tracks. As a result, a defect 46 caused by the movement of fluid along the scratches 44 occurs. Defect 46 may include, for example, the removal of a layer such as poly-silicon that functions as a storage electrode, from the wafer cell area 42. Such a defect caused by the movement of fluids through the wafer cell area may also result in a decrease in the production yield of the semiconductor manufacturing process.

[0016] The present disclosure is directed towards overcoming one or more shortcomings of the conventional wafer guide apparatus.

SUMMARY OF THE INVENTION

[0017] One aspect of the present disclosure includes a wafer guide in a wafer cleaning apparatus. The wafer guide comprises of a lower panel portion. The wafer guide also comprises of a plurality of wafer supporting panel portions, the plurality of wafer supporting panel portions being configured to protrude from at least one side of the lower panel portion and support a wafer. The wafer guide also comprises of a plurality of slot portions, the plurality of slot portions being configured to form at upper ends of the plurality of wafer supporting panel portions and hold the wafer by forming contact with at least a portion of a wafer edge area without forming contact with a wafer cell area.

[0018] Another aspect of the present disclosure includes a wafer guide in a wafer cleaning apparatus. The wafer guide comprises of a lower panel portion. The wafer guide also comprises of a pair of outer wafer supporting panel portions, formed at right and left side edges of the lower panel portion, supporting a wafer. The wafer guide also comprises of a pair of inner wafer supporting panel portions formed between the pair of outer wafer supporting panel portions and spaced apart from each other by a distance exceeding a length of a wafer flat zone, supporting the wafer. The wafer guide also comprises of a plurality of slot portions, formed at upper ends of the pair of outer wafer supporting panel portions and the pair of inner wafer supporting panel portions, holding the wafer by forming contact with at least a portion of a wafer edge area without forming contact with a wafer cell area.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail preferred embodiments thereof with reference to the attached drawings in which:

[0020] FIGS. 1 through 3 illustrate the distance between a wafer cell area and a wafer edge area in exemplary wafers, respectively;

[0021] FIGS. 4A and 4B depict a wafer cell area including scratches;

Brief Patent Description - Full Patent Description - Patent Application Claims
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