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Voltage translator circuits using capacitive techniquesUSPTO Application #: 20070159859Title: Voltage translator circuits using capacitive techniques Abstract: A voltage translator circuit and a method for operating the same. The voltage translator circuit includes (a) an input node, an output node, and a ground node; (b) a voltage divider circuit including a first and second resistors coupled in series between the input node and the ground node; (c) a start voltage circuit coupled to a first voltage and to the input node; (d) a transfer circuit coupled to the output node; and (e) a capacitive circuit having a first and second capacitive nodes. The first capacitive node is coupled to the voltage divider circuit. The second capacitive node is coupled (i) to the first voltage via the start voltage circuit, and (ii) to the output node via the transfer circuit. In response to the input node changing towards the first voltage, the start voltage circuit is capable of disconnecting the second capacitive node from the first voltage. (end of abstract)
USPTO Applicaton #: 20070159859 - Class: 363039000 (USPTO)
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