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  Voltage multiplier circuit including a control circuit providing dynamic output voltage controlUSPTO Application #: 20060290411Title: Voltage multiplier circuit including a control circuit providing dynamic output voltage control Abstract: A voltage multiplier circuit includes a control circuit and a first voltage multiplier stage. The control circuit receives a power supply voltage and a reference voltage and provides a first output voltage being the difference between a first selected voltage and the power supply voltage where the first selected voltage is a function of the reference voltage and is independent of variations in the power supply voltage. The first voltage multiplier stage receives the first output voltage and a clock voltage signal having a clock voltage value and provides a second output voltage being the sum of the first output voltage and the clock voltage value. When the clock voltage value is equal to the power supply voltage, the second output voltage of the first voltage multiplier stage is the first selected voltage independent of any power supply voltage variations. (end of abstract)
Agent: Patent Law Group LLP - San Jose, CA, US Inventors: Paul Smith, John Shaw USPTO Applicaton #: 20060290411 - Class: 327536000 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20060290411. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The invention relates to voltage multiplier circuits and, in particular, to a voltage multiplier circuit incorporating a control circuit for providing dynamic control of the output voltage. DESCRIPTION OF THE RELATED ART [0002] Voltage multiplier circuits for generating operational voltages higher than a power supply voltage provided from an external source are known. Typically, a voltage multiplier circuit receives two fixed input voltages, one of the input voltages being the power supply voltage and the other being a clock voltage. The voltage multiplier provides an output voltage being the sum of its two input voltages. When the two fixed input voltages are the same, the voltage multiplier circuit generates an output voltage that is N times the power supply voltage where N is the number of voltage multiplication stages. In general, a voltage multiplier circuit may include two or more voltage multiplier stages to provide an output voltage that is two or more times the input power supply voltage. Exemplary types of voltage multiplier circuits include voltage multiplier circuits and voltage doubler circuits. [0003] FIG. 1 is a block diagram of a conventional two-stage voltage multiplier circuit. Referring to FIG. 1, voltage multiplier circuit 1 includes a first voltage multiplier stage 10 (Voltage Multiplier Stage 1) and a second voltage multiplier stage 15 (Voltage Multiplier Stage 2). Voltage multiplier circuit 1 receives a power supply voltage V.sub.DD as the first input voltage and a clock signal and its inverse, denoted as a clock voltage signal V.sub.CLK and its inverse V.sub.CLK\, as the second input voltage. At first voltage multiplier stage 10, an output voltage V.sub.OUT1 is generated where V.sub.OUT1=V.sub.DD+.DELTA.V. The output voltage V.sub.OUT1 is coupled as an input voltage to second voltage multiplier stage 15. Second voltage multiplier stage 15 adds another voltage .DELTA.V to its input voltage and provides an output voltage V.sub.OUT2 being V.sub.OUT2=V.sub.DD+2.DELTA.V. The .DELTA.V voltage represents a voltage increment introduced by each voltage multiplier stage and is usually equal to the second input voltage, that is, the clock voltage signal V.sub.CLK. When voltage V.sub.CLK=.DELTA.V=V.sub.DD, voltage doubling is realized at first voltage multiplier stage 10. That is, V.sub.OUT1=V.sub.DD+.DELTA.V=2V.sub.DD. The final output voltage of voltage multiplier circuit 1 is voltage V.sub.OUT2=V.sub.DD+2.DELTA.V=3V.sub.DD. By incorporating multiple voltage multiplier stages, a final output voltage being N times the power supply voltage can be obtained. [0004] One example of a voltage multiplier circuit is a voltage double circuit described in an article entitled "A New High efficiency CMOS Voltage Doubler," by Pierre Favrat et al., IEEE Custom Integrated Circuits Conference, 1997, pages 259 to 262. Favrat et al. describes using a charge pump cell to make a voltage doubler using improved serial switches. The voltage double circuit architecture allows the voltage doubler circuit to achieve very high efficiency, particularly for heavy capacitive loads. [0005] In the conventional voltage multiplier circuits, the output voltage of each voltage multiplication stage is a function of the input power supply voltage. Therefore, the output voltage of each stage will vary in accordance with variations in the input power supply voltage. In some applications, such variations in the voltage multiplier circuit output voltage is not desired, particularly when the voltage multiplier circuit is used to drive MOS devices where precision in the gate drive voltages is critical. [0006] Therefore, a voltage multiplier circuit capable of providing an output voltage that can be made stable over input voltage variations is desired. SUMMARY OF THE INVENTION [0007] According to one embodiment of the present invention, a voltage multiplier circuit includes a control circuit and a first voltage multiplier stage. The control circuit has a first input terminal coupled to receive a power supply voltage, a second input terminal coupled to receive a reference voltage. The control circuit provides a first output voltage having a voltage value being the difference between a first selected voltage and the power supply voltage where the first selected voltage is a function of the reference voltage and is independent of variations in the power supply voltage. The first voltage multiplier stage has a first input terminal receiving the first output voltage of the control circuit and second and third input terminals receiving a clock voltage signal and its inverse where the clock voltage signal having a clock voltage value. The first voltage multiplier stage provides a second output voltage being the sum of the first output voltage and the clock voltage value. [0008] In one embodiment, when the clock voltage value is equal to the power supply voltage, the second output voltage is equal to the first selected voltage which is a function of the reference voltage and is independent of variations in the power supply voltage. [0009] According to one embodiment of the present invention, a voltage multiplier circuit includes a control circuit, a first voltage multiplier stage and a second voltage multiplier stage. The control circuit has a first input terminal coupled to receive a first power supply voltage and a second input terminal coupled to receive a reference voltage. The control circuit provides a first output voltage having a voltage value being the difference between a first selected voltage and the first power supply voltage where the first selected voltage is a function of the reference voltage and is independent of variations in the first power supply voltage. The first voltage multiplier stage has a first input terminal receiving the first output voltage of the control circuit and second and third input terminals receiving a first clock voltage signal and its inverse where the first clock voltage signal has a first clock voltage value. The first voltage multiplier stage provides a second output voltage being the sum of the first output voltage and the first clock voltage value. The second voltage multiplier stage has a first input terminal receiving the second output voltage of the first voltage multiplier stage and second and third input terminals receiving a second clock voltage signal and its inverse where the second clock signal has a second clock voltage value. The second voltage multiplier stage provides a third output voltage being the sum of the second output voltage and the second clock voltage value. [0010] In one embodiment, the first clock voltage value is equal to the first power supply voltage and the second clock voltage value is equal to a second power supply voltage, the second output voltage is equal to the first selected voltage and the third output voltage has a voltage value equal to the sum of the first selected voltage and the second power supply voltage. [0011] According to another aspect of the present invention, a method of generating an output voltage using a power supply voltage, a reference voltage, and a first clock voltage signal having a first clock voltage value includes generating a first voltage having a voltage value being the difference between a first selected voltage and the power supply voltage where the first selected voltage is a function of the reference voltage and is independent of variations in the power supply voltage, generating a second voltage using a first voltage multiplier stage where the first voltage multiplier stage receives the first clock voltage signal and the second voltage is the sum of the first voltage and the first clock voltage value. The second voltage is the output voltage. [0012] According to yet another aspect of the present invention, a method of generating a gate drive voltage for an NMOS transistor where the NMOS transistor has a drain terminal coupled to a first power supply voltage and a source terminal coupled to a load includes generating a first voltage having a voltage value being the difference between a first selected voltage and a second power supply voltage where the first selected voltage is a function of a reference voltage and is independent of variations in the second power supply voltage, generating a second voltage using a first voltage multiplier stage where the first voltage multiplier stage receives a first clock voltage signal having a first clock voltage value equal to the second power supply voltage and the second voltage is the sum of the first voltage and the first clock voltage value and therefore is equal to the first selected voltage, generating a third voltage using a second voltage multiplier stage where the second voltage multiplier stage receives a second clock voltage signal having a second clock voltage value equal to the first power supply voltage. The third voltage is the sum of the second voltage and the second clock voltage value and therefore is equal to the sum of the first selected voltage and the first power supply voltage. Finally, the method includes applying the third voltage as the gate drive voltage for the NMOS transistor. The application of the third voltage as the gate drive voltage resulting in a gate-to-drain voltage at the NMOS transistor having a voltage value equal to the first selected voltage and being substantially constant over variations of the first power supply voltage. [0013] The present invention is better understood upon consideration of the detailed description below and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0014] FIG. 1 is a block diagram of a conventional two-stage voltage multiplier circuit where each stage operates as a voltage doubler. [0015] FIG. 2 is a circuit diagram of a two-stage voltage multiplier circuit incorporating a drive voltage generator according to one embodiment of the present invention. [0016] FIG. 3 is a circuit diagram of the drive voltage generator circuit according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0017] In accordance with the principles of the present invention, a voltage multiplier circuit incorporates a control circuit for providing dynamic control of the voltage multiplier output voltage. Specifically, the voltage multiplier output voltage is controlled through the dynamic control of a driving voltage coupled to drive the one or more voltage multiplier stages of the voltage multiplier circuit. In one embodiment, the control circuit controls the output voltage of a multi-stage voltage multiplier circuit through the continuous control of the input voltage to the first voltage multiplier stage. In this manner, the output voltage of the first voltage multiplier stage is made independent of the variations of the input power supply voltage VDD and the output voltage of the remaining voltage multiplier stages of the voltage multiplier circuit is the sum of this Vdd-independent voltage and a multiple of the power supply voltage. [0018] More specifically, the voltage multiplier circuit of the present invention incorporates a control circuit for generating a drive voltage V.sub.DRV to be used as the input voltage to the one or more voltage multiplier stages of the voltage multiplier circuit. The control circuit receives the power supply voltage V.sub.DD as a first input voltage and a reference voltage V.sub.REF as a second input voltage. The control circuit operates to generate the drive voltage V.sub.DRV as a function of the reference voltage V.sub.REF and the power supply voltage V.sub.DD. When the drive voltage V.sub.DRV is coupled to drive the voltage multiplier circuit and when the first voltage multiplier stage receives a clock voltage that is equal to the power supply voltage, the output voltage of the first voltage multiplier stage of the voltage multiplier circuit will become independent of variations in the power supply voltage V.sub.DD. [0019] By using the control circuit to provide dynamic control of the drive voltage to the voltage multiplier stages, the voltage multiplier circuit of the present invention eliminates the need for any feedback control circuitry for controlling the output voltage. Thus, no current is drawn from the voltage multiplier output terminal, allowing the output voltage to maintain maximum voltage amplification efficiency. Continue reading... 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