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Via reactive ion etching processRelated Patent Categories: Semiconductor Device Manufacturing: Process, Chemical Etching, Vapor Phase Etching (i.e., Dry Etching)Via reactive ion etching process description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060105572, Via reactive ion etching process. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD [0001] The present invention relates generally to semiconductor fabrication, and more particularly, to a via reactive ion etching process. RELATED ART [0002] In the semiconductor industry, reactive ion etching (RIE) is used to open pathways for circuitry within a semiconductor chip. One structure formed using RIE is a via, which electrically connects conductors within different layers. RIE is a variation of plasma (gas) etching in which a semiconductor wafer is placed on a radio frequency (RF) powered electrode, and etching species are extracted and accelerated from the plasma toward the surface to be etched. A chemical etching reaction occurs which removes parts of the surface. RIE is one of the most common etching techniques in semiconductor manufacturing. [0003] Referring to FIG. 1, a semiconductor structure 10 including large-via pad dielectric layers 12 prior to etching is shown. Structure 10 includes a conductor level 14 including a dielectric layer 16 (e.g., of silicon dioxide SiO.sub.2) surrounding conductor 18 (e.g., of copper Cu); a cap layer 20 (e.g., of silicon nitride Si.sub.3N.sub.4) atop conductor level 14; a dielectric layer 22 (e.g., of silicon dioxide SiO.sub.2); another dielectric layer 24 (e.g., of silicon nitride Si.sub.3N.sub.4); and a patterned photoresist 26. A typical large-via RIE process is conducted in a single plasma chamber capable of two RF settings, e.g., 2 MHz and 27 MHz. One conventional RIE process includes the following steps: etching of dielectric layer 24, etching dielectric layer 22 and stopping on cap layer 20 so as to not expose conductor 18, stripping photoresist 26, etching cap layer 20 to expose conductor 18, and finally, performing a nitrogen-hydrogen (N.sub.2H.sub.2) plasma chemistry (ash) to remove residual RIE polymers from conductor 18. More specifically, dielectric layer 22 etching may occur, for example, using the following conditions: 80 mTorr (mT) of pressure, an RF energy of 1800 watts (W) at 27 MHz and 600 W at 2 MHz, and a gas flow of 10 standard cubic centimeters per minute (sccm) of tetrafluoro methane (CF.sub.4), 220 sccm of carbon monoxide (CO) and 400 sccm of argon (Ar), resulting in an approximately 45 .ANG.ngstrom/second (.ANG./s) etch rate. The photoresist strip may use, for example, the following conditions in two stages including: 800 mT of pressure, an RF energy of 800 W at 27 MHz, and a gas flow of 1000 sccm of oxygen (O.sub.2), followed by 450 mT of pressure, 1200 W at 27 MHz and 200 W at 2 MHz, and a gas flow including 1000 sccm of oxygen (O.sub.2). The dielectric layer 20 etch may occur, for example, using the following conditions: 150 mT of pressure, an RF energy of 1000 W at 2 MHz and 1500 W at 27 MHz, and a gas flow of 100 sccm of oxygen (O.sub.2), 190 sccm tetrafluoro methane (CF.sub.4) and 400 sccm argon (Ar). The ash step may occur, for example, using the following conditions: 200 mT of pressure, an RF energy of 1200 W at 27 MHz, and a gas flow including 600 sccm nitrogen (N.sub.2) and 200 sccm hydrogen (H.sub.2). [0004] The conventional RIE process suffers from a number of problems. First, conventional RIE techniques suffer from a low etch rate because the gas flow for the process is typically centered at the minimum operating range of a mass flow controller, which reduces yields. Second, typical plasma processes are susceptible to gas flow fluctuations, e.g., within a process chamber or between different equipment, which results in widely varying etch rates. Finally, with the movement of wafer fabrication facilities from the conventional 200 mm wafer to the larger 300 mm wafer, process cycle times of conventional RIE processes are considered too long. For example, large via (LV) pads are the final level of 300 mm wafer fabrication connecting the transistors to the wire bonds for the final electrical test. The via RIE process for LV pads typically takes approximately 5 minutes per wafer, which makes this step a target for improvement. [0005] In view of the foregoing, there is a need in the art for an improved via RIE process that does not suffer from the problems of the related art. SUMMARY OF THE INVENTION [0006] The invention includes methods of etching a dielectric layer and a cap layer over a conductor level to open a via to the conductor. The methods include the provision of tetrafluoro methane (CF.sub.4) in a photoresist strip. In addition, the methods may provide an increased amount of tetrafluoro methane (CF.sub.4) in a dielectric layer etch, and trifluoro methane (CHF.sub.3) in a cap layer etch. The invention provides higher yield, more predictable etch rates, faster processing, and removes the need for an ash step. [0007] A first aspect of the invention is directed to a method of etching a dielectric layer and a cap layer over a conductor level to open a via to the conductor, a pattern for the via being provided by a photoresist, the method comprising the steps of: etching the via through the dielectric layer; stripping the photoresist using a plasma chemistry including tetrafluoro methane (CF.sub.4); and etching the cap layer to open the via to the conductor. [0008] A second aspect of the invention includes a method of etching a dielectric layer and a cap layer over a conductor level to open a via to the conductor, a pattern for the via being provided by a photoresist, the method consisting of the steps of: etching the via through the dielectric layer; stripping the photoresist using a plasma chemistry including tetrafluoro methane (CF.sub.4); and etching the cap layer to open the via to the conductor. [0009] A third aspect of the invention relates to a method of etching a dielectric layer and a cap layer over a conductor level to open a via to the conductor, a pattern for the via being provided by a photoresist, the method comprising of the steps of: etching the via through the dielectric layer using approximately 80 mT of pressure, an RF energy of approximately 1200 W at 27 MHz and approximately 2700 W at 2 MHz, and a gas flow including tetrafluoro methane (CF.sub.4) and carbon monoxide (CO) in a gas flow ratio of no less than approximately 0.104 and no greater than approximately 0.2; stripping the photoresist using a plasma chemistry including tetrafluoro methane (CF.sub.4) using a gas flow of no less than approximately 7 standard cubic centimeters per minute (sccm) and no greater than approximately 15 sccm of the tetrafluoro methane (CF.sub.4); and etching the cap layer to open the via to the conductor using approximately 150 mT of pressure, an RF energy of approximately 1000 W at 2 MHz and approximately 1500 W at 27 MHz, and a gas flow including tetrafluoro methane (CF.sub.4) and trifluoro methane (CHF.sub.3) in a gas flow ratio of no less than approximately 2.33 and no greater than approximately 3.96. [0010] A fourth aspect of the invention relates to a method of etching a first dielectric layer, a second dielectric layer and a cap layer over a conductor level to open a via to the conductor, a pattern for the via being provided by a photoresist, the method comprising the steps of: etching the via through the first dielectric layer; etching the via through the second dielectric layer; stripping the photoresist using a plasma chemistry including tetrafluoro methane (CF.sub.4); and etching the cap layer to open the via to the conductor. [0011] The foregoing and other features of the invention will be apparent from the following more particular description of embodiments of the invention. BRIEF DESCRIPTION OF THE DRAWINGS [0012] The embodiments of this invention will be described in detail, with reference to the following figures, wherein like designations denote like elements, and wherein: [0013] FIG. 1 shows a conventional semiconductor structure including large-via pad dielectric layers prior to etching. [0014] FIGS. 2-5 show a method of etching a via according to the invention. [0015] FIG. 6 shows a semiconductor structure illustrating some of the problems solved by the invention. DETAILED DESCRIPTION OF THE INVENTION [0016] With reference to the accompanying drawings, FIG. 2-5 show a method of etching a dielectric layer and a cap layer over a conductor level to open a via to the conductor according to the invention. The method modifies the conventional process such that the process results in improved yields, more predictable etch rates and greatly reduced processing time. The process begins with a conventional semiconductor structure 10 including large-via pad dielectric layers 12, similar to that shown in FIG. 1. Structure 10 includes a conductor level 14 including a dielectric layer 16 (e.g., of silicon dioxide SiO.sub.2 or any other appropriate dielectric material) surrounding conductor 18 (e.g., of copper Cu); a cap layer 20 atop conductor level 14; a dielectric layer 22; another dielectric layer 24 (e.g., of silicon nitride Si.sub.3N.sub.4 or any other dielectric material); and a patterned photoresist 26. Patterned photoresist 26 includes a pattern (opening) for the via to be formed. Dielectric layer 22 may include any silicon dioxide (SiO.sub.2) type material such as hydrogenated silicon oxycarbide (SiCOH), CORAL.TM. available from Novellus, tetraethyl orthosilicate (Si(OC.sub.2H.sub.5).sub.4)(TEOS), fluorine doped TEOS (FTEOS), fluorine doped silicate glass (FSG), undoped silicate glass (USG), boro-phospho-silicate glass (BPSG), etc. Cap layer 20 may include any typical cap material such as: high density plasma (HDP) silicon nitride, ultraviolet light transparent silicon nitride (UVN), silicon carbide (SiC), etc. [0017] An initial step of the method includes, as shown in FIG. 2, etching through dielectric (e.g., silicon nitride) layer 24. Since the etch conditions 100 used may be any conventional method, this step is not considered an integral part of the invention in all cases. [0018] Next, as shown in FIG. 3, the via is etched through dielectric layer 22. In one embodiment, etching recipe 104 includes using approximately 80 mTorr (mT) of pressure, and an RF energy of approximately 1200 watts (W) at 27 MHz and approximately 2700 W at 2 MHz, which represents an increase in RF energy compared to the conventional process. A gas flow for this embodiment includes tetrafluoro methane (CF.sub.4) and carbon monoxide (CO) in a gas flow ratio of approximately 0.104-0.200, and preferably about 0.136. Tetrafluoro methane (CF.sub.4) (also known as carbon tetrafluoride) is an etchant that etches practically all dielectrics, and is available, for example, under the brand name Freon.RTM. 14 from Dupont. In one embodiment, the gas flow includes approximately 25-40 sccm of tetrafluoro methane (CF.sub.4) (preferably about 30 sccm), and approximately 200-240 sccm of carbon monoxide (CO) (preferably about 220 sccm). In addition, the gas flow includes approximately 400 sccm of argon (Ar). This etch recipe 102 provides more than twice as fast an etch rate (i.e., approximately 95 .ANG.ngstroms/second (.ANG./s)) as the conventional process due to an increased amount of tetrafluoro methane (CF.sub.4). In addition, this etch recipe 102 is highly selective to cap layer 20, and causes no changes in the etch profile compared to the conventional process. [0019] Referring to FIG. 4, a next step includes stripping the photoresist using a plasma chemistry 102 including tetrafluoro methane (CF.sub.4), which is not used in conventional stripping processes. In one embodiment, the photoresist stripping step includes two stages. A first stage uses approximately 120 mT of pressure, and an RF energy of approximately 1000 W at 27 MHz and approximately 200 W at 2 MHz. In one embodiment, a gas flow of approximately 900-1100 sccm of oxygen (O.sub.2) (preferably about 1000 sccm) is used in the first stage. A second stage uses approximately 400 mT of pressure, and an RF energy of approximately 1600 W at 2 MHz. A gas flow of the second stage includes tetrafluoro methane (CF.sub.4) and oxygen (O.sub.2) in a gas flow ratio of approximately 0.006-0.016, and preferably about 0.010. During the second stage, the tetrafluoro methane (CF.sub.4) may be provided at approximately 7-15 sccm (preferably about 10 sccm), and the oxygen (O.sub.2) may be provided at approximately 900-1100 sccm (preferably about 1000 sccm). Continue reading about Via reactive ion etching process... Full patent description for Via reactive ion etching process Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Via reactive ion etching process patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. 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