Site News  |   Monitor Keywords  |   Monitor Archive  |   Organizer  |   Account Info  |

Vertical type nanotube semiconductor device

Vertical type nanotube semiconductor device description/claims

This application is a continuation of U.S. patent application Ser. No. 11/325,964, filed on Jan. 5, 2006, which claims priority from Korean Patent Application No. 10-2005-0025368, filed on Mar. 28, 2005, the disclosures of both of which are incorporated herein by reference in their entirety

The present invention relates to integrated circuit devices and, more particularly, to integrated circuit devices having nanotube conductive layers therein.

Nanotubes with conductive properties are cylindrical members with highly microscopic diameters of several to several tens of nanometers and significantly large aspect ratios of about 10˜1,000. Carriers are migrated by ballistic transport within a nanotube having a generally uniform resistance along its length. Particularly, a carbon nanotube has carrier mobility of about 70 times or more than that of silicon at a room temperature.

Because of excellent electrical characteristics, nanotubes can be applied to semiconductor devices, flat panel displays, batteries, various sensors, etc. Particularly, in a conventional nanotube semiconductor device, the nanotube is used as a channel through which carriers are migrated or is used as a lower electrode of a capacitor.

A bit line applied to a conventional nanotube semiconductor device can be fabricated to have a diameter of about several to several hundreds of nanometers. However, if the bit line of several to several hundreds of nanometers is fabricated in a typical manner that simply decreases a width of a conductive material, then grain boundary defects within the bit line may cut off electrical connection.

Embodiments of the invention include integrated circuit devices having nanotube elements therein. In some of these embodiments, a device is provided with a substrate and an electrically conductive nanotube bit line on the substrate. This nanotube bit line is electrically coupled to a field effect transistor. In particular, a field effect transistor is provided, which has a first current carrying terminal (e.g., drain terminal) electrically connected to the nanotube bit line. The field effect transistor may include a nanotube channel region and a gate electrode surrounding the nanotube channel region. According to aspects of these embodiments, the nanotube bit line includes at least one material selected from a group consisting of C, ZnO, CdO, In2O3, MgO, Al2O3, AlN, InN, GaN, Si, AlP, InP, GaP, InAs, GaAs, AlAs, InSb, GaSb, ZnSe, ZnS, CdS, CdSe and BiSb. This nanotube bit line may be doped with a dopant selected from a group consisting of Mg, Zn, Cd, Ti, Li, Cu, Al, Ni, Y, Ag, Mn, V, Fe, La, Ta, Nb, Ga, In, S, Se, P, As, Co, Cr, B, N, Sb and H. In some cases, the device may be a dynamic random access memory (DRAM) cell that includes a capacitor having a nanotube electrode electrically connected to a second current carrying terminal (e.g., source terminal) of the field effect transistor. The capacitor may also include a capacitor having a dielectric layer covering the nanotube electrode. Barrier layers may also be provided to improve adhesion and electrical connections within the memory cell. In particular, a first electrically conductive barrier layer may be provided that extends between the electrically conductive nanotube bit line and the nanotube channel region. A second electrically conductive barrier layer may also be provided that extends between the nanotube electrode and the second current carrying terminal of the field effect transistor. These electrically conductive barrier layers may be formed of a material selected from a group consisting of Ni, Co, Fe, alumina and carbon-based conductive materials.

According to another embodiment of the invention, a vertical nanotube semiconductor device is provided. A bit line is disposed on the substrate in parallel with the substrate. This bit line is formed as a nanotube with a conductive property. Also, a nanotube pole, which is connected to the bit line in a vertical direction to the substrate, provides a channel through which carriers migrate. Also, a gate insulating layer encircling the nanotube pole to a uniform thickness is included. A gate electrode encircles the gate insulating layer to control formation of the channel and carrier migration.

The bit line may be formed of a material selected from a group consisting of C, ZnO, CdO, In2O3, MgO, Al2O3, AlN, InN, GaN, Si, Alp, InP, GaP, InAs, GaAs, AlAs, InSb, GaSb, ZnSe, ZnS, CdS, CdSe, BiSb, and combinations of these materials. The bit line is doped with at least one material selected from a group consisting of Mg, Zn, Cd, Ti, Li, Cu, Al, Ni, Y, Ag, Mn, V, Fe, La, Ta, Nb, Ga, In, S, Se, P, As, Co, Cr, B, N, Sb, and H. Additionally, a diameter of the bit line may be in a range of 1˜100 nm.

In addition, a first barrier layer for improving a bonding strength between the bit line and the nanotube pole may be included. The first barrier layer may be formed of at least one material selected from a group consisting of Ni, Co, Fe, alumina, and a carbon-based conductive material.

The nanotube pole is formed of a material selected from a group consisting of C, ZnO, CdO, In2O3, MgO, Al2O3, AlN, InN, GaN, Si, AlP, InP, GaP, InAs, GaAs, AlAs, InSb, GaSb, ZnSe, ZnS, CdS, CdSe, BiSb, and combinations of these materials. The nanotube pole may be doped with at least one material selected from a group consisting of Mg, Zn, Cd, Ti, Li, Cu, Al, Ni, Y, Ag, Mn, V Fe, La, Ta, Nb, Ga, In, S, Se, P, As, Co, Cr, B, N, Sb, and H. A height of the nanotube pole may be the same as a length of the channel.

The gate electrode is one of a single layer formed of a material selected from the group consisting of amorphous polysilicon, doped polysilicon, poly-SiGe, and a conductive metal containing one or more metal layers. Moreover, the gate electrode may be formed as a plurality of gate electrodes spaced apart from one another by a predetermined interval.

Additional embodiments of the invention include methods of manufacturing a vertical type nanotube semiconductor device. A bit line is formed on the substrate in parallel with the substrate. The bit line may be a nanotube with a conductive property. A nanotube pole that is connected to the bit line in a vertical direction to the substrate is formed to provide a channel through which carriers migrate. After forming a gate insulating layer encircling the nanotube pole to a uniform thickness, a gate electrode is formed that encircles the gate insulating layer controls the formation of the channel.

At this time, the bit line may be formed using a method such as plasma CVD, thermal CVD, low pressure CVD, and MOCVD.

The first barrier layer may be formed to improve the bonding strength between the bit line and the nanotube pole. After forming a second insulating layer covering the substrate on which the bit line is formed, a hole for the barrier layer is formed within the second insulating layer to expose the bit line. A first barrier material layer is deposited to fill the hole for the barrier layer. Also, the first barrier layer is formed by removing the first barrier material layer so as to expose and planarize an upper surface of the second insulating layer.

The forming of the nanotube pole includes forming a third insulating layer that covers the substrate on which the bit line is formed, and forming a nanotube hole within the third insulating layer to expose the bit line. Then, a nanotube material layer is formed to fill the second contact hole, and the nanotube pole is formed by removing the nanotube material layer to expose and planarize an upper surface of the third insulating layer.

The formation of the nanotube pole may include forming a third insulating layer on the second insulating layer on which the first barrier layer is formed, and forming a nanotube hole within the third insulating layer to expose the first barrier layer. After forming a nanotube material layer to fill the nanotube hole, the nanotube pole is formed by removing the nanotube material layer to expose and planarize an upper surface of the third insulating layer.

The step of forming the gate insulating layer may include removing the third insulating layer on which the nanotube pole is formed, and forming a gate insulating material layer encircling the nanotube pole by blanket deposition. After forming a first mask layer on the nanotube pole and the gate insulating material layer, the gate insulating layer is formed by removing the gate insulating material layer using the first mask layer as an etch mask.

• Provisional Patent
• Utility Patent

• What Is a Patent?
• What Is a Trademark or Servicemark?
• What Is a Copyright?
• Patent Laws