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Vertical twist scheme for high density dramsRelated Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, Floorplanning, Constraint-based Placement (e.g., Critical Block Assignment, Delay Limits, Wiring Capacitance)Vertical twist scheme for high density drams description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070050743, Vertical twist scheme for high density drams. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of U.S. patent application Ser. No. 09/567,673, filed May 9, 2000, which is incorporated herein by reference in its entirety and to which priority is claimed. FIELD OF THE INVENTION [0002] This invention relates generally to a semiconductor memory array and semiconductor integrated circuits, and, more particularly to a scheme for arranging line conductors and interconnection lines in such a semiconductor memory array and in semiconductor integrated circuits. BACKGROUND OF THE INVENTION [0003] Semiconductor integrated circuits (ICs) typically are formed by metal-oxide semiconductor (MOS) or bipolar transistors that are integrated at a planar major surface of a silicon chip. Electrical interconnections between various transistors, and between certain transistors and input/output pads, have taken the form of electrically connecting lines that comprise a layer of metallization running along an essentially planar surface. In some ICs, two or more "levels" of interconnections may be required. The planar surfaces of the interconnections are oriented mutually parallel to, and are insulated from, both each other and the top planar surface of the chip by suitable insulating layers. Connections to the transistors at lower levels than the metallization layers are provided through openings called contacts, and connections between different interconnection layers are provided through insulation openings called vias. [0004] In memory ICs, such as random access memories (RAMs), the data in the memory array are accessed by an external data path by means of a number of electrically conducting lines. The electrically conducting lines in the array are conventionally arranged in the form of an array of parallel metallization strips. For example, a dynamic RAM (DRAM) contains an array of hundreds of parallel bit lines, or digit lines. A DRAM also contains an array of parallel word lines. The word lines typically lie at a different planar level than the bit lines. The array of bit lines and the array of word lines lie perpendicular to each other, forming a grid. Memory cells in the DRAM lie at an intersection of a bit line and a word line. [0005] The bit lines, or digit lines, in a DRAM can give rise to electrical cross-coupling or "cross-talk." For example, access to any given bit line or digit line may spuriously influence memory cells connected to adjacent bit lines or digit lines. The term "pattern sensitivity" is applied to this undesirable phenomenon. The problems of cross-talk and pattern sensitivity can arise in other interconnection arrays, such as address busses and data busses where similarly paired, parallelly disposed line conductors are employed. In these environments, cross-talk and pattern sensitivity can result in undesirable errors. [0006] Memory ICs such as DRAMs typically have a memory array of millions of memory cells that store electrical charges indicative of binary data. For instance, the presence of an electrical charge in the memory cell usually equates to a binary "1" value, and the absence of an electrical charge usually equates to a binary "0" value. The memory cells are accessed via address signals on row and column lines. Once accessed, data is written to, or read from, the addressed memory cell via bit lines, or digit lines. [0007] One common design found in many memory circuit topologies or configurations or layouts is the "folded bit line" or "folded digit line" structure or architecture, also known as the 8F.sup.2 architecture. In a folded bit line construction, the bit lines are arranged in pairs with each pair being assigned to complementary binary signals. For example, one bit line (the "true" line) in the pair is dedicated to a binary signal DATA while the other bit line (the "associated complementary" line) in the pair is dedicated to handle the associated complementary binary signal DATA*. (The asterisk notation "*" is used throughout to indicate the binary complement.) [0008] The memory cells are connected to one of the bit lines in the folded pair. During read and write operations, the bit lines are driven to opposing voltage levels depending on the data content being written to or read from the memory cell. For purposes of explanation, the following example describes a read operation of a memory cell holding a charge indicative of a binary "1" value. The voltage potential of both bit lines in the pair are first preferably equalized to a middle voltage level such as 1.2V for a memory circuit with a supply voltage level of 2.5V. Then, the addressed memory cell is accessed and the charge held therein begins to flow to one of the bit lines in the bit line pair, causing the voltage of that bit line to be raised slightly above the voltage of the other bit line of the pair. A sense amplifier, or similar circuit, senses the voltage differential on the bit line pair and further increases this differential by increasing the voltage on the first bit line to 2.5V and decreasing the voltage on the second bit line to 0 V. The folded bit lines thereby output the data in a complementary form, which is transmitted to the output pads. [0009] One version of a folded bit line architecture or structure is the twisted bit line structure. FIG. 1 illustrates a conventional twisted bit line structure having bit line pairs D0/D0* through D3/D3*. Twisting occurs at twist junctions 120 across the array of bit lines when the true line in a bit line pair (D0 for example) exchanges positions with the associated complementary line (D0*) in the pair. Memory cells are coupled to the bit line pairs throughout the array. Representative memory cells 122a through 122n and 124a through 124n are shown coupled to bit line pair D0/D0*. The twisted bit line structure evolved as a technique to reduce bit line interference noise or cross-talk or pattern sensitivity during chip operation. Such noise becomes more problematic as memory density increases. The twisted bit line structure is therefore used in larger, higher density, memories such as a 64 Mb DRAM. [0010] Conventional twisted bit line architectures have a number of disadvantages as compared to open bit line architectures. One disadvantage is the relatively large amount of chip "real estate" that is typically used by the twist junctions 120. Yet another disadvantage is that the use of the conventional twisted folded bit line architecture may result in an inefficient use of the cell matrix space. The conventional twisted bit line architecture does not use space efficiently because it provides a lower packing density of memory cells than the open bit line architecture, and because it cannot utilize a cross-point layout cell structure. Some of these disadvantages could be overcome if a cross-point layout were combined with a folded bit line architecture. This combination would offer both high packing density and good noise immunity. Implementing this combination would require that the bit lines be vertically twisted, not just horizontally twisted as shown in FIG. 1. [0011] One attempt in the prior art to provide a DRAM architecture that utilizes the advantages of both a cross-point layout cell architecture and a folded bit line architecture is described in U.S. Pat. No. 5,107,459 to Chu et al. Chu utilizes a three-dimensional approach by stacking the two lines in a bit line pair (the true bit line and the complementary bit line) vertically one above the other in two layers of metallization. The two layers are twisted by means of a third layer. [0012] A scheme similar to the scheme described by Chu is shown conceptually and schematically in FIG. 2. In the scheme in FIG. 2, bit line pairs (D.sub.1, D.sub.1*) and (D.sub.2, D.sub.2*) form a sub-array 200. Bit line pair (D.sub.1, D.sub.1*) consists of bit lines D.sub.1L and D.sub.1L* to the left of the twisting region 210, and bit lines D.sub.1R and D.sub.1R* to the right of the twisting region 210. Similarly, bit line pair (D.sub.2, D.sub.2*) consists of bit lines D.sub.2L and D.sub.2L* to the left of the twisting region 210, and bit lines D.sub.2R and D.sub.2R* to the right of the twisting region 210. The thick strips in FIG. 2 represent a first layer of metallization, and the thin solid lines represent a second layer of metallization arranged above, and insulated from, the first layer of metallization. The alternating dashed-dotted lines in FIG. 2 represent a third interconnection layer, a polysilicon layer, arranged below and insulated from the first layer of metallization. The twisting region 210 is situated between two dummy word lines 220 formed in the polysilicon layer. The two dummy word lines 220 are situated adjacent to real word lines (not shown). [0013] In the scheme shown in FIG. 2, the two bit lines (the true bit line and the complementary bit line) in a bit line pair, which are stacked vertically one above the other, exchange vertical positions as they cross the twisting region 210. In other words, the bit lines are vertically twisted within the twisting region 210. For example, the portion of the true bit line D.sub.2 on the left of the twisting region 210 (D.sub.2L) is formed in the first (lower) layer of metallization, while the portion of D.sub.2 on the right of the twisting region 210 (D.sub.2R) is formed in the second (upper) layer of metallization. Likewise, the portion of the complementary bit line D.sub.2* on the left of the twisting region 210 (D.sub.2L*) is formed in the second (upper) layer of metallization, while the portion of D.sub.2* on the right of the twisting region 210 (D.sub.2R*) is formed in the first (lower) layer of metallization. Thus D.sub.2 and D.sub.2* exchange vertical positions as they cross the twisting region 210. As shown in FIG. 2, the vertical twisting of bit line pair (D.sub.2, D.sub.2*) is effected within the twisting region 210 by having the bit line D.sub.2L veer to its left (upwards in FIG. 2), and connecting D.sub.2L to D.sub.2R through a via 230. The vertical twisting of bit line pair (D.sub.2, D.sub.2*) is further effected within the twisting region 210 by having the bit line D.sub.2R* veer to its left (downwards in FIG. 2), and connecting D.sub.2R* to the bit line D.sub.2L* through a via 240. [0014] Vertical twisting of the other bit line pair (D.sub.1, D.sub.1*) in sub-array 200 is accomplished in a different manner. The portion of the true bit line D.sub.1 on the left of the twisting region 210 (DIL) is formed in the first (lower) layer of metallization, while the portion of D.sub.1 on the right of the twisting region 210 (DIR) is formed in the second (upper) layer of metallization. Likewise, the portion of the complementary bit line D.sub.1* on the left of the twisting region 210 (D.sub.1L*) is formed in the second (upper) layer of metallization, while the portion of D.sub.1* on the right of the twisting region 210 (D.sub.1R*) is formed in the first (lower) layer of metallization. As shown in FIG. 2, the vertical twisting of bit line pair (D.sub.1, D.sub.1*) is effected within the twisting region 210 by having the bit line DIL connect to a polysilicon layer interconnection 250 through a contact hole 255. The polysilicon layer interconnection 250 extends across the twisting region 210, passes underneath bit lines D.sub.2L and D.sub.2R*, and connects to an interlayer interconnection 260 through a contact hole 265. The interlayer interconnection 260, which is formed in the first metallization layer, connects in turn to the bit line DIR through a via 270. The vertical twisting of bit line pair (D.sub.1, D.sub.1*) is further effected within the twisting region 210 by having the bit line D.sub.1R* connect to a polysilicon layer interconnection 275 through a contact hole 280. The polysilicon layer interconnection 275 extends across the twisting region 210, passes underneath the bit lines D.sub.2R* and D.sub.2L, and connects to an interlayer interconnection 285 through a contact hole 290. The interlayer interconnection 285, which is formed in the first metallization layer, connects in turn to the bit line D.sub.1L* through a via 295. [0015] The vertical twisting scheme represented in FIG. 2 has a number of shortcomings. One shortcoming is that the bit line pairs within each sub-array exchange horizontal positions as they cross the twisting region 210. In other words, the bit lines are twisted horizontally as well as vertically. For example, bit line pairs (D.sub.1, D.sub.1*) and (D.sub.2, D.sub.2*) in FIG. 2 exchange horizontal positions (upper and lower positions in the figure) within sub-array 200 as they cross the twisting region 210. This exchange of horizontal positions tends to complicate the layout of the memory array. Another shortcoming of the scheme in FIG. 2 is that the scheme requires the use of two sets of polysilicon layer interconnections to effect the vertical twisting of the odd-numbered bit line pairs, (D.sub.2j+1, D.sub.2j+1*) (with j=0, 1, 2, 3) in each sub-array. For example, in FIG. 2 two polysilicon layer interconnections (250 and 275) are used to effect the vertical twisting of the odd-numbered bit line pair (D.sub.1, D.sub.1*) in sub-array 200. A third shortcoming of the vertical twisting scheme in FIG. 2 is that the scheme requires three layers to achieve the twist. This added complexity takes up more space (being both wide and long due to additional metal pads) and does not allow three twists. Further, the vertical twisting scheme of FIG. 2 requires the deposition of additional layers beyond the layers deposited in the standard DRAM fabrication process. A final shortcoming of the scheme in FIG. 2 is that the scheme does not allow vertical twisting of only one of the bit line pairs of each sub-array. A twisting scheme without this shortcoming would provide more design flexibility. For example, the ability to effect vertical twisting of only one of the bit line pairs would allow the twisting of each of the bit line pairs in a sub-array 200 to occur at different locations, as shown in FIG. 1 (where bit line pair (D0, D0*) is twisted at a different location 120 than bit line pair (D1, D1*)). Staggering the locations at which adjacent bit line pairs are twisted provides superior noise reduction. [0016] The present invention is directed to overcoming, or at least reducing the effects of, one or more of the perceived shortcomings of prior art twisting schemes. Furthermore, the present invention advantageously occupies less chip "real estate" than the vertical twisting scheme represented in FIG. 2. SUMMARY OF THE INVENTION [0017] In accordance with one aspect of the present invention, an interconnection array subunit and method for forming the interconnection array subunit are provided, the interconnection array subunit including a first pair of line conductors in first and second regions, the first pair of line conductors including a first true line conductor and a first associated complementary line conductor connected and vertically twisted in a vertical twisting region between the first and second regions. The interconnection array subunit also includes a second pair of line conductors adjacent to the first pair of line conductors in the first and second regions, the second pair of line conductors including a second true line conductor and a second associated complementary line conductor. The interconnection array subunit also includes a first interconnection layer disposed in the vertical twisting region, the first interconnection layer connecting the second associated complementary line conductor in the first region to the second associated complementary line conductor in the second region. The interconnection array subunit also includes a second interconnection layer disposed in the vertical twisting region, the second interconnection layer connecting the second true line conductor in the first region to the second true line conductor in the second region. The two interconnection layers do so by bypassing beneath the adjacent twist region. The first true line conductor is disposed below the first associated complementary line conductor in the first region and above the first associated complementary line conductor in the second region. The second true line conductor is disposed below the second associated complementary line conductor in the first and second regions. [0018] In accordance with another aspect of the instant invention, a method is provided for laying out line conductors for such an interconnection array subunit. BRIEF DESCRIPTION OF THE DRAWINGS [0019] Other objects and advantages of the invention will become apparent upon reading the following detailed description of a specific embodiment of the invention, and upon reference to the accompanying drawings, in which: Continue reading about Vertical twist scheme for high density drams... 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