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  Vertical replacement-gate junction field-effect transistorUSPTO Application #: 20060166429Title: Vertical replacement-gate junction field-effect transistor Abstract: An architecture for creating a vertical JFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is positioned over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET. In an associated method of manufacturing the semiconductor device, a first source/drain region is formed in a semiconductor layer. A field-effect transistor gate region, including a channel and a gate electrode, is formed over the first source/drain region. A second source/drain region is then formed over the channel having the appropriate conductivity type. (end of abstract) Agent: Beusse Wolter Sanks Mora & Maire, P. A. - Orlando, FL, US Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, Ross Thomson, Jack Qingsheng Zhao USPTO Applicaton #: 20060166429 - Class: 438212000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Complementary Insulated Gate Field Effect Transistors (i.e., Cmos), Vertical Channel The Patent Description & Claims data below is from USPTO Patent Application 20060166429. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This patent application is a continuation of U.S. patent application Ser. No. 10/723,547 filed on Nov. 26, 2003, which is a divisional of U.S. patent application Ser. No. 09/950,384 filed on Sep. 10, 2001, now U.S. Pat. No. 6,690,040. FIELD OF THE INVENTION [0002] The present invention is directed to semiconductor devices incorporating junctions of varying conductivity types and methods of making such devices. More specifically, the present invention is directed to vertical replacement-gate (VRG) junction field-effect transistor devices and methods for fabricating integrated circuits incorporating such devices. BACKGROUND OF THE INVENTION [0003] Enhancing semiconductor device performance and increasing device density (the number of devices per unit area), continue to be important objectives of the semiconductor industry. Device density is increased by making individual devices smaller and packing devices more compactly. But, as the device dimensions (also referred to as the feature size or design rules) decrease, the methods for forming devices and their constituent elements must be adapted. For instance, production device sizes are currently in the range of 0.25 microns to 0.12 microns, with an inexorable trend toward smaller dimensions. However, as the device dimensions shrink, certain manufacturing limitations arise, especially with respect to the lithographic processes. In fact, current lithographic processes are nearing the point where they are unable to accurately manufacture devices at the required minimal sizes demanded by today's device users. [0004] Currently most metal-oxide-semiconductor field effect transistors (MOSFETs) are formed in a lateral configuration, with the current flowing parallel to the major plane of the substrate or body surface. As the size of these MOSFET devices decreases to achieve increased device density, the fabrication process becomes increasingly difficult. In particular, the lithographic process for creating the gate channel is problematic, as the wavelength of the radiation used to delineate an image in the lithographic pattern approaches the device dimensions. Therefore, for lateral MOSFETs, the gate length is approaching the point where it cannot be precisely controlled through the lithographic techniques. [0005] Like MOSFETs, junction field-effect transistors (JFETs) have been formed using lithographically defined channel lengths. As the channel length decreases to increase device density, the channel length may not be controllable using conventional photolithographic techniques. Instead, expensive x-ray and electron beam lithographic equipment may be required for the formation of both MOSFETs and JFETs with state-of-the-art channel lengths. [0006] Generally, integrated circuits comprise a plurality of active devices, including MOSFETs, JFETs and bipolarjunction transistors, as well as passive components such as resistors and capacitors. Commonly owned U.S. Pat. Nos. 6,027,975 and 6,197,441, which are hereby incorporated by reference, teach certain techniques for the fabrication of vertical replacement gate (VRG) MOSFETs. It is therefore advantageous to fabricate JFETs using similar and compatible processing steps as those employed for the fabrication of MOSFETs to reduce integrated circuit fabrication costs. BRIEF SUMMARY OF THE INVENTION [0007] To provide further advances in the fabrication of JFETs having gate lengths precisely controlled through a deposited film thickness, an architecture is provided for fabricating vertical replacement gate (VRG) JFET devices. [0008] According to one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first doped region formed therein. A second doped region of a different conductivity type than the first region is formed over the first region. A third doped region is formed over the second doped region, with a different conductivity type than the second doped region. [0009] The first region is a source/drain region of a junction field-effect transistor, and the second doped region is the channel. The second source/drain region is formed over the channel and comprises the third doped region. [0010] In an associated method of manufacture, an integrated circuit structure is fabricated by providing a semiconductor layer suitable for device formation and having a first surface formed along a first plane. For a JFET device, a first device region is formed in the semiconductor layer, wherein the device region is selected from among a source and a drain region. A gate region for the JFET is formed above the first device region. In fabricating the vertical JFET, the gate length is precisely controlled through the use of a sacrificial layer. Both JFETs and MOSFETs can be fabricated using the same basic fabrication process. [0011] A JFET fabricated according to the teachings of the present invention provides a uniform depletion layer (or a uniform pinch-off condition) because the gate completely surrounds the channel and the channel is uniformly doped along a horizontal cross-section. In the prior art, the channel is oriented horizontally and the carriers flow horizontally through it. The channel is formed by diffusion into the semiconductor substrate and thus the upper channel region has a higher doping density then the lower region. As a result, the depletion layer is not uniform along any given vertical. Also, creating dual wells in a semiconductor substrate according to the present invention allows the fabrication of closely matched JFET pairs. BRIEF DESCRIPTION OF THE DRAWINGS [0012] The present invention can be more easily understood and the further advantages and uses thereof more readily apparent, when considered in view of the description of the preferred embodiments and the following figures in which: [0013] FIGS. 1A through 1R illustrate, in cross-section, a circuit structure according to one embodiment of the invention during sequential fabrication steps. [0014] In accordance with common practice, the various described features are not drawn to scale, but are drawn to emphasize specific features relevant to the invention. Reference characters denote like elements throughout the figures and text. DESCRIPTION OF THE PREFERRED EMBODIMENTS [0015] With regard to the fabrication of transistors and integrated circuits, the term "major surface" refers to that surface of the semiconductor layer in and about which a plurality of transistors are fabricated, e.g., in a planar process. As used herein, the term "vertical" means substantially orthogonal with respect to the major surface. Typically, the major surface is along a <100> plane of a monocrystalline silicon layer on which the field-effect transistor devices are fabricated. The term "vertical transistor" means a transistor with individual semiconductor components vertically oriented with respect to the major surface so that the current flows vertically from source to drain. By way of example, for a vertical JFET the source, channel and drain regions are formed in relatively vertical alignment with respect to the major surface. [0016] FIGS. 1A through 1R illustrate cross-sectional views of an integrated circuit structure 200 during various stages of fabrication to form an exemplary device according to the present invention. From the description, it will become apparent how a vertical replacement gate junction field-effect transistor can be fabricated, either independently or in conjunction with the fabrication of a vertical replacement gate metal-oxide-semiconductor field-effect transistor. [0017] The fabrication process for forming both a VRG MOSFET and JFET is illustrated with reference to FIGS. 1A through 1R. The formation of both a VRG MOSFET and a VRG JFET are illustrated to demonstrate the compatibility of fabricating both device types in a single fabrication process. However, the invention is not limited to embodiments wherein a VRG MOSFET are a VRG JFET are fabricated in a side-by-side orientation or even in the same process. The various semiconductor features and regions described therein are preferably composed of silicon, but it known to those skilled in the art that other embodiments of the invention may be based on other semiconductor materials, including compound or hereto junction semiconductors alone or in combination. [0018] Referring to FIG. 1A, a heavily doped source region 205 is formed in a silicon substrate 200, preferably a substrate having a <100> crystal orientation along an exposed major surface 203. In this illustration, of a vertical MOSFET and a vertical JFET, the source region of the device is formed in the silicon substrate and the drain region is formed atop a subsequently formed vertical channel, as will be discussed further. Alternatively, the drain region may be formed in the substrate with the source region formed atop the vertical channel. The former embodiment is the subject of this description. However, from this description, one skilled in the art can easily form a device in which the drain region is formed in the silicon substrate and the source region is formed overlying the subsequently formed vertical channel. [0019] The depth of the heavily doped source region 205, the concentration of the dopant therein and the type of dopant (e.g., n-type or p-type) are all matters of design choice. An exemplary source region 205, wherein the dopant is phosphorous (P), arsenic (As), antimony (Sb) or boron (B) has a dopant concentration in the range of about 1.times.10.sup.19 atoms/cm.sup.3 to about 5.times.10.sup.20 atoms/cm.sup.3. A source region depth of about 200 nm is suitable. Preferably, the source region 205 is formed by a high dose ion implantation in the range of 1.times.10.sup.4 to 1.times.10.sup.16 atoms/cm.sup.2 with an energy of 1 to 100 KeV. Continue reading... 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