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  Vertical misfet manufacturing method, vertical misfet, semiconductor memory device manufacturing method, and semiconductor memory deviceUSPTO Application #: 20070202638Title: Vertical misfet manufacturing method, vertical misfet, semiconductor memory device manufacturing method, and semiconductor memory device Abstract: A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film (10) constituting the channel forming region from an n type poly-crystalline silicon film (7) constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film (10); and reducing an effective impurity concentration in the poly-crystalline silicon film (10). (end of abstract) Agent: Antonelli, Terry, Stout & Kraus, LLP - Arlington, VA, US Inventors: Tsuyoshi Tabata, Kazuo Nakazato, Hiroshi Kujirai, Masahiro Moniwa, Hideyuki Matsuoka, Teruaki Kisu, Teruo Kisu, Haruko Kisu, Satoru Haga USPTO Applicaton #: 20070202638 - Class: 438156000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, On Insulating Substrate Or Layer (e.g., Tft, Etc.), Having Insulated Gate, Vertical Channel The Patent Description & Claims data below is from USPTO Patent Application 20070202638. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a divisional application of U.S. application Ser. No. 10/493,443, filed Apr. 23, 2004, the contents of which are incorporated herein by reference. TECHNICAL FIELD OF THE INVENTION [0002] The present invention relates to a vertical MISFET, a semiconductor memory device, and their manufacturing methods and, particularly, to a technique effectively applied to a semiconductor memory device in which a transistor composed of a memory cell is constituted by a vertical MISFET (Metal Insulator Semiconductor Field Effect transistor). BACKGROUND OF THE INVENTION [0003] The DRAM (Dynamic Random Access Memory) has been mainly used as a general-purpose and high-capacity semiconductor memory device. Memory cells in the DRAM are placed at the intersections between a plurality of word lines and a plurality of bit lines arranged in matrix on a main surface of a semiconductor substrate, and each is composed of one memory cell selecting MISFET and one capacitive element (capacitor) connected to this MISFET in series. The memory cell selecting MISFET is mainly composed of a gate oxide film, a gate electrode formed integrally with a word line, and a pair of semiconductor regions constituting a source and a drain. The bit line is arranged on the memory cell selecting MISFET and electrically connected to one of the source and drain. Similarly, a data storage capacitor is arranged on the memory cell selecting MISFET and electrically connected to the other of the source and drain. [0004] Japanese Patent Laid-Open No. 5-110019 discloses a one-transistor and one-capacitor semiconductor memory device in which a trench capacitor is formed in a semiconductor substrate and a vertical MIS transistor is arranged thereon. [0005] Japanese Patent Laid-Open No. 11-87541 discloses another vertical MISFET, which is different from that shown in Japanese Patent Laid-Open No. 5-110019. In this vertical MISFET, a columnar laminated structure made of poly-crystalline silicon is provided on a semiconductor substrate, and a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) are formed in this order from below in the laminated structure. A sidewall of the intermediate semiconductor layer functions as a channel region and a gate insulating film is formed on the surface of the sidewall. Also, a gate electrode is formed on the sidewall of the laminated structure via the above-mentioned gate insulating film. DISCLOSURE OF THE INVENTION [0006] The inventors of the present invention have been developing a semiconductor memory device using the vertical MISFET disclosed in Japanese Patent Laid-Open No. 11-87541. In this vertical MISFET, the source region, the channel forming region, and the drain region are formed in the columnar laminated structure formed on the semiconductor substrate. Therefore, there is an advantage of being capable of reducing an area occupied by the transistor. For example, if the trench capacitor is formed inside the trench formed in the semiconductor substrate and the memory cell selecting MISFET is formed thereon by using this vertical MISFET, it is possible to realize the memory cell with a smaller cell size than that of a conventional DRAM. [0007] Meanwhile, since the source and drain regions of the vertical MISFET are formed by laminating poly-crystalline silicon films each having a high impurity concentration on and below the channel forming region composed of an undoped poly-crystalline silicon film or a poly-crystalline silicon film having a extremely low impurity concentration, the impurities in the source and drain are thermally diffused easily into the channel forming region by a thermal treatment during a process thereof. [0008] However, since the leakage current (off current) during the time when the vertical MISFET is not operated is reduced by complete depletion of the channel forming region, there is the problem that if the impurities in the source and drain regions are thermally diffused in the channel forming region, the complete depletion of the channel forming region is hindered and the leakage current (off current) is increased. Additionally, the threshold voltage is varied due to the diffusion of the impurities into the channel forming region. [0009] An object of the present invention is to provide a technique capable of achieving the vertical MISFET in which the leakage current (off current) is smaller. [0010] An object of the present invention is to provide a technique capable of achieving the vertical MISFET in which the variation of the threshold voltage is reduced. [0011] The above and other objects and novel characteristics of the present invention will be apparent from the description of the specification and the accompanying drawings. [0012] Outlines of the typical ones of the inventions disclosed in this application will be briefly described as follows. [0013] The present invention is a manufacturing method for a MISFET having a source region, a channel forming region, and a drain region formed over a main surface of a semiconductor substrate, and a gate electrode formed on a sidewall of said channel forming region via a gate insulating film, or is a manufacturing method for a semiconductor memory device provided with said MISFET, the method comprising the steps of: forming the source region containing a first impurity over the main surface of the semiconductor substrate; forming the channel forming region over said source region; introducing a second impurity of a conductivity type opposite to that of said first impurity into said channel forming region; and forming, over said channel forming region, the drain region containing said first impurity. [0014] Also, the semiconductor memory device according to the present invention is provided with a MISFET having a source region, a channel forming region, and a drain region formed over a main surface of a semiconductor substrate, and a gate electrode formed on a sidewall of said channel forming region via a gate insulating film, wherein said source and drain regions are each composed of a poly-crystalline silicon film containing a first impurity, and said channel forming region is composed of a poly-crystalline silicon film containing a second impurity of a conductivity type opposite to that of said first impurity. BRIEF DESCRIPTION OF THE DRAWINGS [0015] FIG. 1 is a plan view showing a principal part of a semiconductor substrate in a semiconductor memory device manufacturing method according to an embodiment of the present invention. [0016] FIG. 2 is a sectional view showing a principal part of the semiconductor substrate taken along the line A-A' in FIG. 1. [0017] FIG. 3 is a sectional view showing a principal part of a semiconductor substrate in the semiconductor memory device manufacturing method according to the embodiment of the present invention. [0018] FIG. 4 is a plan view showing a principal part of a semiconductor substrate in the semiconductor memory device manufacturing method according to the embodiment of the present invention. [0019] FIG. 5 is a sectional view showing a principal part of a semiconductor substrate in the semiconductor memory device manufacturing method according to the embodiment of the present invention. Continue reading... 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