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Using constrained scan cells to test integrated circuits

Using constrained scan cells to test integrated circuits description/claims

This application claims the benefit of U.S. Provisional Application No. 60/510,641, filed Oct. 10, 2003, which is hereby incorporated by reference.

This invention relates generally to the testing of circuits for faults. More particularly, this invention relates to a method and apparatus for constraining scan cells in a circuit under test to improve its testability.

The very large scale integrated (VLSI) circuits fabricated today typically contain hundreds of thousands of circuit elements. Testing these complex circuits to isolate faulty circuits from fault-free circuits has become increasingly difficult because of the inaccessibility of internal circuit elements and the elements' interdependencies. Furthermore, as the number of possible test paths through a circuit rises at 2n, where n is the number of circuit elements, efficient testing will continue to increase in difficulty as the density of these circuits continues to grow.

To test a circuit, a set of test vectors, or patterns, must be developed. The circuit is simulated without faults and the test patterns are applied to determine the circuit's expected response to the patterns at its primary outputs. The circuit is then simulated with faults and the test patterns again applied to determine if there is a change in the expected response to any pattern at the outputs. A fault that does not cause a change in the expected (fault free) response is an undetected fault. A test procedure desirably detects a high percentage of faults, and thus should have a minimum of undetected faults.

One common method of developing tests employs external automated test equipment (ATE). In this method, an automatic test pattern generator (ATPG) is used which, given a circuit and fault model, generates a set of test patterns designed to detect close to 100% of the circuit's faults. These deterministic test patterns are then compressed and stored in a tester. During testing, they are decompressed and loaded into the primary inputs of the circuit under test (CUT). Faults are detected by comparing the response of the circuit to the expected response. Although deterministic ATPG can detect close to 100% of faults, it requires enormous resources to generate and store the test patterns required for complex VLSI circuits. Furthermore, interactions between the external tester and elements in the CUT create their own set of potential errors.

To counter these problems, built-in self-test (BIST) methods have been developed that move the test pattern generation and output response analysis from an external source onto the chip itself. The core of the BIST technology is that rather than using a defined set of test patterns specifically defined to detect a known set of faults, a pseudo-random pattern generator (PRPG), generally a linear feedback shift register (LFSR), on the chip itself generates pseudo-random patterns which are then used to detect faults. On-chip output response analysis is typically performed by a multiple-input-shift-register (MISR), a circuit that compacts the output response and generates a signature for comparison with the signature of a fault-free circuit.

Although pseudo-random pattern generation is simple, this method rarely achieves the close-to 100% fault detection achieved by ATPG, as there are almost always faults that require very specific patterns to test; these patterns often take many, many cycles to be automatically generated, thereby elevating the cost of test application and fault simulation beyond acceptable levels.

To tackle the problem of pseudo-random-pattern resistance, many techniques have been proposed, which, generally speaking, can be classified into two categories: changing the attributes of the pseudo-random patterns, or physically modifying the CUT.

The first category consists of techniques for modifying the pseudo-random patterns to provide better fault coverage. Some of these modification methods include reseeding, weighted random testing, and pattern mapping. In reseeding, deterministic test patterns are compressed and encoded as seeds for a PRPG. These seeds then generate test patterns known to find otherwise-undetectable faults. Weighted random testing uses mathematical methods to tweak the pseudo-random patterns in ways that bias them toward detecting random-pattern-resistant faults by assigning weights to the values contained in specific scan cells, biasing their values towards “1” or “0”. Pattern mapping takes the set of patterns generated by the PRPG and transforms them, using on-chip logic, into a new set of deterministic patterns that provides the desired fault coverage. However, these methods are significantly more complicated than simple random pattern generation and either require extra memory to store the seeds or weight sets, or require additional logic, all of which is expensive in terms of area overhead.

Another way of improving random pattern testability is through physical modification of the CUT. Test points, which include observation and control points, are inserted at selected nodes of the CUT. A control point—which forces a specific location in the circuit under test to a particular signal value—can test for known undetected faults at a node (e.g., a logic gate), and can also test for otherwise undetectable faults in the node's fanout cone. A control point is typically inserted by adding logic to the circuit. An observation point allows faults to be tested that do not propagate to a CUT output, but can be observed at a specific location within the CUT logic. Observation points—typically inserted by adding an additional output lead from the node—improve the observability both of the output of an internal node and nodes in its fanin cone.

One such method of selecting and inserting test points, multi-phase test point insertion (MTPI), partitions the testing into multiple phases, in which each phase includes testing for a progressively reduced set of faults. In the first phase, observation points are selected to capture the detectable faults. Within each subsequent phase, a set of control points are selected that, when added to the CUT logic, can find still-undetected faults. While observation points help improve fault coverage, control points can cause complicated changes in the circuit that may not always improve the fault coverage and that also may cause timing degradations due to the additional logic inserted into critical paths of the core logic of the CUT.

Various new and non-obvious apparatus and methods for testing an integrated circuit using modified scan cells are disclosed. The disclosed exemplary apparatus and methods should not be construed as limiting in any way. Instead, the present disclosure is directed toward novel and non-obvious features and aspects of the various disclosed embodiments, alone and in various combinations and subcombinations with one another. The apparatus and methods are not limited to any specific aspect, feature, or combinations thereof, nor do the disclosed apparatus and methods require that any one or more specific advantages be present or problems be solved.

In one disclosed embodiment, a control point is selected in an integrated circuit design. One or more scan cells in the integrated circuit design are identified that can be loaded with a set of fixed values in order to propagate a desired test value to the control point. The integrated circuit design is modified to include circuit components configured to load the scan cells in the integrated circuit design with the set of fixed values during a test phase. In certain implementations, the functional paths of the integrated circuit design are unchanged after the modification. The one or more scan cells may be identified by justifying the control point to one or more scan cells, thereby determining values that the scan cells must output in order to drive the control point to the desired test value. In some implementations, a control point can be selected by performing a probabilistic fault simulation of the integrated circuit design, identifying one or more nodes in the integrated circuit design where fault coverage is below a selected threshold, and designating an output of one of the identified nodes as the control point. The set of fixed value with which the one or more scan cells can be loaded is termed a justification cube. In some implementations, the method may further includes identifying multiple justification cube candidates for propagating the desire value to the control point, calculating a performance parameter for a selected justification cube candidate (the performance parameter being indicative of the fault detection probability of the selected justification cube), and evaluating the justification cube candidate based at least in part on the performance parameter. The performance parameter may be calculated, for example, by obtaining a signal and pattern probability associated with the selected justification cube candidate (e.g., by simulating faults in the integrated circuit design while applying the justification cube candidate to corresponding scan cells), using the signal and pattern probability to obtain a propagation profile indicative of the selected justification cube candidate's ability to locate faults, and calculating the performance parameter using the propagation profile. In certain implementations, if a justification-cube candidate overlaps a previously chosen justification cube candidate, it is discarded. The method may further include identifying at least one observation point (a point in the integrated circuit design having a value indicative of the existence of a downstream fault) in the integrated circuit design.

In another embodiment, a method of testing an integrated circuit is disclosed. In this embodiment, a test pattern is shifted into a scan chain comprising multiple scan cells, and, during a portion of the period of clock cycles, the inputs of one or more scan cells in the scan chain are overridden to load a set of known values into the scan chain. thereby modifying the test pattern. The modified test pattern may be launched into the logic of the integrated circuit, thereby provoking a targeted fault at a control point. In some implementations, the act of overriding the inputs of the one or more scan cells is triggered by a signal generated on the integrated circuit (e.g., from a phase decoder on the integrated circuit). Furthermore, the overriding can be executed at least partially by logic coupled to the inputs of one or more of the scan cells. In some embodiments, the portion of the period of clock cycles when the scan cells are overridden is the last clock cycle of the period.

Another of the disclosed embodiments is a scan cell used for testing logic in an integrated circuit. The scan cell of this embodiment comprises a clocked element (e.g., a flip-flop) that inputs test-pattern data from a test-pattern-input path during a scan mode and inputs system data on a system-data path during an operational mode, respectively. The scan cell also comprises test logic having an output coupled to the test-pattern-input path and having inputs coupled to a scan path and one or more scan-override paths. In this embodiment, the value on at least one of the scan override paths controls the value on the test-pattern input path and is at least partially determined by test hardware (e.g., a phase decoder and shift counter) located on the integrated circuit. The clocked element may be further configured to output data on a downstream functional path whose timing is unaffected by the test logic. In some implementations, the test logic is configured to output a logic high value or a logic low value on the test-pattern-input path when a scan-override path has a logic high value.

Another disclosed embodiment is a method for designing a built-in self-test (BIST) architecture for a circuit under test (CUT). In this embodiment, faults are simulated within the CUT (e.g., faults undetected by pseudo-random patterns), and a control point candidate within the logic of the CUT is identified which has a threshold probability of provoking a target fault when it has a specific logic value. The control point candidate is justified to a corresponding set of one or more scan cells in the CUT. The act of justifying comprises determining the values that the corresponding set of one or more scan cells should output to force the control point candidate to the specific logic value. The justified control point candidate is evaluated with respect to other justified control point candidates, and, based at least in part on the evaluation, at least one scan cell within the CUT is assigned to be a constrained scan cell. The constrained scan cell can be configured to input a set value during a predetermined test phase. The method may further include selecting one or more observation points within the logic of the CUT.

Another embodiment is a circuit which comprises circuit logic and one or more scan chains. The scan chains are coupled to the circuit logic and are operable in at least two modes: a scan mode and an operational mode. This embodiment additionally comprises test logic that is coupled to a scan path of at least one scan cell and that is configured to load the scan cells with either a fixed value or a pseudo-random value during the scan mode. In certain implementations, the test logic is not directly coupled to the circuit logic. The circuit may also include a pseudo-random pattern generator (e.g., a linear feedback shift register (LFSR)) coupled to the test logic, which produces the pseudo-random value. In certain implementations, the circuit also comprises a phase decoder which is coupled to the test logic and which at least partially produces the fixed value. In these implementations, the circuit may also have a shift counter which has an output signal that is logically coupled with an output signal of the phase decoder, the shift counter being configured to control when the fixed value is loaded by the test logic into one of the scan cells. The shift counter may be configured, for example, to load the fixed value during a last shift cycle of the scan mode. The circuit may also include an observation point in the circuit logic, the observation point having a value indicative of the presence of a fault whose value does not otherwise propagate to circuit logic outputs.

• Provisional Patent
• Utility Patent

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