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12/20/07 - USPTO Class 257 |  81 views | #20070290292 | Prev - Next | About this Page  257 rss/xml feed  monitor keywords

Use of teos oxides in integrated circuit fabrication processes

USPTO Application #: 20070290292
Title: Use of teos oxides in integrated circuit fabrication processes
Abstract: A method for manufacturing a low temperature removable silicon dioxide hard mask for patterning and etching is provided, wherein tetra-ethyl-ortho-silane (TEOS) is used to deposit a silicon dioxide hard mask. (end of abstract)



Agent: Macpherson Kwok Chen & Heid LLP - San Jose, CA, US
Inventors: Tai-Peng Lee, Barbara Haselden
USPTO Applicaton #: 20070290292 - Class: 257506000 (USPTO)

Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Integrated Circuit Structure With Electrically Isolated Components, Including Dielectric Isolation Means

Use of teos oxides in integrated circuit fabrication processes description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20070290292, Use of teos oxides in integrated circuit fabrication processes.

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