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  Use of selective epitaxial silicon growth in formation of floating gatesUSPTO Application #: 20060208308Title: Use of selective epitaxial silicon growth in formation of floating gates Abstract: Apparatus utilizing epitaxial silicon growth on a base structure of a floating gate of a floating-gate memory cell to increase the available coupling area of the floating gate while reducing the spacing between adjacent memory cells. The epitaxial silicon growth facilitates a reduction in spacing between adjacent cells beyond the capability of the patterning technology, e.g., photolithography. (end of abstract) Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert - Minneapolis, MN, US Inventor: Roger W. Lindsay USPTO Applicaton #: 20060208308 - Class: 257315000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Variable Threshold (e.g., Floating Gate Memory Device), With Floating Gate Electrode The Patent Description & Claims data below is from USPTO Patent Application 20060208308. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001] This is a divisional application of U.S. patent application Ser. No. 10/886,078 (the '078 application), titled "USE OF SELECTIVE EPITAXIAL SILICON GROWTH IN FORMATION OF FLOATING GATES", filed Jul. 7, 2004 (pending), which application is assigned to the assignee of the present invention and the entire contents of which are incorporated herein by reference. TECHNICAL FIELD OF THE INVENTION [0002] The present invention relates generally to integrated circuit devices and, in particular, to the use of selective epitaxial silicon growth in the formation of floating gates for floating-gate transistors. BACKGROUND OF THE INVENTION [0003] Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address. [0004] One type of memory is a non-volatile memory known as Flash memory. A flash memory is a type of EEPROM (electrically-erasable programmable read-only memory) that generally can be erased and reprogrammed in blocks. Many modern personal computers (PCs) have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in wireless electronic devices because it enables the manufacturer to support new communication protocols as they become standardized and to provide the ability to remotely upgrade the device for enhanced features. [0005] A typical flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating-gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate. [0006] Flash memory typically utilizes one of two basic architectures known as NOR flash and NAND flash. The designation is derived from the logic used to read the devices. In NOR flash architecture, a column of memory cells are coupled in parallel with each memory cell coupled to a bit line. In NAND flash architecture, a column of memory cells are coupled in series with only the first memory cell of the column coupled to a bit line. [0007] Memory device fabricators are continuously seeking to increase productivity. One common approach is to place larger numbers of memory cells in a given amount of area, thus requiring smaller cells and/or closer spacing between cells. Smaller devices facilitate higher productivity and reduced power consumption. However, as device sizes become smaller, coupling area of the floating gate becomes increasingly critical. Additionally, it becomes increasingly difficult to reduce the spacing between adjacent floating gates. [0008] For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternate methods and device structures for providing increased coupling area in a floating gate of a memory cell. BRIEF DESCRIPTION OF THE DRAWINGS [0009] FIGS. 1A-1I are cross-sectional views of a portion of a memory array during various stages of fabrication in accordance with an embodiment of the invention. [0010] FIGS. 2A-2G are cross-sectional views of a portion of a memory array during various stages of fabrication in accordance with another embodiment of the invention. [0011] FIGS. 3A-3B are cross-sectional views of a portion of a memory array during various stages of fabrication in accordance with a further embodiment of the invention. [0012] FIG. 4 is a functional block diagram of a basic memory device in accordance with an embodiment of the invention coupled to a processor. DETAILED DESCRIPTION OF THE INVENTION [0013] In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that process or mechanical changes may be made without departing from the scope of the present invention. The terms wafer and substrate used previously and in the following description include any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and their equivalents. [0014] FIGS. 1A-1I generally depict a method of forming a portion of a memory array in accordance with an embodiment of the invention. FIG. 1A depicts a portion of the memory array after several processing steps have occurred. Formation of the type of structure depicted in FIG. 1A is well known and will not be detailed herein. In general, FIG. 1A depicts a substrate 105 upon which sacrificial layers 110 and 115 have been formed. For one embodiment, the substrate 105 is a monocrystalline silicon substrate. For a further embodiment, substrate 105 is a P-type monocrystalline silicon substrate. [0015] The sacrificial layers 110 and 115 will function as a hard mask during subsequent processing. For one embodiment, the first sacrificial layer 110 is an oxide layer. Oxide layer 110 could be formed, for example, through a thermal oxidation of a silicon-containing substrate 105. For one embodiment, the second sacrificial layer 115 is a silicon nitride layer. Silicon nitride layer 115 could be formed, for example, through a chemical vapor deposition (CVD) of a silicon nitride material. [0016] In FIG. 1B, the hard mask, i.e., sacrificial layers 110 and 115 are patterned. Patterning of such layers is well understood and will not be detailed herein. As one example, in a photolithographic process, a resist layer could be formed overlying the layers 110 and 115 and subsequently exposed and developed to produce a mask exposing portions of the layers 110 and 115. The exposed portions of the layers 110 and 115 could then be removed, such as by etching, to produce the structure of FIG. 1B. [0017] In FIG. 1C, portions of the substrate 105 exposed upon the removal of portions of the layers 110 and 115 are removed to define trenches 120 for future isolation regions. In FIG. 1D, the trenches 120 are filled with one or more dielectric materials, e.g., silicon dioxide and any excess is planarized, such as by chemical mechanical planarization (CMP), using the layer 115 as a stopping layer. This results in isolation regions 125 interposed between the areas of the substrate 105 covered by the layers 110 and 115. Such isolation, often referred to as shallow trench isolation (STI) is well known. [0018] In FIG. 1E, the sacrificial layers 110 and 115 are removed. As one example, a silicon oxide strip can first be performed to ensure that the silicon nitride layer 115 is devoid of any silicon oxide material left after the CMP process. The silicon nitride layer 115 is then removed, such as by etching. The oxide layer 110 is subsequently removed, such as by etching. Upon removal of the sacrificial layers 110 and 115, the structure of FIG. 1E may be obtained. For the example materials described with reference to this embodiment, it is expected that the corners of the isolation regions 125 will be recessed upon the removal of the layers 110 and 115. [0019] In FIG. 1F, a tunnel dielectric layer 130 is formed on the substrate 110. The tunnel dielectric layer 130 might be formed by thermal oxidation of the silicon substrate 105, forming the structure as depicted in FIG. 1F. Alternatively, the tunnel dielectric layer 130 could be formed by a blanket deposition of a dielectric material, such as by CVD or physical vapor deposition (PVD). Tunnel dielectric layer 130 is generally a silicon oxide, but may include other dielectric materials. Some specific examples include silicon oxides (SiO/SiO.sub.2), silicon nitrides (SiN/Si.sub.2N/Si.sub.3N.sub.4) and silicon oxynitrides (SiO.sub.xN.sub.y). Continue reading... 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