| Use of multiple etching steps to reduce lateral etch undercut -> Monitor Keywords |
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Use of multiple etching steps to reduce lateral etch undercutRelated Patent Categories: Semiconductor Device Manufacturing: Process, Chemical Etching, Vapor Phase Etching (i.e., Dry Etching), Utilizing Electromagnetic Or Wave Energy, By Creating Electric Field (e.g., Plasma, Glow Discharge, Etc.), Utilizing Multilayered MaskUse of multiple etching steps to reduce lateral etch undercut description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060211255, Use of multiple etching steps to reduce lateral etch undercut. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] The present application is a division of U.S. patent application Ser. No. 10/772,932 filed on Feb. 4, 2004, incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] The present invention relates to integrated circuits, and more particularly to reducing a lateral etch undercut. [0003] In an integrated circuit fabrication process, a layer of material (e.g. a conductive layer, a dielectric, or a semiconductor layer) can be patterned by an isotropic etch. A masked isotropic etch may involve an undercut--the etchant may etch the layer laterally under the mask. The undercut can be undesirable. There is a need to impede or eliminate the undercut etching. SUMMARY [0004] This section summarizes some features of the invention. Other features are described in the subsequent sections. The invention is defined by the appended claims which are incorporated into this section by reference. [0005] In some embodiments of the present invention, before an isotropic etch of a layer, another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the isotropic etch mask will not necessarily completely seal off the feature to be formed, but the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed. [0006] Whether or not the portion has been removed entirely or only partially, the extension of the isotropic etch mask beyond the feature can be shortened. [0007] The invention is not limited to isotropic or anisotropic etches. [0008] Other features and advantages of the invention are described below. The invention is defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS [0009] FIG. 1 is a circuit diagram of a nonvolatile memory according to one embodiment of the present invention. [0010] FIGS. 2A, 2B, 2C are top views of the memory of FIG. 1. [0011] FIGS. 2D, 2E, 2F show vertical cross sections of the memory of FIG. 1. [0012] FIGS. 3, 4A, 4B, 4C, 5A, 5B, 5C, 6A, 6B, 6C show vertical cross sections of memory structures in the process of fabrication according to some embodiments of the present invention. [0013] FIG. 7A is a top view of a memory structure according to an embodiment of the present invention. [0014] FIG. 7B shows a vertical cross section of a memory structure according to an embodiment of the present invention. [0015] FIG. 8A is a top view of a memory structure according to an embodiment of the present invention. [0016] FIGS. 8B, 8C, 8D, 8E, 8F show vertical cross sections of memory structures according to some embodiments of the present invention. [0017] FIGS. 9, 10 are top views of memory structures according to some embodiments of the present invention. DESCRIPTION OF SOME EMBODIMENTS [0018] The embodiments described in this section illustrate but do not limit the invention. The invention is not limited to particular materials, process steps, or dimensions. The invention is defined by the appended claims. [0019] FIG. 1 is a circuit diagram of a flash memory array which will be used to illustrate some embodiments of the present invention. FIG. 2A is a top view showing some features of the memory of FIG. 1. FIG. 2B is a top view of an array area which has contact openings to the wordlines. FIG. 2C shows another area near the array boundary, possibly overlapping with the area of FIG. 2B. FIG. 2D shows a vertical cross section marked Y1-Y1' in FIG. 2A. FIG. 2E shows a vertical cross section marked Y2-Y2' in FIGS. 2B and 2C. FIG. 2F shows a vertical cross section marked Y3-Y3' (FIG. 2C). Continue reading about Use of multiple etching steps to reduce lateral etch undercut... Full patent description for Use of multiple etching steps to reduce lateral etch undercut Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Use of multiple etching steps to reduce lateral etch undercut patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Use of multiple etching steps to reduce lateral etch undercut or other areas of interest. ### Previous Patent Application: Top patterned hardmask and method for patterning Next Patent Application: Porous underlayer film and underlayer film forming composition used for forming the same Industry Class: Semiconductor device manufacturing: process ### FreshPatents.com Support Thank you for viewing the Use of multiple etching steps to reduce lateral etch undercut patent info. IP-related news and info Results in 0.15618 seconds Other interesting Feshpatents.com categories: Canon USA , Celera Genomics , Cephalon, Inc. , Cingular Wireless , Clorox , Colgate-Palmolive , Corning , Cymer , 174 |
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