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  Ultra dense trench-gated power device with the reduced drain-source feedback capacitance and miller chargeUSPTO Application #: 20070040214Title: Ultra dense trench-gated power device with the reduced drain-source feedback capacitance and miller charge Abstract: The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate. (end of abstract) Agent: Hiscock & Barclay, LLP - Rochester, NY, US Inventor: Jun Zeng USPTO Applicaton #: 20070040214 - Class: 257330000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Short Channel Insulated Gate Field Effect Transistor, Gate Controls Vertical Charge Flow Portion Of Channel (e.g., Vmos Device), Gate Electrode In Groove The Patent Description & Claims data below is from USPTO Patent Application 20070040214. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of U.S. patent application Ser. No. 11/178,215 filed Jul. 8, 20005 which claims the benefit of U.S. Provisional Patent Application Ser. No. 60/274,760, filed Mar. 9, 2001 (expired), U.S. patent application Ser. No. 10/092,692 filed Mar. 7, 2002, now U.S. Pat. No. 6,683,346 and U.S. patent application Ser. No. 10/678,444 filed Oct. 1, 2003, now U.S. Pat. No. 6,929,988. FIELD OF THE INVENTION [0002] The present invention is directed to semiconductor devices and, more particularly, to a trench MOSFET with reduced Miller capacitance having improved switching speed characteristics. BACKGROUND OF THE INVENTION [0003] The semiconductor industry is witnessing an increasing demand for low-output-voltage DC-DC converters with very fast transient response and higher power efficiency for high frequency power conversion applications. When the operation frequency reaches 1 MHz or even higher, the power losses of a synchronous buck DC-DC converter will be dominated by the switching losses. Switching losses in a power MOSFET occur during charging/discharging the drain-gate feedback capacitance. The corresponding gate charge is called Miller Charge. Thus, the reduction of Miller capacitance is one of most important focus to improve DC-DC converter efficiency. [0004] Also, as the cell density and speed of a microprocessor increases, more current is needed to power the microprocessor. This means that the DC-DC converter is required to provide a higher output current. The increase of the output current raises the conduction loss of not only the lower switches but also the upper switches in synchronous DC-DC converter. Therefore, in order to power an advanced microprocessor, the power MOSFETS, which are used as the upper and the lower switches in a DC-DC converter must have both low switching power losses and low conduction power losses. The switching losses can be reduced by lowering on-resistance. Unfortunately, lowering the on-resistance raises the Miller capacitance. For example, in order to reduce the on-resistance of a power MOSFET, the most efficient way is to reduce the device cell pitch and increase the total channel width. Both of these result in an increase of the drain-gate overlay area. As the consequence, the device's Miller capacitance, or Miller charge increases. [0005] Due to gate to drain capacitance's significant impact on device switching speed, a series of improvements for minimizing it's impact have been proposed. These improvements include tailoring of source-drain ion implant angles and gate spacers, in order to obtain sufficient gate overlap of source-drains for maintaining low channel resistance, while still minimizing the associated capacitance values. One such effort to minimize Miller capacitance is a process step that locally increases the gate oxide thickness in the region of gate to drain overlap. However, that process is difficult to control because you need to maintain overlap while growing the thick oxide in the bottom of the trench and etching back. Therefore, what is needed is a method that will achieve low switching power losses and low conductivity power losses. SUMMARY OF THE INVENTION [0006] The present invention is directed towards a power device that has low switching power losses and low conductivity power losses. A power device having features of the present invention comprises a first substrate layer that is highly doped with a dopant of a first conductivity type, forming a drain. Over this first layer is a second layer that is lightly doped with the same conductivity dopant as the first layer. Above this second layer is a third layer, doped with a second conductivity dopant that is opposite in polarity to the first conductivity type. A fourth layer highly doped with the first conductivity dopant, is on the opposite surface of the semiconductor substrate. A trench extends from this fourth layer, into the second layer. This trench divides the fourth layer into a plurality of source regions. The trench also has sidewalls adjacent to the third and fourth layers for controlling a channel layer. Finally, this trench also has upper and lower conductive layers that are separated by a dielectric layer. [0007] According to another aspect of the invention, the upper conductive layer in the trench forms a gate electrode for controlling current through a channel adjacent the sidewall of the trench. The polysilicon gate layer, the polysilicon shield layer and the interlevel dielectric layer are suitably sized so that the bottom of the polysilicon gate layer is proximate the curvature of the well region. This will minimize the overlap between the gate and drain, and therefore minimize the gate-to-drain capacitance. [0008] According to still another aspect of the invention, the device originally described can have a source metal layer over the device and in electrical contact with the fourth layer, so that it is in contact with the source regions. This source metal also is in contact with the third layer doped with the second conductivity type. This metal layer will also be in contact with the lower conductive layer of the trench at peripheral locations around the cells of the device. The lower conductive layer, or shield layer, will be at the same electrostatic potential as the source. Now the capacitance at the bottom of the trench is no longer gate-to-drain it is now gate-to-source, because the shield is tied to the source. BRIEF DESCRIPTION OF THE DRAWINGS [0009] FIG. 1 is a cross-section of a DMOS cell structure. [0010] FIG. 1A is a table showing comparative results. [0011] FIG. 2 is a first graph showing gate voltage as a function of gate charge for new and conventional 0.2 micron cell pitch devices. [0012] FIG. 3 is a second graph similar to FIG. 2 for 0.3 micron cell pitch devices. [0013] FIG. 4 is an n-type doped epi-layer grown on the N+ substrate. [0014] FIG. 5 is pad oxidation followed by the Boron implant and annealing. [0015] FIG. 6 is LTO oxide deposition, followed by the LTO pattern definition by using photo-mask/etch steps. [0016] FIG. 7 is silicon etch to form the trench structure. [0017] FIG. 8. is LTO removal followed by Sacrificial Oxidation and Gate oxidation. [0018] FIG. 9 is polysilicon fill. [0019] FIG. 10 is polysilicon recess etch forming the polysilicon shield layer. Continue reading... Full patent description for Ultra dense trench-gated power device with the reduced drain-source feedback capacitance and miller charge Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Ultra dense trench-gated power device with the reduced drain-source feedback capacitance and miller charge patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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