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Trimming method and apparatus for voltage controlled delay loop with central interpolatorTrimming method and apparatus for voltage controlled delay loop with central interpolator description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060132206, Trimming method and apparatus for voltage controlled delay loop with central interpolator. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] The present invention is related to United States Patent Application entitled, "Voltage Controlled Delay Loop and Method with Injection Point Control," (Attorney Docket No. Freyman 15-23-37) and United States Patent Application entitled, "Voltage Controlled Delay Loop With Central Interpolator," (Attorney Docket No. Freyman 18-26-40-7), each filed on Nov. 30, 2004, and United States Patent Application entitled, "Phase Interpolator Having A Phase Jump," (Attorney Docket No. Freyman 16-24-38), filed contemporaneously herewith and each incorporated by reference herein. FIELD OF THE INVENTION [0002] The present invention is related to techniques for clock and data recovery (CDR) and, more particularly, to methods and apparatus for digital control of the generation and selection of different phases of a clock signal. BACKGROUND OF THE INVENTION [0003] In many applications, including digital communications, clock and data recovery (CDR) must be performed before data can be decoded. Generally, in a digital clock recovery system, a reference clock signal of a given frequency is generated together with a number of different clock signals having the same frequency but with different phases. In one typical implementation, the different clock signals are generated by applying the reference clock signal to a delay network. Thereafter, one or more of the clock signals are compared to the phase and frequency of an incoming data stream and one or more of the clock signals are selected for data recovery. [0004] A number of existing digital CDR circuits use voltage controlled delay loops (VCDL) to generate a number of clocks having the same frequency and different phase for data sampling (i.e., oversampling). For example, published International Patent Application No. WO 97/14214, discloses a compensated delay locked loop timing vernier. The disclosed timing vernier produces a set of timing signals of similar frequency and evenly distributed phase. An input reference clock signal is passed through a succession of delay stages. A separate timing signal is produced at the output of each delay stage. The reference clock signal and the timing signal output of the last delay stage are compared by an analog phase lock controller. The analog phase lock controller controls the delay of all stages so that the timing signal output of the last stage is phase locked to the reference clock. Based on the results of the oversampled data, the internal clock is delayed so that it provides data sampling adjusted to the center of the "eye." The phase of the VCDL is adjusted to keep up with phase deviations of the incoming data. [0005] While such voltage controlled delay loops effectively generate the sampling clocks and control the delay stages to maintain alignment of the reference clock signal and the last timing signal, they suffer from a number of limitations, which if overcome, could further improve the utility of such voltage controlled delay loops. For example, when the voltage controlled delay loops are implemented using integrated circuit technology, an inherent mismatch exists between the various delay stages, causing nonlinearities in the generated phases of the clock sources. A need therefore exists for a trimming method for a voltage controlled delay loop to compensate for such mismatched delay stages. SUMMARY OF THE INVENTION [0006] Generally, methods and apparatus are provided for trimming a desired delay element in a voltage controlled delay loop. The disclosed trimming process comprises the steps of obtaining a first phase signal of a reference clock; applying the first phase signal along a first path to the desired delay element and a common delay element connected in series to the desired delay element; applying the reference clock along a second path to a first delay element and the common delay element; measuring a delay difference between the first and second paths at an output of the common delay element; and adjusting a delay of the desired delay element based on the measured delay difference. [0007] The delay difference may be measured, for example, by applying the signals from the first and second paths to a data latch having a source of phase controlled data, such as a roaming tap interpolator. The delay of the desired delay element may be adjusted, for example, by setting one or more register control bits that adjust a tail current of the desired delay element. In a voltage controlled delay loop having a plurality of delay elements, the trimming method may be repeated for each delay element. [0008] A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0009] FIG. 1 illustrates an exemplary conventional clock recovery circuit; [0010] FIG. 2 illustrates the transitions in a data stream; [0011] FIG. 3 illustrates a VCDL having coarse phase control; [0012] FIG. 4 illustrates the nonlinearity of the delay as a function of the injection point for the VCDL of FIG. 3; [0013] FIG. 5 illustrates a VCDL providing coarse phase control and fine phase control provided by a central interpolator; [0014] FIG. 6 illustrates the nonlinearity of the delay as a function of the injection point for the VCDL of FIG. 5; [0015] FIG. 7 illustrates a VCDL incorporating features of the present invention; and [0016] FIG. 8 is a schematic block diagram of an exemplary roaming tap interpolator that provides a source of phase controlled data for the data latch of FIG. 7. DETAILED DESCRIPTION [0017] The present invention provides a trimming method for voltage controlled delay loops with digital phase control. FIG. 1 illustrates an exemplary conventional clock recovery circuit 100. As shown in FIG. 1, the clock recovery circuit 100 produces a clock signal with a predetermined number of phases, T.sub.0, S.sub.0, . . . T.sub.i, S.sub.i, discussed below in conjunction with FIG. 2. The exemplary clock recovery circuit 100 includes a reference clock signal (3 GHz, for example) generated by a phase locked loop (PLL) 110 and applied to the input of a voltage controlled delay loop 120. As shown in FIG. 1, the voltage controlled delay loop 120 interacts with two control loops 150, 160. The first phase control loop 150 is comprised of a VCDL phase detector 130, a digital filter 140 and a current steering DAC 145. Generally, the first control loop 150 adjusts the delays of the voltage controlled delay loop 120. The reference signal and the output of the VCDL 120 are applied to the VCDL phase detector 130 which provides phase detection by producing an output representative of the phase difference that is applied to a filter 140 whose digital output is converted to an analog current by the DAC 145 to control the delay in the stages of the voltage controlled delay loop 120. [0018] The second data control loop 160 is comprised of a preamplifier 165, a data sampling block 170, a data decimator 175, a parallel data and clock output block 180 and a second order proportional and integral (PI) filter 190. The serial data is received and amplified by the preamplifier 165 and applied to the data sampling block 170. The data sampling block 170 samples the data using the plurality of phases, T.sub.0, S.sub.0, . . . T.sub.i, S.sub.i. The data samples are then applied to the optional data decimator 175 that drops the data rate, for example, by a factor of two. In addition, the data sampling block 170 provides a recovered bit clock output that is applied to the data decimator 175, parallel data and clock output block 180 and second order PI filter 190. The parallel data and clock output block 180 outputs the sampled serial data and recovered lower frequency clock as parallel data (usually 16 or 20 bit wide) and clock. The second order PI filter 190 interprets the transition and data sample information associated with the, T.sub.0, S.sub.0, . . . T.sub.i, S.sub.i samples to generate phase control information for the VCDL 120. Generally, the phase control information ensures that the transitions clocks are maintained close to the transition points in the serial data (see FIG. 2). Continue reading about Trimming method and apparatus for voltage controlled delay loop with central interpolator... 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