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  Trenched mosfets with part of the device formed on a (110) crystal planeUSPTO Application #: 20060108635Title: Trenched mosfets with part of the device formed on a (110) crystal plane Abstract: This invention discloses an improved MOSFET devices manufactured with a trenched gate by forming part of the trench on a (110) crystal orientation of a semiconductor substrate. The trench is covering with a dielectric oxide layer along the sidewalls and the bottom surface or the termination of the trench formed along different crystal orientations of the semiconductor substrate. Special manufacturing processes such as oxide annealing process, special mask or SOG processes are implemented to overcome the limitations of the non-uniform dielectric layer growth. (end of abstract)
Agent: Bo-in Lin - Los Altos Hills, CA, US Inventors: Anup Bhalla, Sik K. Lui, Sung-Shan Tai USPTO Applicaton #: 20060108635 - Class: 257329000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Short Channel Insulated Gate Field Effect Transistor, Gate Controls Vertical Charge Flow Portion Of Channel (e.g., Vmos Device) The Patent Description & Claims data below is from USPTO Patent Application 20060108635. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The invention relates generally to the semiconductor power devices. More particularly, this invention relates to a novel and improved manufacture method and device configuration for a metal-oxide semiconductor field effect transistor (MOSFET) trenched power device manufactured with part of trench oriented on a (110) crystal plane of a silicon wafer. [0003] 2. Description of the Prior Art [0004] Even though the techniques to provide improved carrier mobility for a P-channel MOSFET, i.e., metal oxide silicon field effect transistors, by forming the transistor on a (110) crystal plane is known, the difficulties of high interface state density is still a limitation for practical implementation of such configurations. Specifically, Sze disclosed in "Physics of Semiconductor Devices" (Wiley-Interscience, 1969, pp. 16, pp. 473) and B. Goebel, D. Schumann, E. Bertagnolli disclosed in IEEE Trans. Electronics Devices, Vol. 48, No. 5, May 2001, pp. 897-906 that there is a thicker oxidation and higher interface state density along a (110) crystal plane. The thicker oxidation thus results in a thick gate oxide layer and lead to an adversely affected higher threshold voltage. [0005] Historically, the MOS devices are formed on the silicon wafer along a crystal orientation of a (100) plane because the oxide layer grown on a (100) plane has the lowest fixed charge and interface state density. For these reasons, the trench walls of the N-channel and P-channel of the trenched MOSFETs are typically oriented along the (100) plane as well. Specifically, for a N-channel device, the channel formed along the (100) orientation has the benefit for achieving higher channel mobility. In contrast, the oxide layer grown along the (110) plane has greater thickness and higher interface state density. A thicker oxide layer often leads to a higher threshold voltage and lower transconductance. Furthermore, measured data also provide some evidence that thicker oxide layer also causes a degradation of channel mobility. Due to these concerns, forming the MOSFET power devices using a (100) crystal orientation has become a common rule in the conventional design methods. However, there are potential benefits of forming the power MOSFET devices or at least part of the transistors on the (110) plane. These potential benefits are often ignored due to the common practice as typically carried out by those of ordinary skill in the art without further exploration. Furthermore, even when there are several U.S. patents and patent applications that explored the techniques of building the MOS devices on a semiconductor substrate having a (110) crystal orientation, these disclosures are still limited by several technique difficulties due to different practical configuration and manufacture constraints due to the oxide layer thickness variations along different crystal orientations as will be discussed below. [0006] In U.S. Pat. No. 4,933,298, entitled "Method of making high speed semiconductor device having a silicon-on-insulator structure", Hasegawa discloses a CMOS silicon-on-insulation structure fabricated by first forming an insulating SiO2 layer on a silicon substrate having a (110) plane. Openings are then formed in the SiO2 layer to expose a part of the substrate, and a polycrystalline or an amorphous silicon layer is deposited on the SiO2 layer and in the openings. The deposited silicon layer is divided into islands so that a first island includes one of the openings and a second island does not include any openings. A laser beam is then irradiated onto the islands so as to melt the islands, and when the laser light irradiation is discontinued, the melted islands recrystallize so that the first island forms a (110) plane and the second island forms a (100) plane. A p-channel MOSFET is fabricated on the first island, and an n-channel MOSFET is fabricated on the second island. The thus paired CMOS operates at high speeds, because the p-channel MOSFET using positive holes as the carrier is fast in a (110) crystal, and the n-channel MOSFET using electrons as the carrier is fast in a (100) crystal. Hasegawa disclose the benefits of building a p-channel MOSFET in a (110) crystal plane, however the configurations and method as disclosed would be too complicate and costly with limited merits for practical application to build a commercial MOSFET product. [0007] In another U.S. Pat. No. 6,245,615 entitled "Method and apparatus on (110) surfaces of silicon structures with conduction in the (110) direction" Noble et al. disclosed methods and structures that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the (110) direction for the purposed of achieving improvements in hole carrier mobility. The structure's channel is oriented in a (110) plane such that the electrical current flow is in the (110) direction. A method of forming an integrated circuit includes forming a trench in a silicon wafer with the trench wall oriented to have a (110) crystal plane orientation. A semiconductor device is also formed lateral to the trench wall such that the semiconductor device is capable of conducting an electrical current in a (110) direction. The method disclosed by Noble et al. provides for forming an integrated circuit including an array of MOSFETs and another method includes forming an integrated circuit including a number of lateral transistors. The disclosure also includes structures as well as systems incorporating such structures all formed according to the methods provided in this application. Noble's disclosures are however for a lateral device. A vertical trench MOS device would require different considerations. [0008] FIG. 1 shows a typical trench power MOSFET device that has its MOS channel vertically along the sidewall of a trench 10. The trench sidewall is covered by the gate dielectric 20, and is filled with the gate electrode material 30. Current flows from the source contact 40 to the drain contact 50, vertically down along the channel when the gate voltage is sufficient to connect the source and drain regions by an inversion layer of mobile carriers, e.g., electrons for n-channel and holes for p-channel. Many such cells operated in parallel form a power MOSFET. [0009] Table 1 shows the measured data that summarizes the characteristics of two identical P-channel MOSFETs next to each other on the same wafer, with the channel formed on (100) and (110) interfaces respectively on a (100) wafer. An (110) orientation on the trench sidewall where the channel is formed is achieved by simply rotating the FETs by 45 degrees as can be seen from FIG. 2. The results from two wafers are shown. The only difference in process between the two wafers is the duration of gate oxidation. TABLE-US-00001 Estimated Crystal Oxide Rds1 Rds2 Rds3 Orientation thickness Vth Vgs = 10 V Vgs = 4.5 V Vgs = 2.5 V Qg 100 250 .ANG. 0.99 V 0.37 Ohm 0.37 Ohm 0.37 Ohm 1.02 nC 110 330 .ANG. 1.33 V 0.31 Ohm 0.31 Ohm 0.31 Ohm 0.82 nC [0010] TABLE-US-00002 Estimated Crystal Oxide Rds1 Rds2 Orientation thickness Vth Vgs = 10 V Vgs = 4.5 V Qg 100 450 .ANG. 1.7 V 0.37 Ohm 0.83 Ohm 110 600 .ANG. 2.6 V 0.31 Ohm 0.78 Ohm It is clear from those measured data that there is a significant increase in threshold voltage, i.e., Vth, caused by the thicker oxide for (110) oriented device. However, there is a marked improvement in on-resistance, especially at higher gate bias, showing that there must have been a large improvement in the hole-channel mobility. [0011] Therefore, a need still exists in the art of MOSFET device design and manufacture to provide new design method and device configuration in forming the MOSFET channel along the (110) plane to achieve device performances. SUMMARY OF THE PRESENT INVENTION [0012] It is therefore an object of the present invention to provide a new design and manufacturing methods and device configuration for the power MOSFET devices to take advantages of building the devices on planes of different crystal orientations such that the limitations of the conventional methods can be overcome. [0013] Specifically, it is an object of the present invention to provide improved MOSFET devices manufactured with a trenched gate by forming part of the trench on a (110) crystal orientation of a semiconductor substrate. The trench is covering with a dielectric oxide layer along the sidewalls and the bottom surface or the termination of the trench formed along different crystal orientations of the semiconductor substrate. Special manufacturing processes such as oxide annealing process, special mask or SOG processes are implemented to overcome the limitations of the non-uniform dielectric layer growth. In a special preferred embodiment, forming the trenches with a stripe configuration, and choosing a different orientation of the seed crystal can produce an orientation of the trench with both sidewalls and bottom surface align along a (110) crystal orientation of the semiconductor substrate. [0014] Briefly in a preferred embodiment this invention discloses a trenched MOSFET power transistor that includes a gate disposed in a trench formed in a semiconductor substrate. The trench further includes sidewalls and a trench bottom surface all formed along a (110) crystal orientation of the semiconductor substrate. In a preferred embodiment, the MOSFET power transistor is a P-channel MOSFET power transistor. In a different preferred embodiment, this invention further discloses a trenched MOSFET power transistor comprising a gate disposed in a trench formed in a semiconductor substrate. The trench further includes sidewalls formed along a first crystal orientation of the semiconductor substrate and a trench bottom surface formed along a second crystal orientation of the semiconductor substrate different from the first crystal orientation. The trench further includes an oxide layer covering the sidewalls having a substantially the same thickness as an oxide layer covering the bottom surface of the trench. [0015] These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various drawing figures. BRIEF DESCRIPTION OF THE DRAWINGS [0016] FIG. 1 is a cross sectional view of a MOSFET device manufactured according to a process of this invention; [0017] FIG. 2 shows two identical MOSFETs next to each other on the same wafer, with the channel formed on (100) and (110) interfaces on the vertical sidewall respectively on a (100) wafer. [0018] FIGS. 3A and 3B are perspective views for showing the crystal orientations of a silicon ingot and the configuration of a trench; [0019] FIG. 4A to 4C are cross sectional views for showing the process to form the trench aligned along different crystal orientations of a semiconductor substrate; [0020] FIG. 5 is a perspective view for showing the termination tip of a trench to minimize the (100) plane effect; Continue reading... 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