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  Trench isolated capacitive micromachined ultrasonic transducer arrays with a supporting frameUSPTO Application #: 20080048211Title: Trench isolated capacitive micromachined ultrasonic transducer arrays with a supporting frame Abstract: A one or two-dimensional capacitive micro-machined ultrasonic transducer (CMUT) array with supporting frame is provided. The CMUT array has at least three array elements deposited on a conductive substrate. The invention also has at least one CMUT cell in the array element, a conductive top layer deposited to a top side of the element, and a conductive via disposed within the elements. The via is isolated from the conductive top layer and conducts with the substrate. There are at least two isolation trenches in the conductive substrate, and the trenches are disposed between adjacent vias to conductively isolating the vias. A substrate region between the trenches forms a mechanical support frame. At least one conductive electrode is deposited to a bottom surface of the conductive substrate, where the electrode conducts with the via. The support frame eliminates the need for a carrier wafer in the process steps. (end of abstract) Agent: Lumen Intellectual Property Services, Inc. - Palo Alto, CA, US Inventors: Butrus T. Khuri-Yakub, Xuefeng Zhuang, Arif Sanli Ergun USPTO Applicaton #: 20080048211 - Class: 257204000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Gate Arrays, Having Specific Type Of Active Device (e.g., Cmos) The Patent Description & Claims data below is from USPTO Patent Application 20080048211. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is cross-referenced to and claims the benefit from U.S. Provisional Patent Application 60/832,317 filed Jul. 20, 2006, which is hereby incorporated by reference. FIELD OF THE INVENTION [0003] The invention relates generally to ultrasonic transducers. More particularly, the invention relates to one-dimensional and two-dimensional trench isolated capacitive micro-machined ultrasonic transducer (CMUT) arrays built on a silicon-on-insulator (SOI) wafer having a supporting mesh frame using either wafer-bonding or sacrificial release methods. BACKGROUND [0004] In large, fully populated 1D and 2D transducer arrays, providing connection to each array element is a challenge. In the case of 2D CMUT arrays, researchers have reported on interconnect techniques both based on through-wafer vias and through wafer trench isolation. In the through-wafer via implementation, a conductive material, usually doped polysilicon, is used to fill the vias and serves as the conductor between the front and back sides of the array elements. It was found that after the deposition of the polysilicon, performing wafer-to-wafer fusion bonding is difficult. Therefore, the through-wafer via approach is limited to only surface micromachining CMUT processes. [0005] It has further been reported that in the trench isolation process, a carrier wafer is required during the deep reactive ion etching (DRIE) and the flip-chip bonding steps to provide the mechanical support for the membranes. This particular requirement presents certain drawbacks in processing. Good adhesion between the carrier wafer and the membrane surface is required for adequate mechanical support for the membranes. However, it is difficult to separate the carrier wafer and the membrane after the flip-chip bonding. The adhesive material may also swell in the solvent, creating stress that can break the CMUT membranes. It is highly desirable to eliminate the need of the carrier wafer for the trench isolation process. SUMMARY OF THE INVENTION [0006] A trench-isolated CMUT array with a supporting mesh frame for fully populated 1D and 2D arrays is provided. According to the current invention, the CMUT array is built on a silicon-on-insulator (SOI) wafer. Electrical interconnections to array elements are provided through the highly conductive silicon substrate. Neighboring array elements are separated from one another by trenches on both the device layer and the bulk silicon. A mechanically supporting frame is designed as a mesh structure between the silicon pillars providing electrical connections to the individual elements. The framed trench isolation is compatible with both wafer-bonded and surface-micromachined CMUTs. The invention eliminates the need for attaching the device wafer to a carrier wafer for the required mechanical support during the deep trench etching and flip-chip bonding steps, which presents difficulties during the release of the carrier wafer. [0007] According to one aspect of the invention, a one-dimensional or a two-dimensional capacitive micro-machined ultrasonic transducer (CMUT) array with supporting frame has at least three CMUT array elements deposited on a conductive substrate. The invention also has at least one CMUT cell in the array element, a conductive top layer deposited to a top side of the element, and a conductive via disposed within the elements. The via is isolated from the conductive top layer and conducts with the substrate. There are at least two isolation trenches in the conductive substrate, wherein the trenches are disposed between adjacent vias to conductively isolating the vias. A substrate region between the trenches forms a mechanical support frame, and at least one conductive electrode is deposited to a bottom surface of the conductive substrate, where the electrode is disposed to conduct with the via. [0008] In another aspect of the invention, the conductive substrate has a silicon-on-insulator wafer, where the wafer includes a silicon oxide layer on a silicon layer. [0009] In a further aspect of the invention, the conductive top layer is a conductive material such as aluminum, titanium, tungsten or polysilicon. [0010] In one aspect of the invention, the conductive top layer can be omitted when the top side of the element is as highly conductive silicon membrane. [0011] In a further aspect of the invention, the conductive via is a conductive material such as aluminum, polysilicon or amorphous silicon. [0012] In yet another aspect, the conductive electrode can be copper, titanium, gold, platinum, aluminum or nickel. [0013] The current invention includes a method of fabricating a one-dimensional or two-dimensional capacitive micro-machined ultrasonic transducer (CMUT) array with supporting frame. The method includes the steps of providing a double-side-polished silicon-on-insulator wafer, etching CMUT cavities in a device layer of the wafer using oxidation and buffered oxide etching methods, electrically dividing front electrical pads on the wafer using deep reactive ion etching, bonding a second silicon-on-insulator wafer to the etched device layer, removing a handle layer of the second silicon-on-insulator wafer, providing a contact via on each array element of the CMUT array using photo lithography and wet etching or dry etching, depositing a conductive top electrode material on the etched wafer, removing the conductive material around the vias to separate front and back electrodes from each other, etching through-wafer trenches on the silicon wafer for electrical isolation and to define a supporting frame, patterning signal electrodes on the back electrodes, and flip-chip bonding CMUT arrays to appropriate electronic circuits or printed circuit boards. [0014] In one aspect of the method of fabricating a one-dimensional or two-dimensional capacitive micro-machined ultrasonic transducer (CMUT) array with supporting frame, the wafer bonding steps are replaced with sacrificial layer releasing steps. BRIEF DESCRIPTION OF THE FIGURES [0015] The objectives and advantages of the present invention will be understood by reading the following detailed description in conjunction with the drawing, in which: [0016] FIG. 1 shows a schematic cross-section planar view of a prior art trench isolated CMUT without supporting frame. [0017] FIGS. 2a-2b show a schematic cross-section planar view and a perspective cutaway view of a trench isolated CMUT with supporting frame according to the present invention. [0018] FIG. 3 shows the calculated parasitic capacitance as a function of BOX layer thickness for a 200-.mu.m thick SOI wafer with a frame width of 30 .mu.m and a trench width of 30 .mu.m according to the present invention. [0019] FIG. 4 shows the measured and calculated parasitic capacitance values due to the frame structure of a trench isolated CMUT with supporting frame according to one embodiment of the invention. [0020] FIG. 5 shows the expected resistance values of an electrode for various substrate resistivities of a trench isolated CMUT with supporting frame according to one embodiment of the invention. Continue reading... Full patent description for Trench isolated capacitive micromachined ultrasonic transducer arrays with a supporting frame Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Trench isolated capacitive micromachined ultrasonic transducer arrays with a supporting frame patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. 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