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  Treatment of semiconductor wafersUSPTO Application #: 20080063872Title: Treatment of semiconductor wafers Abstract: A semiconductor wafer having a surface layer of semiconductor material that exhibits a reduced number of defects. This feature is achieved by a treatment method wherein the surface layer undergoes a chemical-mechanical polishing step, an intermediate step of cleaning the surface of the surface layer of semiconductor material using an SC1 solution, and then an RCA cleaning step. (end of abstract)
Agent: Winston & Strawn LLP Patent Department - Washington, DC, US Inventors: Stephane Coletti, Veronique Duquennoy-Pont USPTO Applicaton #: 20080063872 - Class: 428414000 (USPTO) Related Patent Categories: Stock Material Or Miscellaneous Articles, Composite (nonstructural Laminate), Of Epoxy Ether, As Intermediate Layer The Patent Description & Claims data below is from USPTO Patent Application 20080063872. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCED TO RELATED APPLICATIONS [0001] This application is a division of application Ser. No. 11/256,348 filed Oct. 20, 2005. FIELD OF INVENTION AND BACKGROUND ART [0002] The present invention relates to treating or cleaning the surface of a wafer in the form of a thin sheet having on its surface a layer of semiconductor material (e.g., silicon (Si) or silicon-germanium (SiGe)), such layer being termed a "useful layer", and constituting a medium from which large quantities of components (e.g., integrated circuit cells or discrete devices) can be produced. [0003] One known technique for fabricating such wafers is the Smart Cut.RTM. technique, which can be used to obtain an SOI (silicon on insulator) wafer, for example. An example of carrying out the SMART-CUT.RTM. technique applied to the production of SOI wafers is described in U.S. Pat. No. 5,374,564 or in the article by A. J. Auberton-Herve et al entitled "Why Can Smart-Cut Change the Future of Microelectronics?", Int Journal of High Speed Electronics and Systems, Vol 10, No 1, 2000, p 131-146. In general, the SMART-CUT.RTM. technique consists in implanting atomic species into an implantation zone beneath the face of a semiconductor wafer (e.g., Si or SiGe), in bringing the face of the wafer that has undergone implantation into intimate contact with a support substrate, and in cleaving the wafer at the implantation zone to transfer the portion of the wafer that is located between the implantation zone and the surface through which implantation has taken place onto the support substrate. [0004] Thus, a structure (e.g., a SOI structure) is obtained having a layer that has been transferred onto one face of a support substrate. After cleavage and transfer, the surface of the transferred layer is treated to remove part of the thickness of the implanted layer and to reduce the roughness of the cleavage surface. Examples of such treatments are described in United States patent application US 2004/115905 and International patent application WO 01/15215. Typically, the treatment comprises a polishing step followed by a cleaning step carried out prior to an optional final step of sacrificial oxidation and/or a smoothing heat treatment. The polishing step can reduce the root mean square (rms) roughness to less than 2.5 Angstroms (.ANG.) (e.g., 2 .ANG. rms) for a scan area (carried out using an atomic force microscope, for example) of 2 micrometers (.mu.m) by 2 .mu.m. [0005] More precisely, in a first step, polishing comprises a chemical-mechanical polishing step employing a polishing plate associated with a polishing solution containing both an agent for chemically attacking the surface of the layer and abrasive particles for mechanically attacking the surface, and a washing step, generally using deionized water (DIW). Thereafter, a cleaning step is carried out, consisting in treating the wafers with cleaning solutions. [0006] To clean the surfaces of wafers having a surface layer of semiconductor material, it is known to use a standard treatment known as "RCA" (because it was developed by Radio Corporation of America) and which comprises: [0007] a first cleaning step using an SC1 solution (Standard Clean 1) (or APM, Ammonium-Hydrogen Peroxide Mixture); containing ammonium hydroxide (NH.sub.4OH), hydrogen peroxide (H.sub.2O.sub.2), and deionized water (H.sub.2O); [0008] a second cleaning step using an SC2 solution (Standard Clean 2) (or (HPM, Hydrochloric Peroxide Mixture); containing hydrochloric acid (HCl), hydrogen peroxide (H.sub.2O.sub.2), and deionized water. [0009] The first solution, SC1, generally comprises 5 parts by volume water (H.sub.2O), 1 part by volume 27% ammonium hydroxide (NH.sub.4OH), and 1 part by volume 30% hydrogen peroxide (H.sub.2O.sub.2) and is generally used in the temperature range of 50.degree. C. to 80.degree. C., is principally intended to remove particles isolated on the surface of the wafer and particles buried close to the surface, as well as to render the surface hydrophilic. [0010] The second solution, SC2, generally used in the temperature range of 70.degree. C. to 90.degree. C., is principally intended to remove metallic contamination that has become deposited on the wafer surface, in particular by forming chlorides. [0011] For thin structures, i.e., structures such as SOI structures having a semiconductor useful layer of thickness of less than about 1000 .ANG., "HF" defect densities have been observed in the final products (i.e., after final sacrificial oxidation) which exceed the acceptable limits. "HF" defects are defects in the active semiconductor layer of the SOI structure that extend from the surface of the layer right into the buried oxide layer; their presence can be revealed by a ring pattern after treating the SOI structure with hydrofluoric acid (HF). The HF defect density observed for certain wafers may be as high as 15 defects per square centimeter (cm.sup.2), while the recommended limit value is typically of the order of 0.5 defects per cm.sup.2, or even less than 0.1 defects per cm.sup.2. [0012] HF defects are considered to be "destructive" defects for wafers, since they render them non viable (i.e., of unacceptable quality) for subsequent treatments, in particular for component formation. Thus, there is a need for cleaning procedures that reduce the number of HF defects in the final product. SUMMARY OF THE INVENTION [0013] The present invention also provides a wafer having at least a surface layer of semiconductor material, the surface layer having a thickness of less than 1000 .ANG., a roughness of less than 2.5 .ANG. rms for a scan area of 2 .mu.m.times.2 .mu.m, and an HF defect density of less than 0.5/cm.sup.2, or even less than 0.1/cm.sup.2. The wafer may be a silicon on insulator (SOI) structure. [0014] The surface layer of semiconductor material is preferably less than 1000 .ANG. thick, is generally formed from silicon (Si) or silicon-germanium (SiGe) and optionally constitutes the surface layer of an SOI or SGOI (SiGe on insulator) structure respectively fabricated using the SMART-CUT.RTM. technique. [0015] To achieve these features, the invention proposes a technical solution for layers of semiconductor material that have undergone a chemical-mechanical polishing step and an RCA cleaning step which can reduce the influence of the treatments on the emergence of HF defects, in particular during subsequent treatments, and as a result can reduce the HF defect density in the layers. [0016] This solution is achieved by a method of treating a wafer having at least a surface layer of semiconductor material, the surface of the surface layer having undergone a chemical-mechanical polishing step followed by an RCA cleaning step, in which method, after the polishing step and prior to the RCA cleaning step, implements an intermediate step of cleaning the surface of the surface layer of semiconductor material using an SC1 solution under concentration and temperature conditions that allow the subsequent emergence of defects (HF defects) to be reduced compared with a similar surface layer which has not undergone the intermediate cleaning step. [0017] As is described in detail below, it has been found that the HF defect density emerging during subsequent treatments (e.g., sacrificial oxidation) is much lower in a surface layer that has undergone an intermediate cleaning step in accordance with the invention than in a similar layer that has not undergone the step (i.e., having only undergone the polishing step and the RCA cleaning step). Without the intermediate cleaning step, defects form in the surface layer by preferential etching in the region of polishing contaminants or residues. The defects may be defects emerging on the surface of the layer; these are thus already HF defects. When the defects do not emerge, they may become emergent defects and, as a result, HF defects, during subsequent treatments such as during thinning by sacrificial oxidation, for example, which may transform a non emergent defect into an emergent defect as thinning is "conformal", i.e., material removal is constant over the surface regardless of the initial thickness. [0018] In one aspect of the invention, the SC1 solution comprises 1 volume of ammonium hydroxide (NH.sub.4OH), 4 volumes of hydrogen peroxide (H.sub.2O.sub.2), and 10 to 40 volumes of deionized water (H.sub.2O), the SC1 solution being used at a temperature of less than 50.degree. C. [0019] As an example, the SC1 solution may comprise 1 volume of ammonium hydroxide (NH.sub.4OH), 4 volumes of hydrogen peroxide (H.sub.2O.sub.2), and 20 volumes of deionized water (H.sub.2O) and be used at a temperature of 20.degree. C..+-.5.degree. C. [0020] The intermediate cleaning step may be carried out by immersing a wafer having the semiconductor useful layer in an SC1 solution. [0021] In a variation, the cleaning step is carried out using a polishing unit comprising a polishing head holding the wafer, the surface of the surface layer of semiconductor material of the wafer also being held in contact with a plate, the polishing unit including an injection line via which the SC1 solution is dispensed. Continue reading... Full patent description for Treatment of semiconductor wafers Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Treatment of semiconductor wafers patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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