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  Transistor fabrication methods using reduced width sidewall spacersUSPTO Application #: 20060019455Title: Transistor fabrication methods using reduced width sidewall spacers Abstract: Transistor fabrication methods (50) are presented in which shrinkable sidewall spacers (120) are formed (66, 68) along sides of a transistor gate (114), and a source/drain implant is performed (74) after forming the sidewall spacer (120). The sidewall spacer width is then reduced by annealing the shrinkable sidewall spacer material (76) following the source/drain implant (74). (end of abstract)
Agent: Texas Instruments Incorporated - Dallas, TX, US Inventors: Haowen Bu, PR Chidambaram, Rajesh Khamankar USPTO Applicaton #: 20060019455 - Class: 438303000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Self-aligned, Source Or Drain Doping, Utilizing Gate Sidewall Structure The Patent Description & Claims data below is from USPTO Patent Application 20060019455. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF INVENTION [0001] The present invention relates generally to semiconductor devices and methods for making the same. BACKGROUND OF THE INVENTION [0002] Current trends in the semiconductor industry include faster switching speeds, reduced power consumption, and lower operating voltages, wherein the performance of MOS transistors needs to be correspondingly improved. For example, high-speed transistors are required for modern wireless communications systems, portable computers, and other low-power, low-voltage devices, wherein MOS transistors must be adapted to operate at lower voltages using less power. Carrier mobility in a MOS transistor has a significant impact on power consumption and switching performance. The carrier mobility is a measure of the average speed of a carrier (e.g., holes or electrons) in a given semiconductor, given by the average drift velocity of the carrier per unit electric field. Improving the carrier mobility in the channel region of a MOS transistor can improve the switching speed, and can also facilitate operation at lower voltages, alone or in combination with reducing the transistor channel length and gate dielectric thickness to improve current drive and switching performance. [0003] Carrier mobility of a MOS transistor is affected by the mechanical stress in the device channel. The carrier mobility can be improved by depositing silicon/germanium alloy or other material layers between upper and lower silicon layers under compressive stress, in order to enhance hole carrier mobility in a channel region. For NMOS transistors, tensile stress in the channel material improves carrier mobility by lifting conduction band degeneracy. However, buried silicon/germanium channel layer devices have shortcomings, including increased alloy scattering in the channel region that degrades electron mobility, a lack of favorable conduction band offset which mitigates the enhancement of electron mobility, and the need for large germanium concentrations to produce strain and thus enhanced mobility. Furthermore, such additional alloy layers and silicon layers are costly, adding further processing steps to the device manufacturing procedure. [0004] Thus, there is a need for methods and apparatus by which the carrier mobility and other electrical operational properties of MOS transistor devices may be improved so as to facilitate improved switching speed and low-power, low-voltage operation, without significantly adding to the cost or complexity of the manufacturing process. SUMMARY OF THE INVENTION [0005] The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. [0006] The invention relates to methods for transistor fabrication, in which relatively wide sidewall spacers are provided along lateral sides of a transistor gate structure during deep source/drain implantation to control the location of the source/drains on either side of the transistor channel region, and the spacers are narrowed after the deep source/drain implant to facilitate the inducing enhanced stress in the transistor channel, to improve source/drain contact resistance, and to improve PMD gap fill. The invention may be employed in conjunction with stress inducing PMD liner material layers formed over the transistor after source/drain implantation, wherein the reduced sidewall spacer width facilitates inducing enhanced stress at the center of the transistor channel. [0007] In accordance with one aspect of the invention, a method is provided for fabricating a transistor, comprising forming a sidewall spacer along a side of a gate structure, implanting dopants into a source/drain region of a semiconductor body after forming the sidewall spacer, and reducing the sidewall spacer width after implanting the dopants. The spacer may be formed using a material that shrinks upon application of energy during processing following the source/drain implantation. In one implementation, a shrinkable sidewall spacer material is formed over the gate structure and over the source/drain region, and an etch process is performed, leaving a shrinkable sidewall spacer along the lateral side of the gate structure over a portion of the source/drain region. The spacer material may be thermally shrinkable silicon oxide, nitride, oxynitride, carbide, or Si.sub.WO.sub.XC.sub.YN.s- ub.Z with a non-zero hydrogen content, which can be deposited using low temperature chemical vapor deposition (CVD) processes, where the spacer is then shrunk or reduced by annealing after the source/drain implantation. A stress inducing material may then be formed over the transistor, wherein the reduced sidewall spacer width facilitates lower source/drain contact resistance and/or improved channel carrier mobility through induced stress in the semiconductor body. [0008] The following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. BRIEF DESCRIPTION OF THE DRAWINGS [0009] FIG. 1 is a simplified flow diagram illustrating an exemplary transistor fabrication method in accordance with the present invention; [0010] FIG. 2 is a detailed flow diagram illustrating an exemplary implementation of the invention using dual sidewall spacers; and [0011] FIGS. 3A-3L are partial side elevation views in section illustrating an exemplary integrated circuit with MOS transistors undergoing fabrication processing generally in accordance with the method of FIG. 2. DETAILED DESCRIPTION OF THE INVENTION [0012] One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale. [0013] The invention provides techniques for improving transistor performance by facilitating application of stress to improve carrier mobility, such as tensile stress provided to NMOS channel regions, and by source/drain contact resistance improvement. In one particular implementation illustrated and described hereinafter, a stress inducing PMD liner nitride film is formed over the transistor following silicide processing to impart stress in the transistors, where the liner protects the underlying transistors from a subsequently formed pre-metal dielectric (PMD) material and operates as an etch-stop layer in forming openings for contacts to transistor terminals through the PMD material. In accordance with the invention, a shrinkable sidewall spacer technique is employed to provide wide spacers during deep source/drain implantation, with a narrower (e.g., reduced width) spacer during silicide processing and PMD liner formation, by which the contact resistance of the silicide source/drain contact can be reduced, PMD gap fill can be improved, and by which the PMD liner has a greater impact on the stress level at the center of the transistor channel. [0014] The inventors have appreciated that it is desirable to increase carrier mobility throughout the length of the transistor channel, including the central portion of the channel, which may be accomplished by depositing certain stress inducing materials over the transistors. However, the inventors have found that the induced stress at any location in the semiconductor material varies with the distance between the stress inducing material and the semiconductor material. In the case where a PMD liner material is deposited over the transistor after silicide processing, the resulting stress at the central portion of the channel can be increased by reducing the distance from the PMD liner to the channel center. The invention provides techniques for reducing this distance, and hence increasing the stress effect at the channel center, by reducing the sidewall spacer width at the point where the PMD liner is formed during fabrication. [0015] The improved induced stress, in turn, results in improved carrier mobility and hence improved transistor drive current. In one example, reducing the sidewall spacer width from 700 .ANG. to 500 .ANG. results in about 20-25% increase in carrier mobility, leading to about 5-10% higher drive current. However, the inventors have further appreciated that merely decreasing the sidewall spacer width throughout fabrication processing may lead to unacceptable transistor leakage current because the sidewall spacer width also serves to set the lateral location of the deep source/drain dopants during implantation. Thus, if the sidewall spacers are too narrow during deep source/drain implantation, the dopants may diffuse too far under the gate (e.g., toward the center of the channel) during subsequent processing, which may cause higher transistor leakage current. [0016] Referring initially to FIG. 1, the invention accordingly provides fabrication methods in which initially wide sidewall spacers are provided during deep source/drain implantation, and the spacers are then narrowed prior to forming the stress inducing PMD liner, whereby improved transistor performance can be realized without adversely impacting leakage current. A method 2 is illustrated in FIG. 1 in accordance with the present invention. While the method 2 and other methods are illustrated and described below as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Furthermore, the methods according to the present invention may be implemented in association with the devices and systems illustrated and described herein as well as in association with other structures not illustrated. [0017] Beginning at 4, isolation processing and well formation are performed at 6 in the method 2, wherein any suitable isolation processing may be performed at 6, such as local oxidation of silicon (LOCOS) processing to form field oxide (FOX) isolation structures, shallow trench isolation (STI) processing, or other suitable techniques to form isolation structures between active regions of a semiconductor body. Patterned gate structures are then formed at 8 over channel regions of the semiconductor body. The invention may be employed in fabricating transistors with any suitable gate structure, such as a thin gate dielectric (e.g., oxides such as SiO.sub.2, or other dielectric material) formed over the semiconductor channel, with an overlying conductive gate (e.g., doped polysilicon, metal, or stacks or multi-layer gate contact structures), which are formed at 8 by any suitable means, such as deposition of the gate dielectric and gate contact layers, followed by etching to define the patterned gate structure. At 10, a drain extension implant is performed to initially dope a shallow portion of prospective source/drain regions on either side of the channel. Any suitable drain extension implant may be performed at 10, including but not limited to lightly-doped-drain (LDD) implants, moderately-doped-drain (MDD) implants, etc. [0018] Shrinkable sidewall spacers are formed at 12 along lateral sides of the patterned gate structures. As described further below with respect to FIGS. 2 and 3A-3L, the sidewall spacers may be formed at 12 of high shrinkage material using low temperature deposition techniques, thereby providing shrinkable sidewall spacers that may be controllably reduced in size (e.g., narrowed) upon application of thermal or other types of energy. Deep source/drain implantation is performed at 14 to further define the source/drain regions with the spacers in place, after which the width of the sidewall spacers is reduced at 16, such as during source/drain implant activation annealing. Silicide is then formed at 18 over the source/drains and the gate contact, and a PMD liner is formed at 20 to impart stress in the transistor for carrier mobility improvement. A PMD dielectric material layer is then formed over the liner at 22 and conductive contacts are formed at 24 through select portions of the PMD layer to provide electrical connection to the transistor gate and source/drains. Interconnect metallization and other back end processing is then performed at 26 to complete the device, and the method 2 ends at 28. [0019] Referring now to FIGS. 2 and 3A-3L, FIG. 2 illustrates an exemplary detailed method 50 in accordance with the invention where shrinkable sidewall spacers are employed to provide relatively wide spacers during deep source/drain implantation (e.g., to control the lateral location of the source/drains and hence to control transistor leakage current) and to subsequently provide narrowed spacers during silicidation and PMD liner formation (e.g., to improve contact resistance, PMD gap fill, and carrier mobility). FIGS. 3A-3L illustrate an exemplary integrated circuit device 102 with MOS transistors undergoing fabrication processing generally in accordance with the method 50 of FIG. 2. Continue reading... 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