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  Tracker architecture for gps systemsUSPTO Application #: 20070008218Title: Tracker architecture for gps systems Abstract: A tracker architecture for Global Positioning System (GPS) receivers is disclosed. A typical tracker comprises an RF front end and GPS architecture. The architecture comprises a bus structure, a Central Processing Unit (CPU) core, cache, RAM, and ROM memories, and a GPS engine that comprises a receiving, tracking, and demodulating engine for GPS and Wide Area Augmentation Service (WAAS) signals. The GPS architecture can couple to at least two different protocol interfaces via the bus structure, where the protocol interfaces are commonly used in different applications. (end of abstract) Agent: The Eclipse Group - Granada Hills, CA, US Inventors: Nicolas Vantalon, Leon Kuo-Liang Peng, Gregory Turetzky USPTO Applicaton #: 20070008218 - Class: 342357120 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20070008218. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application claims priority under 35 U.S.C. 119(e) of U.S. Provisional Patent Application No. 60/306,620, filed Jul. 18, 2001, entitled "TRACKER ARCHITECTURE FOR GPS SYSTEMS," by Nicolas Vantalon et al., which application is incorporated by reference herein. [0002] This application is also related to U.S. Pat. No. 5,901,171, by Sanjai Kohli et al., entitled "TRIPLE MUTIPLEXING SPREAD SPECTRUM RECEIVER," and related to U.S. Pat. No. 6,278,403, by Leon Kuo-Liang Peng et al, entitled "AUTONOMOUS HARDWIRED TRACKING LOOP COPROCESSOR FOR GPS AND WAAS RECEIVER," both of which applications are hereby incorporated by reference herein. BACKGROUND OF THE INVENTION [0003] 1. Field of the Invention [0004] The present invention relates in general to Global Satellite System (GSS) receivers, and in particular to a tracker architecture for Global Positioning System (GPS) systems. [0005] 2. Description of the Related Art [0006] Currently, there are many GPS systems available that can acquire, track, and navigate using GPS signals. However, the navigation and tracking architectures for these systems vary widely. Many of these systems are not optimized for tracking or navigation, and are designed to work with only one type of GPS system. SUMMARY OF THE PRESENT INVENTION [0007] To minimize the limitations in the prior art described above, and to minimize other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses, a tracker architecture for Global Positioning System (GPS) receivers. An architecture in accordance with the present invention comprises a bus structure, a Central Processing Unit (CPU) core, cache, RAM, and ROM memories, and a GPS engine that comprises a receiving, tracking, and demodulating engine for GPS and Wide Area Augmentation Service (WAAS) signals. The GPS architecture can couple to at least two different protocol interfaces via the bus structure, where the protocol interfaces are commonly used in different applications. [0008] The present invention is a member of digital signal processors used for a GPS navigation architecture. The present invention is built on a state-of-the-art, low power, 0.18 micron CMOS process. This highly integrated design includes a compatible GPS/WAAS (wide area augmentation signal) Digital Signal Processor (DSP) engine, Satellite Signal Tracking Engine (SSTE), BEACON DSP, ARM microprocessor, real time counter (RTC), dual UART, interrupt controller, ROM, SRAM, on-chip ADC, Multiple serial interfaces (including I2C, USB, CAN, J1850 and SPI), two-way associate cache, and bus interface unit (BIU). [0009] The present invention provides the architecture flexibility to support all GPS market segments: Cellular Phone, Car Navigation, GPS Hand-helds, Consumer Electronics, PC accessory and others, because the present invention integrates the CPU core, memory, GPS engine and other system peripherals. As a minimum system configuration, a receiver can comprise an RF front-end, and the present invention, which is used as a backend digital component. The present invention also has extra computing power to run applications other than GPS tracking and navigation. The present invention is fully compatible with many types of tracking and navigation software. BRIEF DESCRIPTION OF THE DRAWINGS [0010] Referring now to the drawings in which like reference numbers represent corresponding parts throughout: [0011] FIG. 1 illustrates an architecture in accordance with the present invention. DETAILED DESCRIPTION OF THE DRAWINGS [0012] In the following description of the preferred embodiment, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention. Overview [0013] When integrating GPS components and receivers with other electronics, e.g., cellular telephones, automotive systems, etc., the GPS components must be readily compatible with such systems and still retain the ability to acquire and track the GPS satellites under the conditions presented by each of the environments that the GPS components will be introduced into. The present invention combines the systems typically present in a GPS baseband tracker architecture, and provides a single, multi-function interface that is compatible with several different protocols, such that a baseband processor made using the tracker architecture of the present invention can be used in several different applications. [0014] A baseband processor used in the tracker architecture of the present invention typically is manufactured using a 0.18 micron low power CMOS process. This allows for smaller die sizes, as well as low power consumption. [0015] The present invention allows for different operating voltages, typically 3.3 volts, 2.5 volts, or 1.8 volts dc. These voltages are used not only for the baseband processor, but also for the Real Time Clock (RTC) and for the I/O drivers used with the architecture of the present invention. To conserve power, the internal core typically operates at 1.8 volts, so that the processor and other integrated portions of the present invention use as little power as possible. Further, the present invention operates over a wide range of temperatures, typically -40 to +85 degrees Centigrade, and also meets the QS9000 standard for semiconductor circuit manufacture. Block Diagram [0016] FIG. 1 illustrates a block diagram of the present invention. Appendix A illustrates some sample terms used throughout this disclosure and in FIG. 1. Appendix B illustrates the input/output description of the present invention. [0017] Architecture 100 of the present invention is shown with several components described below. Continue reading... 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