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  Top layers of metal for high performance ic'sUSPTO Application #: 20070288880Title: Top layers of metal for high performance ic's Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance. (end of abstract) Agent: Saile Ackerman LLC - Poughkeepsie, NY, US Inventor: Mou-Shiung Lin USPTO Applicaton #: 20070288880 - Class: 716013000 (USPTO) Related Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, Routing (e.g., Routing Map, Netlisting), Global Routing (e.g., Shortest Path, Dead Space, Or Duplicate Trace Elimination) The Patent Description & Claims data below is from USPTO Patent Application 20070288880. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This application is a continuation of application Ser. No. 11/230,102, filed on Sep. 19, 2005, now pending, which is a continuation of application Ser. No. 11/121,477, filed on May 4, 2005, now pending, which is a continuation of application Ser. No. 10/389,543, filed on Mar. 14, 2003, now U.S. Pat. No. 6,965,165, which is a division of application Ser. No. 09/972,639, filed on Oct. 9, 2001, now U.S. Pat. No. 6,657,310, which is a division of application Ser. No. 09/251,183, filed on Feb. 17, 1999, now U.S. Pat. No. 6,383,916, which is a continuation-in-part of application Ser. No. 09/216,791, filed on Dec. 21, 1998, now abandoned. BACKGROUND OF THE INVENTION [0002] (1) Field of the Invention [0003] The invention relates to the manufacturing of high performance Integrated Circuit (IC's), and more specifically to methods of achieving high performance of the Integrated Circuits by reducing the parasitic capacitance and resistance of inter-connecting wiring on a chip. [0004] (2) Description of the Prior Art [0005] When the geometric dimensions of the Integrated Circuits are scaled down, the cost per die is decreased while some aspects of performance are improved. The metal connections which connect the Integrated Circuit to other circuit or system components become of relative more importance and have, with the further miniaturization of the IC, an increasingly negative impact on the circuit performance. The parasitic capacitance and resistance of the metal interconnections increase, which degrades the chip performance significantly. Of most concern in this respect is the voltage drop along the power and ground buses and the RC delay of the critical signal paths. Attempts to reduce the resistance by using wider metal lines result in higher capacitance of these wires. [0006] To solve this problem, the approach has been taken to develop low resistance metal (such as copper) for the wires while low dielectric materials are used in between signal lines. Increased Input-Output (IO) combined with increased demands for high performance IC's has led to the development of Flip Chip Packages. Flip-chip technology fabricates bumps (typically Pb/Sn solders) on Al pads on chip and interconnect the bumps directly to the package media, which are usually ceramic or plastic based. The flip-chip is bonded face down to the package medium through the shortest path. These technologies can be applied not only to single-chip packaging, but also to higher or integrated levels of packaging in which the packages are larger and to more sophisticated substrates that accommodate several chips to form larger functional units. [0007] The flip-chip technique, using an area array, has the advantage of achieving the highest density of interconnection to the device and a very low inductance interconnection to the package. However, pre-testability, post-bonding visual inspection, and TCE (Temperature Coefficient of Expansion) matching to avoid solder bump fatigue are still challenges. In mounting several packages together, such as surface mounting a ceramic package to a plastic board, the TCE mismatch can cause a large thermal stress on the solder-lead joints that can lead to joint breakage caused by solder fatigue from temperature cycling operations. [0008] U.S. Pat. No. 5,212,403 (Nakanishi) shows a method of forming wiring connections both inside and outside (in a wiring substrate over the chip) for a logic circuit depending on the length of the wire connections. [0009] U.S. Pat. No. 5,501,006 (Gehman, Jr. et a].) shows a structure with an insulating layer between the integrated circuit (IC) and the wiring substrate. A distribution lead connects the bonding pads of the IC to the bonding pads of the substrate. [0010] U.S. Pat. No. 5,055,907 (Jacobs) discloses an extended integration semiconductor structure that allows manufacturers to integrate circuitry beyond the chip boundaries by forming a thin film multi-layer wiring decal on the support substrate and over the chip. However, this reference differs from the invention. [0011] U.S. Pat. No. 5,106,461 (Volfson et al.) teaches a multi layer interconnect structure of alternating polyimide (dielectric) and metal layers over an IC in a TAB structure. [0012] U.S. Pat. No. 5,635,767 (Wenzel et al.) teaches a method for reducing RC delay by a PBGA that separates multiple metal layers. [0013] U.S. Pat. No. 5,686,764 (Fulcher) shows a flip chip substrate that reduces RC delay by separating the power and I/O traces. SUMMARY OF THE INVENTION [0014] It is the primary objective of the present invention to improve the performance of High Performance Integrated Circuits. [0015] Another objective of the present invention is to reduce resistive voltage drop of the power supply lines that connect the IC to surrounding circuitry or circuit components. [0016] Another objective of the present invention is to reduce the RC delay constant of the signal paths of high performance IC's. [0017] Yet another objective of the present invention is to facilitate the application of IC's of reduced size and increased circuit density. [0018] Yet another objective of the present invention is to further facilitate and enhance the application of low resistor conductor metals. [0019] Yet another objective of the present invention is to allow for increased I/O pin count for the use of high performance IC's. [0020] Yet another objective of the present invention is to simplify chip assembly by reducing the need for re-distribution of I/O chip connections. [0021] Yet another objective of the present invention is to facilitate the connection of high-performance IC's to power buses. [0022] Yet another objective of the present invention is to facilitate the connection of high-performance IC's to clock distribution networks. Continue reading... Full patent description for Top layers of metal for high performance ic's Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Top layers of metal for high performance ic's patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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