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  Three-dimensional multi-gate device and fabricating method thereofUSPTO Application #: 20070164325Title: Three-dimensional multi-gate device and fabricating method thereof Abstract: A three-dimensional multi-gate device has a silicon fin, a gate structure, and a stress-adjusting layer. The gate structure contacts with three surface of the silicon fin to form a three-dimensional gate structure. The stress-adjusting layer is disposed on the gate structure to provide stress along the direction parallel to the channel length of the gate structure. The stress helps promote the mobility of the charges in the channel region under the gate structure and improve the electrical performance such as drive current and DIBL of the three-dimensional multi-gate device. (end of abstract) USPTO Applicaton #: 20070164325 - Class: 257278000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Junction Field Effect Transistor (unipolar Transistor), Junction Field Effect Transistor In Integrated Circuit, With Devices Vertically Spaced In Different Layers Of Semiconductor Material (e.g., "3-dimensional" Integrated Circuit)
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