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Three-dimensional multi-gate device and fabricating method thereofRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Junction Field Effect Transistor (unipolar Transistor), Junction Field Effect Transistor In Integrated Circuit, With Devices Vertically Spaced In Different Layers Of Semiconductor Material (e.g., "3-dimensional" Integrated Circuit)Three-dimensional multi-gate device and fabricating method thereof description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070164325, Three-dimensional multi-gate device and fabricating method thereof. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of application Ser. No. 11/161,950 filed Aug. 23, 2005. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a three-dimensional multi-gate device and a fabricating method thereof, and more particularly, to a three-dimensional multi-gate device having a stress-adjusting layer and a fabricating method thereof. [0004] 2. Description of the Prior Art [0005] With increasing miniaturization of semiconductor devices, various three-dimensional multi-gate devices have been developed. The three-dimensional multi-gate device is advantageous for the following reasons. First, the manufacturing processes of three-dimensional multi-gate devices can be integrated into the traditional logic device processes, and thus are more compatible. Furthermore, due to the structural particularity of the three-dimensional multi-gate device, traditional shallow trench isolation is not required. In addition, since the three-dimensional structure increases the overlapping area between the gate and the substrate, the channel region is more effectively controlled. This therefore reduces drain-induced barrier lowering (DIBL) effect and short channel effect. Moreover, the channel region is longer under the same gate length. Therefore, the current between the source and the drain is increased. [0006] Although the three-dimensional multi-gate device is advantageous for many reasons, the carrier mobility still requires to be improved. SUMMARY OF THE INVENTION [0007] It is therefore one of the objects of the claimed invention to provide a three-dimensional multi-gate device and a fabricating method thereof to solve the aforementioned problems. [0008] According to the claimed invention, a three-dimensional multi-gate device is disclosed. The three-dimensional multi-gate structure has a semiconductor substrate; a silicon fin disposed on the semiconductor substrate, the silicon fin having a top surface and two side surfaces; a gate structure disposed on the silicon fin and partially covering the top surface and the two side surfaces of the silicon fin; two doped regions disposed in the silicon fin under both sides of the gate structure; and a stress-adjusting layer covering the gate structure. [0009] According to the claimed invention, a method for fabricating a three-dimensional multi-gate device is also disclosed. The method includes the following steps: [0010] (a) providing a semiconductor substrate and forming a silicon fin on the semiconductor substrate, the silicon fin having a top surface and two side surfaces; [0011] (b) forming a gate structure on the silicon fin, the gate structure partially covering the top surface and the two side surfaces of the silicon fin; [0012] (c) forming two doped regions in the silicon fin under both sides of the gate structure; and [0013] (d) forming a stress-adjusting layer covering the gate structure. [0014] The three-dimensional multi-gate device according to the claimed invention features the stress-adjusting layer. The stress-adjusting layer provides the gate structure with stress through a direction parallel to the length of the channel, such that the carrier mobility in the channel region under the gate structure is raised and the electrical performance of the device is improved. [0015] These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0016] FIG. 1 through FIG. 9 are schematic diagrams illustrating a method for fabricating a three-dimensional multi-gate device according to a preferred embodiment of the present invention. [0017] FIG. 10 illustrates the I.sub.off versus I.sub.on curve of the three-dimensional multi-gate device of the present invention and a traditional three-dimensional multi-gate device. [0018] FIG. 11 illustrates the carrier mobility of the three-dimensional multi-gate device of the present invention and a traditional three-dimensional multi-gate device. [0019] FIG. 12 illustrates the DIBL effect of the three-dimensional multi-gate device of the present invention and a traditional three-dimensional multi-gate device. DETAILED DESCRIPTION Continue reading about Three-dimensional multi-gate device and fabricating method thereof... Full patent description for Three-dimensional multi-gate device and fabricating method thereof Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Three-dimensional multi-gate device and fabricating method thereof patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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