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  Three-dimensional memory devicesUSPTO Application #: 20060208304Title: Three-dimensional memory devices Abstract: Memory devices are disclosed. One example of a memory device may include two layers of memory arrays each containing at least four memory cells. In particular, the memory device includes two word lines commonly shared by the two layers of the memory arrays, with the word lines coupled with the memory cells and providing gate regions of the memory cells. Additionally, a first pair of bit lines cross under the two word lines and providing source and drain regions to the first layer of the two layers of the memory arrays, and a second pair of bit lines cross over the two word lines and providing source and drain regions to the second layer of the two layers of the memory arrays. A first set of channel regions are disposed between the source and drain regions to the first layer of the two layers of the memory arrays, and a second set of channel regions are disposed between the source and drain regions to the second layer of the two layers of the memory arrays. In addition, charge storage regions are provided with each of them disposed between a corresponding word line and a corresponding channel region. (end of abstract) Agent: Akin Gump Strauss Hauer & Feld L.L.P. - Philadelphia, PA, US Inventor: Ming Hsiu Lee USPTO Applicaton #: 20060208304 - Class: 257314000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Variable Threshold (e.g., Floating Gate Memory Device) The Patent Description & Claims data below is from USPTO Patent Application 20060208304. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application claims priority to U.S. Provisional Application No. 60/663,866, entitled "Three-Dimensional Memory Devices and Method of Manufacturing and Operating the Same", filed Mar. 21, 2005. BACKGROUND OF THE INVENTION [0002] The invention relates to memory devices, and, specifically, relates to three-dimensional memory devices. [0003] Generally, non-volatile memory devices may implement various design features. One of them includes a so-called SONOS (silicon-oxide-nitride-oxide-silicon) design, which may use a thin tunnel oxide to allow direct-tunneling erase. FIG. 1 illustrates an example of a SONOS non-volatile memory device. Referring to FIG. 1, the memory device may include a source region 10 and a drain region 12, an active or channel region 14, a gate dielectric layer 16 over the active region 14, and a gate 18 over the gate dielectric layer 16. Generally, the active region 14 may be formed adjacent to, such as over or between, the source and drain regions 10 and 12. And the gate dielectric 16 may have an "ONO" structure having two silicon oxide layers with a silicon nitride layer in-between. [0004] Conventional memory devices provide memory cells or storage units in a two-dimensional design to facilitate operation. However, with the development of portable and many other devices requiring a large number of memory cells within a limited chip space, there is a need for non-volatile memory devices that can provide more memory cells within a limited space. BRIEF SUMMARY OF THE INVENTION [0005] Examples consistent with the invention disclose memory devices. A memory device may include a first pair of bit lines; a first pair of word lines over the first pair of bit lines and configured to cross over the first pair of bit lines; and a first pair of channel regions substantially parallel with the first pair of word lines and each disposed at least between the locations where a corresponding word line of the first pair of word lines crosses over the first pair of bit lines and disposed between the corresponding word line and the first pair of bit lines. Additionally, the memory device may include a first set of charge storage regions each disposed at least between the corresponding word line and a corresponding channel region of the first pair of channel regions; a second pair of bit lines over the first pair of word lines and configured to cross over the first pair of word lines; and a second pair of channel regions substantially parallel with the first pair of word lines and each disposed at least between the locations where the second pair of bit lines cross over the corresponding word line and disposed between the second pair of bit lines and the corresponding word line. Furthermore, a second set of charge storage regions may be provided with each of them disposed at least between the corresponding word line and the corresponding channel region. [0006] Examples consistent with the invention further disclose an alternative configuration of memory devices. A memory device may include two layers of memory arrays each containing at least four memory cells; two word lines commonly shared by the two layers of the memory arrays, the word lines coupled with the memory cells and providing gate regions of the memory cells; a first pair of bit lines crossing under the two word lines and providing source and drain regions to a first layer of the two layers of the memory arrays; and a second pair of bit lines crossing over the two word lines and providing source and drain regions to a second layer of the two layers of the memory arrays. Additionally, the memory device may include a first set of channel regions disposed between the source and drain regions to the first layer of the two layers of the memory arrays; a second set of channel regions disposed between the source and drain regions to the second layer of the two layers of the memory arrays; and charge storage regions each disposed between a corresponding word line of the two word lines and a corresponding channel region of the first and second sets of channel regions. [0007] Examples consistent with the invention further disclose further other alternative configurations of memory devices. A memory device may include: two layers of memory arrays each containing at least four memory cells; two bit lines commonly shared by the two layers of the memory arrays, the bit lines coupled with the memory cells and providing source and drain regions of the memory cells; a first pair of word lines crossing under the two bit lines and providing gate regions to a first layer of the two layers of the memory arrays; and a second pair of word lines crossing over the two bit lines and providing gate regions to a second layer of the two layers of the memory arrays. The memory device may further include: channel regions disposed between the source and drain regions; and charge storage regions each disposed between a corresponding word line of the first and second pairs of word lines and a corresponding channel region of the channel regions. BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS [0008] The foregoing summary, as well as the following detailed description of the invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there are shown in the drawings embodiments which are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown. [0009] In the drawings: [0010] FIG. 1 illustrates a cross-sectional view of an exemplary memory device in the prior art. [0011] FIG. 2 illustrates an exemplary structure of a TFT (thin-film transistor) memory cell in examples consistent with the invention. [0012] FIG. 3 illustrates another exemplary configuration of a TFT memory cell in examples consistent with the invention. [0013] FIG. 4 illustrates sandwiched structures for a gate line, source line, drain line, and inhibit line in examples consistent with the invention. [0014] FIGS. 5a-5f illustrate exemplary structures of three-dimensional memory devices in examples consistent with the invention. [0015] FIGS. 6a and 6b illustrate exemplary memory arrays provided by three dimensional memory devices in examples consistent with the invention. DETAILED DESCRIPTION OF THE INVENTION [0016] Examples consistent with the invention disclose three-dimensional memory devices. The memory device may use thin-film-transistor memory cells having a charge storage region. The memory cells may be organized in planes each having a two-dimensional memory array, and the planes may be stacked vertically for providing multiple layers of memory arrays to form a three-dimensional memory device. In some examples, the neighboring planes of memory arrays may share common gate regions (or word lines) or common source and drain regions (or bit lines). Accordingly, examples consistent with the invention may provide a large number of memory cells or storage units within a limited area or substrate area compared to traditional memory arrays. [0017] In some examples, silicon nitride may be used as a charge-storage or charge-trapping region for thin-film-transistor ("TFT") memory devices. Nitride-storage TFTs may provide programmable and erasable devices, and the devices can be used for various applications, such as for one-time programmable memory (OTP), multiple-time programmable memory (MTP), or FLASH memory devices allowing numerous cycles of programming and erasing operations. [0018] Additionally, a non-volatile memory, such as a SONOS memory, may allow programming and erasing operations in various different ways. For example, a program or erase (P/E) operation may change the threshold voltage of a memory cell, thereby indicating a different status of one or more bits of stored data. [0019] In one example, nitride storage TFTs, such as SONOS TFT, may be organized in memory arrays and stacked over each other. For example, layers of bit lines and word lines may cross with each other to provide memory cells in a three-dimensional structure. Accordingly, a memory device may provide a large amount of storage cells within a limited space. Continue reading... Full patent description for Three-dimensional memory devices Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Three-dimensional memory devices patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. 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