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  Three dimensional device integration method and integrated deviceUSPTO Application #: 20060292744Title: Three dimensional device integration method and integrated device Abstract: A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures. (end of abstract) Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C. - Alexandria, VA, US Inventors: Paul M. Enquist, Gaius Fountain USPTO Applicaton #: 20060292744 - Class: 438107000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor, Assembly Of Plural Semiconductive Substrates Each Possessing Electrical Device The Patent Description & Claims data below is from USPTO Patent Application 20060292744. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This application is a continuation of and claims the benefit of priority under 35 U.S.C. .sctn.120 from U.S. application Ser. No. 10/011,432, filed Dec. 11, 2001, now allowed, which is a continuation of U.S. Pat. No. 6,984,571, issued Jan. 10, 2006 and U.S. Pat. No. 6,500,694, issued Dec. 31, 2002 the entire contents of which are incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to three-dimensionally integrated semiconductor devices and, in particular, to semiconductor devices vertically bonded together to form three-dimensional structures. [0004] 2. Discussion of the Background [0005] The ability to integrate determines the success of the semiconductor industry. This was first demonstrated with the invention of the integrated circuit (IC). The IC essentially consists of fabrication of electronic components at the surface of the semiconductor wafer followed by interconnection of these components with metallization on top of the components. The dramatic reduction in cost and increase in performance that has resulted from this integration has had a profound economic impact. [0006] Since the invention of the IC, the semiconductor industry has experienced continued rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.) achieved. For the most part, this improvement in integration density has come from repeated reduction in minimum feature size which allow more components to be integrated in a given area. Additional improvement has come from increases in wafer size. [0007] These integration improvements are essentially two-dimensional (2-D) in nature, in that the volume occupied by the integrated components is essentially at the surface of semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvement in this 2-D integration, there are physical limits to the density which can be achieved in 2-D. One of these limits is simply the minimum size needed to make these components. Another limit is the significant increase in interconnect requirements between components as the component size is reduced. [0008] Efforts to achieve integration beyond that available with 2-D has been explored and resulted in improvement in chip memory and further semiconductor industry growth. For instance, the trench capacitor uses significant semiconductor volume below the wafer surface and allows more functionality to be achieve in a given chip area. Other efforts, directed at achieving higher levels of integration by increased use of the volume in a given chip area, have recently increased. One approach has been to iterate the integration process by adding semiconductor material on top of the interconnect metallization followed by additional interconnect metallization. Although this potentially results in more components per chip area, it suffers from other problems including significantly increased thermal budgets. In addition, this and other efforts are distinct in that they only use one substrate and then work on one surface of that substrate. Not subjecting the devices to the thermal processes involved in fabricating the interconnect would simplify and enhance the fabrication of the devices. [0009] Another problem results from the lagging of the ability to scale interconnect dimensions compared to scaling device dimensions. Ideally, one wants the critical dimension of a via to be the same as a gate dimension. However, since the scaling of vias lags the scaling of devices, integration density is limited. [0010] Further problems arise when trying to integrate different types of technologies into a single circuit or wafer. BiCMOS is one example. Typically, special processing techniques must be devised to be able to combine the technologies. Processes required for one technology often interfere with processes required for another. As a result, compromises are made. The overall development of the combined technology becomes frozen in time, making flexible integration of the technologies that are being combined very difficult if not impossible. In other words, the most advanced "best of breed" technologies are not combined and evolutions in the technologies cannot be exploited. [0011] Another problem of combining technologies is that customization must occur up front. One must first design the processing to combine the technologies and thus the limitations are built into the device. Again, one cannot easily take advantage of evolutions and improvements in technology since that requires redesigning the processing. SUMMARY OF THE INVENTION [0012] It is an object of the present invention to provide a method and device having high integration density. [0013] It is another object of the invention to provide a method and device where different types of materials may be integrated. [0014] It is a further object of the present invention to provide a method of integrating different types of devices, and a structure comprising the integrated devices. [0015] It is yet another object of the invention to provide a method and device where different types of technologies are integrated. [0016] It is a still further object of the invention to avoid or minimize the thermal budgets in interconnecting devices. [0017] It is yet another object of the invention to allow the integration of the best available technologies without making significant processing compromises. [0018] A still further object is to provide improved interconnection of bonded devices, and between devices and boards, cards and/or substrates. [0019] These and other objects may be obtained by a method of forming an integrated device including the steps of forming a first bonding material on a first semiconductor device having a first substrate, forming a second bonding material on a first element having a second substrate and directly bonding the first and second bonding materials. A portion of the first substrate may be removed to expose a remaining portion of the first semiconductor device, and the integrated device may be mounted in a package. [0020] The first semiconductor device may be connected to the package from an exposed side of the remaining portion of the first semiconductor device. The first semiconductor device may have a substrate with top and bottom sides, with an active area being formed in the top side, and the package may be connected to the first semiconductor device from the bottom side. A second element having a third substrate may be bonded to the remaining portion of the first semiconductor device, the first element may be removed or substantially removed and the semiconductor device may be connected to the package from the top side. [0021] The first semiconductor device may have a plurality of levels of interconnect, and connections may be formed to at least one of the levels of interconnect from an exposed remaining portion side. A plurality of levels of interconnect may also be formed from an exposed remaining portion side. A connection may be made directly to a device element region of the first semiconductor device. [0022] The method according to the invention may also include steps of bonding a first thermal spreading substrate to a first semiconductor device having a device substrate, removing a portion of the device substrate to expose a remaining portion of the first semiconductor device, and bonding a second thermal spreading substrate to the remaining portion of the first semiconductor. A plurality of levels of interconnect may be formed in the first semiconductor device, and connections to at least one of these levels of interconnect may be made using the first or second thermal spreading substrates. The connections to the levels of interconnect may be formed using an aerial contacting method and connections may be made directly to device element regions of the semiconductor device. Continue reading... Full patent description for Three dimensional device integration method and integrated device Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Three dimensional device integration method and integrated device patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Three dimensional device integration method and integrated device or other areas of interest. ### Previous Patent Application: Stacked die in die bga package Next Patent Application: Stacked die in die bga package Industry Class: Semiconductor device manufacturing: process ### FreshPatents.com Support Thank you for viewing the Three dimensional device integration method and integrated device patent info. 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