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Three-dimensional capacitor structureThree-dimensional capacitor structure description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070187739, Three-dimensional capacitor structure. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001]1. Field of the Invention [0002]The present invention relates to a capacitor structure, and more particularly, to a three-dimensional capacitor structure having low resistance and high matching. [0003]2. Description of the Prior Art [0004]Capacitor structures are able to store charges, and can be applied to many sorts of integrated circuits, such as RFIC and MMIC. A capacitor structure consists of two parallel electrical plates with an insulation layer between thereof. Please refer to FIG. 1. FIG. 1 is a schematic diagram of a metal-insulator-metal (MIM) capacitor structure according to the prior art. As FIG. 1 shows, the MIM capacitor structure 10 comprises a substrate 12, a first electrical plate 14 disposed on the substrate 12, a capacitor dielectric layer 16 located on the first electrical plate 14, and a second electrical plate 18 disposed on the capacitor dielectric layer 16. [0005]An inter-digitated capacitor structure has been gradually replacing the conventional MIM capacitor structure. U.S. Pat. No. 5,583,359 discloses an inter-digitated capacitor structure. Please refer to FIGS. 2-3. FIG. 2 is a schematic external diagram of a prior art inter-digitated capacitor structure 30. FIG. 3 is a schematic sectional diagram of the prior art inter-digitated capacitor structure 30, taken across sections III-III of FIG. 2. As FIGS. 2-3 show, the prior inter-digitated capacitor structure 30 is composed of a first electrode structure and a second electrode structure. The first electrode structure comprises a plurality of first metal patterns 32 stacked vertically with respect to each other. The second electrode structure comprises a plurality of second metal patterns 34 stacked vertically with respect to each other. In addition, each first metal pattern 32 comprises a first peripheral part 321 and a plurality of first finger parts 322 connected to the first peripheral part 321. Each second metal pattern 34 comprises a second peripheral part 341 and a plurality of second finger parts 342 connected to the first peripheral part 341. Furthermore, a capacitor dielectric layer 38 (not shown in FIG. 2) is disposed between each first metal pattern 32 and each second metal pattern 34. The prior inter-digitated capacitor structure 30 further comprises a plurality of first connective plugs 40 disposed among the capacitor dielectric layers 38 between the first peripheral parts 321 of each first metal pattern 32, so every first metal pattern 32 electrically connects with each other. Additionally, there are a plurality of second connective plugs 42 disposed among the capacitor dielectric layer 38 between the second peripheral parts 341 of each second metal pattern 34, so every second metal pattern 34 electrically connects with each other. [0006]As FIG. 2 shows, the first metal patterns 32 connected with each other by the first connective plugs 40 make up a first electrode structure. The second metal patterns 34 connected with each other by the second connective plugs 42 make up a second electrode structure. Furthermore, the first metal patterns 32, the second metal patterns 34, and the capacitor dielectric layer between the first metal patterns 32 and the second metal patterns 34 form the prior inter-digitated capacitor structure 30. As FIG. 3 shows, the first finger parts 322 of the first metal patterns 32 are connected to a positive voltage, and the second finger parts 342 of the second metal patterns 34 are connected to a negative voltage. [0007]The prior inter-digitated capacitor structure has another embodiment. Please refer to FIGS. 4-5. FIG. 4 is a schematic external diagram of a prior inter-digitated capacitor structure 50. FIG. 5 is a schematic sectional diagram of the prior inter-digitated capacitor structure 50, taken across sections V-V of FIG. 4. As FIGS. 4-5 show, the prior inter-digitated capacitor structure 50 consists of a first electrode structure and a second electrode structure. The first electrode structure comprises a plurality of first metal patterns 52 stacked vertically with respect to each other. The second electrode structure comprises a plurality of second metal patterns 54 stacked vertically with respect to each other. In addition, each first metal pattern 52 comprises a first peripheral part 521 and a plurality of first finger parts 522 connected with the first peripheral part 521. Each second metal pattern 54 comprises a second peripheral part 541 and a plurality of second finger parts 542 connected with the first peripheral part 541. Furthermore, between each first metal pattern 52 and each second metal pattern 54 a capacitor dielectric layer 58 (not shown in FIG. 4) is disposed. The prior inter-digitated capacitor structure 50 further comprises a plurality of first connective plugs 60 disposed among the capacitor dielectric layers 58 between the first peripheral parts 521 of each first metal pattern 52, so every first metal pattern 52 electrically connects with each other. Additionally a plurality of second connective plugs 62 are disposed among the capacitor dielectric layers 58 between the second peripheral parts 541 of each second metal pattern 54, so every second metal pattern 54 electrically connects with each other. [0008]As FIGS. 4-5 show, the difference between the inter-digitated capacitor structure of FIGS. 2-3 and the inter-digitated capacitor structure of FIGS. 4-5 is that the first electrode structure of the inter-digitated capacitor structure 50 is mismatched with the second electrode structure. Therefore, a first finger part 522 combined with four second finger parts 542 that are respectively adjacent to the first finger part 522 will form a capacitor. [0009]Compared with the MIM capacitor structure, the inter-digitated capacitor structure has better capacitance while it maintains the same size. The capacitance, however, is not the only consideration of the capacitor structure. Because the finger parts of the inter-digitated capacitor structure have longer lengths, and the finger parts are only connected electrically on one side, the resistance is correspondingly high, and the matching of the inter-digitated capacitor structure needs to be improved. SUMMARY OF THE INVENTION [0010]It is therefore one objective of the claimed invention to provide a three-dimensional capacitor structure having a low resistance, and high matching. [0011]In one aspect of the claimed invention a three-dimensional capacitor structure is provided. The three-dimensional capacitor structure has a first conductive layer, a second conductive layer disposed above the first conductive layer, and a plug layer disposed therebetween. The first conductive layer is divided into a plurality of grid units arranged in a matrix. The first conductive layer comprises a plurality of first conductive grids and a plurality of first circular holes. In the grid units of odd rows, the first conductive grids are disposed in the grid units of odd columns, and the first circular holes are disposed in the grid units of even columns. In the grid units of even rows, the first conductive grids are disposed in the grid units of even columns, and the first circular holes are disposed in the grid units of odd columns. A centre of each first circular hole further comprises a first conductive island, and each first conductive island is not connected electrically with the first conductive grids. The second conductive layer is divided into a plurality of grid units corresponding to the grid units of the first conductive layer. The second conductive layer comprises a plurality of second conductive grids and a plurality of second circular holes. In the grid units of odd rows, the second conductive grids are disposed in the grid units of even columns, and the second circular holes are disposed in the grid units of odd columns. In the grid units of the even rows, the second conductive grids are disposed in the grid units of odd columns, and the second circular holes are disposed in the gird units of even columns. A centre of the second circular holes further comprises a second conductive island, and each second conductive island being not connected electrically with the second conductive grids. The plug layer comprises a plurality of plugs, where each plug is located individually between each first conductive island and each second conductive grid, and between each first conductive grid and the second conductive island. [0012]These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0013]FIG. 1 is a schematic diagram of a metal-insulator-metal (MIM) capacitor structure according to the prior art. [0014]FIG. 2 is a schematic external diagram of a prior inter-digitated capacitor structure. [0015]FIG. 3 is a schematic sectional diagram of the prior inter-digitated capacitor structure, taken across section III-III of FIG. 2. [0016]FIG. 4 is a schematic external diagram of a prior inter-digitated capacitor structure. [0017]FIG. 5 is a schematic sectional diagram of the prior inter-digitated capacitor structure, taken across section V-V of FIG. 4. [0018]FIGS. 6-8 are schematic layout diagrams of a three-dimensional capacitor structure of an embodiment according to the present invention. [0019]FIG. 9 is a schematic diagram of a three-dimensional capacitor structure of an embodiment according to the present invention. [0020]FIG. 10 is a schematic sectional diagram of the three-dimensional capacitor structure, taken across section X-X of FIG. 9. DETAILED DESCRIPTION Continue reading about Three-dimensional capacitor structure... Full patent description for Three-dimensional capacitor structure Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Three-dimensional capacitor structure patent application. Patent Applications in related categories: 20090289292 - Semiconductor memory device and method for forming capacitor thereof - A semiconductor device that is capable of preventing a storage node bunker defect or a defect due to loss of a barrier layer, and a method for forming a capacitor thereof. The semiconductor memory device includes a contact hole formed in an interlayer dielectric layer on a semiconductor substrate; a ... ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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